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      1 # REQUIRES: mips
      2 # Check generation of MIPS specific ELF header flags.
      3 
      4 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
      5 # RUN:         %S/Inputs/mips-dynamic.s -o %t-so.o
      6 # RUN: ld.lld %t-so.o --gc-sections -shared -o %t.so
      7 # RUN: llvm-readobj -h --mips-abi-flags %t.so | FileCheck -check-prefix=SO %s
      8 
      9 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t.o
     10 # RUN: ld.lld %t.o -o %t.exe
     11 # RUN: llvm-readobj -h --mips-abi-flags %t.exe | FileCheck -check-prefix=EXE %s
     12 
     13 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
     14 # RUN:         -mcpu=mips32r2 %s -o %t-r2.o
     15 # RUN: ld.lld %t-r2.o -o %t-r2.exe
     16 # RUN: llvm-readobj -h --mips-abi-flags %t-r2.exe \
     17 # RUN:   | FileCheck -check-prefix=EXE-R2 %s
     18 
     19 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
     20 # RUN:         -mcpu=mips32r2 %s -o %t-r2.o
     21 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
     22 # RUN:         -mcpu=mips32r5 %S/Inputs/mips-dynamic.s -o %t-r5.o
     23 # RUN: ld.lld %t-r2.o %t-r5.o -o %t-r5.exe
     24 # RUN: llvm-readobj -h --mips-abi-flags %t-r5.exe \
     25 # RUN:   | FileCheck -check-prefix=EXE-R5 %s
     26 
     27 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
     28 # RUN:         -mcpu=mips32r6 %s -o %t-r6.o
     29 # RUN: ld.lld %t-r6.o -o %t-r6.exe
     30 # RUN: llvm-readobj -h --mips-abi-flags %t-r6.exe \
     31 # RUN:   | FileCheck -check-prefix=EXE-R6 %s
     32 
     33 # RUN: llvm-mc -filetype=obj -triple=mips64-unknown-linux \
     34 # RUN:         -position-independent -mcpu=octeon %s -o %t.o
     35 # RUN: ld.lld %t.o -o %t.exe
     36 # RUN: llvm-readobj -h --mips-abi-flags %t.exe \
     37 # RUN:   | FileCheck -check-prefix=OCTEON %s
     38 
     39 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t.o
     40 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
     41 # RUN:         -mattr=micromips %S/Inputs/mips-fpic.s -o %t-mm.o
     42 # RUN: ld.lld %t.o %t-mm.o -o %t.exe
     43 # RUN: llvm-readobj -h --mips-abi-flags %t.exe | FileCheck -check-prefix=MICRO %s
     44 
     45   .text
     46   .globl  __start
     47 __start:
     48   nop
     49 
     50 # SO:      Flags [
     51 # SO-NEXT:   EF_MIPS_ABI_O32
     52 # SO-NEXT:   EF_MIPS_ARCH_32
     53 # SO-NEXT:   EF_MIPS_CPIC
     54 # SO-NEXT:   EF_MIPS_PIC
     55 # SO-NEXT: ]
     56 # SO:      MIPS ABI Flags {
     57 # SO-NEXT:   Version: 0
     58 # SO-NEXT:   ISA: MIPS32
     59 # SO-NEXT:   ISA Extension: None
     60 # SO-NEXT:   ASEs [
     61 # SO-NEXT:   ]
     62 # SO-NEXT:   FP ABI: Hard float (double precision)
     63 # SO-NEXT:   GPR size: 32
     64 # SO-NEXT:   CPR1 size: 32
     65 # SO-NEXT:   CPR2 size: 0
     66 # SO-NEXT:   Flags 1 [
     67 # SO-NEXT:     ODDSPREG
     68 # SO-NEXT:   ]
     69 # SO-NEXT:   Flags 2: 0x0
     70 # SO-NEXT: }
     71 
     72 # EXE:      Flags [
     73 # EXE-NEXT:   EF_MIPS_ABI_O32
     74 # EXE-NEXT:   EF_MIPS_ARCH_32
     75 # EXE-NEXT:   EF_MIPS_CPIC
     76 # EXE-NEXT: ]
     77 # EXE:      MIPS ABI Flags {
     78 # EXE-NEXT:   Version: 0
     79 # EXE-NEXT:   ISA: MIPS32
     80 # EXE-NEXT:   ISA Extension: None
     81 # EXE-NEXT:   ASEs [
     82 # EXE-NEXT:   ]
     83 # EXE-NEXT:   FP ABI: Hard float (double precision)
     84 # EXE-NEXT:   GPR size: 32
     85 # EXE-NEXT:   CPR1 size: 32
     86 # EXE-NEXT:   CPR2 size: 0
     87 # EXE-NEXT:   Flags 1 [
     88 # EXE-NEXT:     ODDSPREG
     89 # EXE-NEXT:   ]
     90 # EXE-NEXT:   Flags 2: 0x0
     91 # EXE-NEXT: }
     92 
     93 # EXE-R2:      Flags [
     94 # EXE-R2-NEXT:   EF_MIPS_ABI_O32
     95 # EXE-R2-NEXT:   EF_MIPS_ARCH_32R2
     96 # EXE-R2-NEXT:   EF_MIPS_CPIC
     97 # EXE-R2-NEXT: ]
     98 # EXE-R2:      MIPS ABI Flags {
     99 # EXE-R2-NEXT:   Version: 0
    100 # EXE-R2-NEXT:   ISA: MIPS32r2
    101 # EXE-R2-NEXT:   ISA Extension: None
    102 # EXE-R2-NEXT:   ASEs [
    103 # EXE-R2-NEXT:   ]
    104 # EXE-R2-NEXT:   FP ABI: Hard float (double precision)
    105 # EXE-R2-NEXT:   GPR size: 32
    106 # EXE-R2-NEXT:   CPR1 size: 32
    107 # EXE-R2-NEXT:   CPR2 size: 0
    108 # EXE-R2-NEXT:   Flags 1 [
    109 # EXE-R2-NEXT:     ODDSPREG
    110 # EXE-R2-NEXT:   ]
    111 # EXE-R2-NEXT:   Flags 2: 0x0
    112 # EXE-R2-NEXT: }
    113 
    114 # EXE-R5:      Flags [
    115 # EXE-R5-NEXT:   EF_MIPS_ABI_O32
    116 # EXE-R5-NEXT:   EF_MIPS_ARCH_32R2
    117 # EXE-R5-NEXT:   EF_MIPS_CPIC
    118 # EXE-R5-NEXT: ]
    119 # EXE-R5:      MIPS ABI Flags {
    120 # EXE-R5-NEXT:   Version: 0
    121 # EXE-R5-NEXT:   ISA: MIPS32r5
    122 # EXE-R5-NEXT:   ISA Extension: None
    123 # EXE-R5-NEXT:   ASEs [
    124 # EXE-R5-NEXT:   ]
    125 # EXE-R5-NEXT:   FP ABI: Hard float (double precision)
    126 # EXE-R5-NEXT:   GPR size: 32
    127 # EXE-R5-NEXT:   CPR1 size: 32
    128 # EXE-R5-NEXT:   CPR2 size: 0
    129 # EXE-R5-NEXT:   Flags 1 [
    130 # EXE-R5-NEXT:     ODDSPREG
    131 # EXE-R5-NEXT:   ]
    132 # EXE-R5-NEXT:   Flags 2: 0x0
    133 # EXE-R5-NEXT: }
    134 
    135 # EXE-R6:      Flags [
    136 # EXE-R6-NEXT:   EF_MIPS_ABI_O32
    137 # EXE-R6-NEXT:   EF_MIPS_ARCH_32R6
    138 # EXE-R6-NEXT:   EF_MIPS_CPIC
    139 # EXE-R6-NEXT:   EF_MIPS_NAN2008
    140 # EXE-R6-NEXT: ]
    141 # EXE-R6:      MIPS ABI Flags {
    142 # EXE-R6-NEXT:   Version: 0
    143 # EXE-R6-NEXT:   ISA: MIPS32
    144 # EXE-R6-NEXT:   ISA Extension: None
    145 # EXE-R6-NEXT:   ASEs [
    146 # EXE-R6-NEXT:   ]
    147 # EXE-R6-NEXT:   FP ABI: Hard float (32-bit CPU, 64-bit FPU)
    148 # EXE-R6-NEXT:   GPR size: 32
    149 # EXE-R6-NEXT:   CPR1 size: 64
    150 # EXE-R6-NEXT:   CPR2 size: 0
    151 # EXE-R6-NEXT:   Flags 1 [
    152 # EXE-R6-NEXT:     ODDSPREG
    153 # EXE-R6-NEXT:   ]
    154 # EXE-R6-NEXT:   Flags 2: 0x0
    155 # EXE-R6-NEXT: }
    156 
    157 # OCTEON:      Flags [
    158 # OCTEON-NEXT:   EF_MIPS_ARCH_64R2
    159 # OCTEON-NEXT:   EF_MIPS_CPIC
    160 # OCTEON-NEXT:   EF_MIPS_MACH_OCTEON
    161 # OCTEON-NEXT:   EF_MIPS_PIC
    162 # OCTEON-NEXT: ]
    163 # OCTEON:      MIPS ABI Flags {
    164 # OCTEON-NEXT:   Version: 0
    165 # OCTEON-NEXT:   ISA: MIPS64r2
    166 # OCTEON-NEXT:   ISA Extension: Cavium Networks Octeon
    167 # OCTEON-NEXT:   ASEs [
    168 # OCTEON-NEXT:   ]
    169 # OCTEON-NEXT:   FP ABI: Hard float (double precision)
    170 # OCTEON-NEXT:   GPR size: 64
    171 # OCTEON-NEXT:   CPR1 size: 64
    172 # OCTEON-NEXT:   CPR2 size: 0
    173 # OCTEON-NEXT:   Flags 1 [
    174 # OCTEON-NEXT:     ODDSPREG
    175 # OCTEON-NEXT:   ]
    176 # OCTEON-NEXT:   Flags 2: 0x0
    177 # OCTEON-NEXT: }
    178 
    179 # MICRO:      Flags [
    180 # MICRO-NEXT:   EF_MIPS_ABI_O32
    181 # MICRO-NEXT:   EF_MIPS_ARCH_32
    182 # MICRO-NEXT:   EF_MIPS_CPIC
    183 # MICRO-NEXT:   EF_MIPS_MICROMIPS
    184 # MICRO-NEXT: ]
    185 # MICRO:      MIPS ABI Flags {
    186 # MICRO-NEXT:   Version: 0
    187 # MICRO-NEXT:   ISA: MIPS32
    188 # MICRO-NEXT:   ISA Extension: None
    189 # MICRO-NEXT:   ASEs [
    190 # MICRO-NEXT:     microMIPS
    191 # MICRO-NEXT:   ]
    192 # MICRO-NEXT:   FP ABI: Hard float (double precision)
    193 # MICRO-NEXT:   GPR size: 32
    194 # MICRO-NEXT:   CPR1 size: 32
    195 # MICRO-NEXT:   CPR2 size: 0
    196 # MICRO-NEXT:   Flags 1 [
    197 # MICRO-NEXT:     ODDSPREG
    198 # MICRO-NEXT:   ]
    199 # MICRO-NEXT:   Flags 2: 0x0
    200 # MICRO-NEXT: }