riscv workarounds for llvm not having good asm integration

2019-07-18 15:20:58 -04:00
parent a3854d042e
commit 03a3b1ca39
4 changed files with 99 additions and 44 deletions
--- a/src/codegen.cpp
+++ b/src/codegen.cpp
@@ -8148,6 +8148,10 @@ static void init(CodeGen *g) {
            target_specific_cpu_args = ZigLLVMGetHostCPUName();
            target_specific_features = ZigLLVMGetNativeFeatures();
        }
+    } else if (target_is_riscv(g->zig_target)) {
+        // TODO https://github.com/ziglang/zig/issues/2883
+        target_specific_cpu_args = "";
+        target_specific_features = "+a";
    } else {
        target_specific_cpu_args = "";
        target_specific_features = "";