llvm: Disable the machine outliner pass on RISC-V

src/codegen/llvm.zig

@@ -1068,6 +1068,9 @@ pub const Object = struct {
                 .full => .FullPreLink,
             },
             .allow_fast_isel = true,
+            // LLVM's RISC-V backend for some reason enables the machine outliner by default even
+            // though it's clearly not ready and produces multiple miscompilations in our std tests.
+            .allow_machine_outliner = !comp.root_mod.resolved_target.result.cpu.arch.isRISCV(),
             .asm_filename = null,
             .bin_filename = options.bin_path,
             .llvm_ir_filename = options.post_ir_path,

src/codegen/llvm/bindings.zig

@@ -92,6 +92,7 @@ pub const TargetMachine = opaque {
         sancov: bool,
         lto: LtoPhase,
         allow_fast_isel: bool,
+        allow_machine_outliner: bool,
         asm_filename: ?[*:0]const u8,
         bin_filename: ?[*:0]const u8,
         llvm_ir_filename: ?[*:0]const u8,