spirv: assembler
spirv: introduce SpvModule.Fn to generate function code into spirv: assembler error message setup spirv: runtime spec info spirv: inline assembly tokenizer spirv: inline assembly lhs result/opcode parsing spirv: forgot to fmt spirv: tokenize opcodes and assigned result-ids spirv: operand parsing setup spirv: assembler string literals spirv: assembler integer literals spirv: assembler value enums spirv: assembler bit masks spirv: update assembler to new asm air format spirv: target 1.5 for now Current vulkan sdk version (1.3.204) ships spirv tools targetting 1.5, and so these do not work with binaries targetting 1.6 yet. In the future, this version number should be decided by the target. spirv: store operands in flat arraylist. Instead of having dedicated Operand variants for variadic operands, just flatten them and store them in the normal inst.operands list. This is a little simpler, but is not easily decodable in the operand data representation. spirv: parse variadic assembly operands spirv: improve assembler result-id tokenization spirv: begin instruction processing spirv: only remove decl if it was actually allocated spirv: work around weird miscompilation Seems like there are problems with switch in anonymous struct literals. spirv: begin resolving some types in assembler spirv: improve instruction processing spirv: rename some types + process OpTypeInt spirv: process OpTypeVector spirv: process OpTypeMatrix and OpTypeSampler spirv: add opcode class to spec, remove @exclude'd instructions spirv: process more type instructions spirv: OpTypeFunction spirv: OpTypeOpaque spirv: parse LiteralContextDependentNumber operands spirv: emit assembly instruction into right section spirv: parse OpPhi parameters spirv: inline assembly inputs spirv: also copy air types spirv: inline assembly outputs spirv: spir-v address spaces spirv: basic vector constants/types and shuffle spirv: assembler OpTypeImage spirv: some stuff spirv: remove spirv address spaces for now
This commit is contained in:
Robin Voetter
@@ -116,6 +116,31 @@ fn render(writer: anytype, allocator: Allocator, registry: g.CoreRegistry) !void
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\\pub const PairIdRefLiteralInteger = struct { target: IdRef, member: LiteralInteger };
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\\pub const PairIdRefIdRef = [2]IdRef;
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\\
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\\pub const Quantifier = enum {
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\\ required,
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\\ optional,
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\\ variadic,
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\\};
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\\
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\\pub const Operand = struct {
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\\ kind: OperandKind,
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\\ quantifier: Quantifier,
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\\};
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\\
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\\pub const OperandCategory = enum {
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\\ bit_enum,
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\\ value_enum,
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\\ id,
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\\ literal,
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\\ composite,
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\\};
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\\
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\\pub const Enumerant = struct {
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\\ name: []const u8,
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\\ value: Word,
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\\ parameters: []const OperandKind,
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\\};
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\\
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\\
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);
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@@ -123,14 +148,118 @@ fn render(writer: anytype, allocator: Allocator, registry: g.CoreRegistry) !void
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\\pub const version = Version{{ .major = {}, .minor = {}, .patch = {} }};
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\\pub const magic_number: Word = {s};
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\\
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\\
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,
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.{ registry.major_version, registry.minor_version, registry.revision, registry.magic_number },
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);
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const extended_structs = try extendedStructs(allocator, registry.operand_kinds);
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try renderClass(writer, allocator, registry.instructions);
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try renderOperandKind(writer, registry.operand_kinds);
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try renderOpcodes(writer, allocator, registry.instructions, extended_structs);
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try renderOperandKinds(writer, allocator, registry.operand_kinds, extended_structs);
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}
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fn renderClass(writer: anytype, allocator: Allocator, instructions: []const g.Instruction) !void {
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var class_map = std.StringArrayHashMap(void).init(allocator);
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for (instructions) |inst| {
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if (std.mem.eql(u8, inst.class.?, "@exclude")) {
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continue;
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}
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try class_map.put(inst.class.?, {});
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}
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try writer.writeAll("pub const Class = enum {\n");
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for (class_map.keys()) |class| {
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try renderInstructionClass(writer, class);
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try writer.writeAll(",\n");
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}
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try writer.writeAll("};\n");
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}
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fn renderInstructionClass(writer: anytype, class: []const u8) !void {
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// Just assume that these wont clobber zig builtin types.
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var prev_was_sep = true;
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for (class) |c| {
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switch (c) {
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'-', '_' => prev_was_sep = true,
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else => if (prev_was_sep) {
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try writer.writeByte(std.ascii.toUpper(c));
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prev_was_sep = false;
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} else {
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try writer.writeByte(std.ascii.toLower(c));
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},
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}
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}
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}
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fn renderOperandKind(writer: anytype, operands: []const g.OperandKind) !void {
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try writer.writeAll("pub const OperandKind = enum {\n");
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for (operands) |operand| {
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try writer.print("{},\n", .{std.zig.fmtId(operand.kind)});
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}
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try writer.writeAll(
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\\
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\\pub fn category(self: OperandKind) OperandCategory {
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\\return switch (self) {
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\\
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);
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for (operands) |operand| {
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const cat = switch (operand.category) {
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.BitEnum => "bit_enum",
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.ValueEnum => "value_enum",
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.Id => "id",
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.Literal => "literal",
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.Composite => "composite",
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};
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try writer.print(".{} => .{s},\n", .{ std.zig.fmtId(operand.kind), cat });
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}
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try writer.writeAll(
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\\};
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\\}
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\\pub fn enumerants(self: OperandKind) []const Enumerant {
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\\return switch (self) {
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\\
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);
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for (operands) |operand| {
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switch (operand.category) {
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.BitEnum, .ValueEnum => {},
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else => {
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try writer.print(".{} => unreachable,\n", .{std.zig.fmtId(operand.kind)});
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continue;
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},
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}
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try writer.print(".{} => &[_]Enumerant{{", .{std.zig.fmtId(operand.kind)});
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for (operand.enumerants.?) |enumerant| {
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if (enumerant.value == .bitflag and std.mem.eql(u8, enumerant.enumerant, "None")) {
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continue;
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}
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try renderEnumerant(writer, enumerant);
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try writer.writeAll(",");
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}
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try writer.writeAll("},\n");
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}
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try writer.writeAll("};\n}\n};\n");
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}
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fn renderEnumerant(writer: anytype, enumerant: g.Enumerant) !void {
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try writer.print(".{{.name = \"{s}\", .value = ", .{enumerant.enumerant});
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switch (enumerant.value) {
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.bitflag => |flag| try writer.writeAll(flag),
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.int => |int| try writer.print("{}", .{int}),
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}
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try writer.writeAll(", .parameters = &[_]OperandKind{");
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for (enumerant.parameters) |param, i| {
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if (i != 0)
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try writer.writeAll(", ");
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// Note, param.quantifier will always be one.
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try writer.print(".{}", .{std.zig.fmtId(param.kind)});
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}
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try writer.writeAll("}}");
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}
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fn renderOpcodes(
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writer: anytype,
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allocator: Allocator,
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@@ -144,6 +273,9 @@ fn renderOpcodes(
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try aliases.ensureTotalCapacity(instructions.len);
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for (instructions) |inst, i| {
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if (std.mem.eql(u8, inst.class.?, "@exclude")) {
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continue;
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}
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const result = inst_map.getOrPutAssumeCapacity(inst.opcode);
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if (!result.found_existing) {
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result.value_ptr.* = i;
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@@ -192,6 +324,47 @@ fn renderOpcodes(
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const inst = instructions[i];
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try renderOperand(writer, .instruction, inst.opname, inst.operands, extended_structs);
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}
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try writer.writeAll(
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\\};
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\\}
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\\pub fn operands(self: Opcode) []const Operand {
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\\return switch (self) {
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\\
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);
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for (instructions_indices) |i| {
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const inst = instructions[i];
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try writer.print(".{} => &[_]Operand{{", .{std.zig.fmtId(inst.opname)});
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for (inst.operands) |operand| {
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const quantifier = if (operand.quantifier) |q|
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switch (q) {
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.@"?" => "optional",
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.@"*" => "variadic",
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}
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else
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"required";
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try writer.print(".{{.kind = .{s}, .quantifier = .{s}}},", .{ operand.kind, quantifier });
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}
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try writer.writeAll("},\n");
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}
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try writer.writeAll(
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\\};
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\\}
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\\pub fn class(self: Opcode) Class {
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\\return switch (self) {
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\\
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);
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for (instructions_indices) |i| {
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const inst = instructions[i];
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try writer.print(".{} => .", .{std.zig.fmtId(inst.opname)});
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try renderInstructionClass(writer, inst.class.?);
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try writer.writeAll(",\n");
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}
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try writer.writeAll("};\n}\n};\n");
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}
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@@ -298,7 +471,7 @@ fn renderBitEnum(
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for (enumerants) |enumerant, i| {
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if (enumerant.value != .bitflag) return error.InvalidRegistry;
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const value = try parseHexInt(enumerant.value.bitflag);
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if (@popCount(value) == 0) {
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if (value == 0) {
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continue; // Skip 'none' items
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}
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