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stage2: change max int align from 8 to 16 for more ISAs

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These targets now have a similar disagreement with LLVM about the
alignment of 128-bit integers as x86_64:
 * riscv64
 * powerpc64
 * powerpc64le
 * mips64
 * mips64el
 * sparcv9

See #2987
This commit is contained in:
Andrew Kelley
2022-05-04 19:11:02 -07:00
parent af7e945a7d
commit 0bebb688fb
2 changed files with 21 additions and 21 deletions
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12
test/behavior/align.zig
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@@ -77,18 +77,12 @@ test "alignment and size of structs with 128-bit fields" {
.hexagon,
.mips,
.mipsel,
.mips64,
.mips64el,
.powerpc,
.powerpcle,
.powerpc64,
.powerpc64le,
.r600,
.amdgcn,
.riscv32,
.riscv64,
.sparc,
.sparcv9,
.sparcel,
.s390x,
.lanai,
@@ -134,6 +128,12 @@ test "alignment and size of structs with 128-bit fields" {
},
},
.mips64,
.mips64el,
.powerpc64,
.powerpc64le,
.riscv64,
.sparcv9,
.x86_64,
.aarch64,
.aarch64_be,