riscv: implement sub-byte addition

2024-07-15 04:01:44 -07:00
parent 81ca3a1d59
commit 1820f44104
4 changed files with 73 additions and 14 deletions
--- a/test/behavior/array.zig
+++ b/test/behavior/array.zig
@@ -773,8 +773,6 @@ test "array init with no result pointer sets field result types" {
 }

 test "runtime side-effects in comptime-known array init" {
-    if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
-
    var side_effects: u4 = 0;
    const init = [4]u4{
        blk: {