riscv: clean up and unify encoding logic
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@@ -539,10 +539,10 @@ set(ZIG_STAGE2_SOURCES
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src/arch/riscv64/bits.zig
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src/arch/riscv64/CodeGen.zig
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src/arch/riscv64/Emit.zig
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src/arch/riscv64/encoder.zig
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src/arch/riscv64/Encoding.zig
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src/arch/riscv64/encoding.zig
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src/arch/riscv64/Lower.zig
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src/arch/riscv64/Mir.zig
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src/arch/riscv64/mnem.zig
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src/arch/sparc64/CodeGen.zig
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src/arch/sparc64/Emit.zig
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src/arch/sparc64/Mir.zig
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