motiejus/zig

commit 1f2e3b39ae8ddd4ae7a969daa8c56949de81295e (tree)
parent 1fcabe0bfcad7bd981ce883a2c407f2b023320ad
Author: Alex Rønne Petersen <alex@alexrp.com>
Date:   Mon, 30 Jun 2025 07:04:35 +0200

test: Disable vector division operators on RISC-V with vector support

https://github.com/ziglang/zig/issues/24301

Diffstat:
M
test/behavior/vector.zig
 | 
1
+

1 file changed, 1 insertion(+), 0 deletions(-)
diff --git a/test/behavior/vector.zig b/test/behavior/vector.zig
@@ -560,6 +560,7 @@ test "vector division operators" {
     if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
     if (builtin.zig_backend == .stage2_spirv) return error.SkipZigTest;
+    if (comptime builtin.cpu.has(.riscv, .v) and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/24301
 
     const S = struct {
         fn doTheTestDiv(comptime T: type, x: @Vector(4, T), y: @Vector(4, T)) !void {