zig

commit 26ce82d98efce4847307c0b73d1765be7a104256 (tree)
parent 3bf008a3d07b2d9f91964141e1fb33d3fab82390
Author: David Rubin <daviru007@icloud.com>
Date:   Fri, 29 Mar 2024 06:59:32 -0700

riscv: correctly derefence `load_symbol` in genSetReg

Diffstat:
M
src/arch/riscv64/CodeGen.zig
 | 
21
+++++++++++++++++++++

1 file changed, 21 insertions(+), 0 deletions(-)
diff --git a/src/arch/riscv64/CodeGen.zig b/src/arch/riscv64/CodeGen.zig
@@ -3535,6 +3535,27 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, src_mcv: MCValue) InnerError!
                     }),
                 },
             });
+
+            const tag: Mir.Inst.Tag = switch (abi_size) {
+                1 => .lb,
+                2 => .lh,
+                4 => .lw,
+                8 => .ld,
+                else => return self.fail("TODO: genSetReg for size {d}", .{abi_size}),
+            };
+
+            _ = try self.addInst(.{
+                .tag = tag,
+                .data = .{
+                    .i_type = .{
+                        .rd = reg,
+                        .rs1 = reg,
+                        .imm12 = 0,
+                    },
+                },
+            });
+
+            unreachable;
         },
         .air_ref => |ref| try self.genSetReg(ty, reg, try self.resolveInst(ref)),
         .indirect => |reg_off| {