motiejus/zig

commit 3d7fb4f204940875e7cd9e4dd82f28c464f688e8 (tree)
parent fd2d4507c86057bf43ae2198edeb3ebddfa6caca
Author: Alex Rønne Petersen <alex@alexrp.com>
Date:   Mon, 30 Jun 2025 06:59:06 +0200

std.zig.system.linux: Add detection for some extra RISC-V CPUs

Diffstat:
M
lib/std/zig/system/linux.zig
 | 
2
++

1 file changed, 2 insertions(+), 0 deletions(-)
diff --git a/lib/std/zig/system/linux.zig b/lib/std/zig/system/linux.zig
@@ -76,9 +76,11 @@ const RiscvCpuinfoImpl = struct {
 
     const cpu_names = .{
         .{ "sifive,u54", &Target.riscv.cpu.sifive_u54 },
+        .{ "sifive,u54-mc", &Target.riscv.cpu.sifive_u54 },
         .{ "sifive,u7", &Target.riscv.cpu.sifive_7_series },
         .{ "sifive,u74", &Target.riscv.cpu.sifive_u74 },
         .{ "sifive,u74-mc", &Target.riscv.cpu.sifive_u74 },
+        .{ "spacemit,x60", &Target.riscv.cpu.spacemit_x60 },
     };
 
     fn line_hook(self: *RiscvCpuinfoImpl, key: []const u8, value: []const u8) !bool {