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stage2: move float types to InternPool

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This commit is contained in:
Andrew Kelley
2023-05-03 16:07:36 -07:00
parent aa1bb5517d
commit 4cd8a40b3b
6 changed files with 403 additions and 256 deletions
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14
src/codegen/c/type.zig
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@@ -1412,13 +1412,13 @@ pub const CType = extern union {
.Bool => self.init(.bool),
.Float => self.init(switch (ty.tag()) {
.f16 => .zig_f16,
.f32 => .zig_f32,
.f64 => .zig_f64,
.f80 => .zig_f80,
.f128 => .zig_f128,
.c_longdouble => .zig_c_longdouble,
.Float => self.init(switch (ty.ip_index) {
.f16_type => .zig_f16,
.f32_type => .zig_f32,
.f64_type => .zig_f64,
.f80_type => .zig_f80,
.f128_type => .zig_f128,
.c_longdouble_type => .zig_c_longdouble,
else => unreachable,
}),

10
src/codegen/llvm.zig
View File

@@ -10932,7 +10932,7 @@ const ParamTypeIterator = struct {
.riscv32, .riscv64 => {
it.zig_index += 1;
it.llvm_index += 1;
if (ty.tag() == .f16) {
if (ty.ip_index == .f16_type) {
return .as_u16;
}
switch (riscv_c_abi.classifyType(ty, mod)) {
@@ -11264,10 +11264,10 @@ fn backendSupportsF128(target: std.Target) bool {
/// LLVM does not support all relevant intrinsics for all targets, so we
/// may need to manually generate a libc call
fn intrinsicsAllowed(scalar_ty: Type, target: std.Target) bool {
return switch (scalar_ty.tag()) {
.f16 => backendSupportsF16(target),
.f80 => (target.c_type_bit_size(.longdouble) == 80) and backendSupportsF80(target),
.f128 => (target.c_type_bit_size(.longdouble) == 128) and backendSupportsF128(target),
return switch (scalar_ty.ip_index) {
.f16_type => backendSupportsF16(target),
.f80_type => (target.c_type_bit_size(.longdouble) == 80) and backendSupportsF80(target),
.f128_type => (target.c_type_bit_size(.longdouble) == 128) and backendSupportsF128(target),
else => true,
};
}