riscv: fix register clobber in certain edge cases

This commit is contained in:
David Rubin
2024-05-10 23:21:53 -07:00
parent 381a1043eb
commit 7ed2f2156f
4 changed files with 12 additions and 16 deletions

View File

@@ -216,7 +216,6 @@ fn poll() void {
test "switch on global mutable var isn't constant-folded" {
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
while (state < 2) {
poll();