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Correct expected/actual parameter order of some assertions

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This commit is contained in:
Carl Åstholm
2024-01-01 17:37:32 +01:00
parent d7b36503ca
commit 85869f8225
4 changed files with 19 additions and 19 deletions
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6
test/c_abi/main.zig
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@@ -946,7 +946,7 @@ test "DC: C returns to Zig" {
if (comptime builtin.cpu.arch.isRISCV()) return error.SkipZigTest;
if (comptime builtin.cpu.arch.isPPC()) return error.SkipZigTest;
if (comptime builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
try expectEqual(c_ret_DC(), DC{ .v1 = -0.25, .v2 = 15 });
try expectEqual(DC{ .v1 = -0.25, .v2 = 15 }, c_ret_DC());
}
pub extern fn c_assert_DC(lv: DC) c_int;
@@ -998,7 +998,7 @@ test "CFF: C returns to Zig" {
if (comptime builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
if (comptime builtin.cpu.arch.isPPC()) return error.SkipZigTest;
if (comptime builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
try expectEqual(c_ret_CFF(), CFF{ .v1 = 39, .v2 = 0.875, .v3 = 1.0 });
try expectEqual(CFF{ .v1 = 39, .v2 = 0.875, .v3 = 1.0 }, c_ret_CFF());
}
pub extern fn c_assert_CFF(lv: CFF) c_int;
pub extern fn c_assert_ret_CFF() c_int;
@@ -1045,7 +1045,7 @@ test "PD: C returns to Zig" {
if (comptime builtin.cpu.arch.isMIPS() and builtin.mode != .Debug) return error.SkipZigTest;
if (comptime builtin.cpu.arch.isPPC()) return error.SkipZigTest;
if (comptime builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
try expectEqual(c_ret_PD(), PD{ .v1 = null, .v2 = 0.5 });
try expectEqual(PD{ .v1 = null, .v2 = 0.5 }, c_ret_PD());
}
pub extern fn c_assert_PD(lv: PD) c_int;
pub extern fn c_assert_ret_PD() c_int;