zig

commit 88b49ed00d6d2efb5b523ab15cbf8ffb37383c56 (tree)
parent 077b003c50065a8b193dcad793ca5c4474222af6
Author: Ivan Velickovic <i.velickovic@unsw.edu.au>
Date:   Thu, 15 Dec 2022 19:16:32 +1100

std.leb128: Re-enable test for riscv64

These were previously disabled due to a LLVM 14 regression, see
https://github.com/ziglang/zig/issues/12031 for more details. This has been fixed
in LLVM 15.

Diffstat:
M
lib/std/leb128.zig
 | 
10
----------

1 file changed, 0 insertions(+), 10 deletions(-)
diff --git a/lib/std/leb128.zig b/lib/std/leb128.zig
@@ -347,11 +347,6 @@ fn test_write_leb128(value: anytype) !void {
 }
 
 test "serialize unsigned LEB128" {
-    if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .riscv64) {
-        // https://github.com/ziglang/zig/issues/12031
-        return error.SkipZigTest;
-    }
-
     const max_bits = 18;
 
     comptime var t = 0;
@@ -366,11 +361,6 @@ test "serialize unsigned LEB128" {
 }
 
 test "serialize signed LEB128" {
-    if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .riscv64) {
-        // https://github.com/ziglang/zig/issues/12031
-        return error.SkipZigTest;
-    }
-
     // explicitly test i0 because starting `t` at 0
     // will break the while loop
     try test_write_leb128(@as(i0, 0));