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std.Target: Introduce Cpu convenience functions for feature tests.

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Before:

* std.Target.arm.featureSetHas(target.cpu.features, .has_v7)
* std.Target.x86.featureSetHasAny(target.cpu.features, .{ .sse, .avx, .cmov })
* std.Target.wasm.featureSetHasAll(target.cpu.features, .{ .atomics, .bulk_memory })

After:

* target.cpu.has(.arm, .has_v7)
* target.cpu.hasAny(.x86, &.{ .sse, .avx, .cmov })
* target.cpu.hasAll(.wasm, &.{ .atomics, .bulk_memory })
This commit is contained in:
Alex Rønne Petersen
2025-02-18 05:25:36 +01:00
parent 14873f9a34
commit 9d534790eb
53 changed files with 373 additions and 393 deletions
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14
src/codegen/spirv/Module.zig
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@@ -190,12 +190,12 @@ entry_points: std.AutoArrayHashMapUnmanaged(IdRef, EntryPoint) = .empty,
pub fn init(gpa: Allocator, target: std.Target) Module {
const version_minor: u8 = blk: {
// Prefer higher versions
if (std.Target.spirv.featureSetHas(target.cpu.features, .v1_6)) break :blk 6;
if (std.Target.spirv.featureSetHas(target.cpu.features, .v1_5)) break :blk 5;
if (std.Target.spirv.featureSetHas(target.cpu.features, .v1_4)) break :blk 4;
if (std.Target.spirv.featureSetHas(target.cpu.features, .v1_3)) break :blk 3;
if (std.Target.spirv.featureSetHas(target.cpu.features, .v1_2)) break :blk 2;
if (std.Target.spirv.featureSetHas(target.cpu.features, .v1_1)) break :blk 1;
if (target.cpu.has(.spirv, .v1_6)) break :blk 6;
if (target.cpu.has(.spirv, .v1_5)) break :blk 5;
if (target.cpu.has(.spirv, .v1_4)) break :blk 4;
if (target.cpu.has(.spirv, .v1_3)) break :blk 3;
if (target.cpu.has(.spirv, .v1_2)) break :blk 2;
if (target.cpu.has(.spirv, .v1_1)) break :blk 1;
break :blk 0;
};
@@ -268,7 +268,7 @@ pub fn idBound(self: Module) Word {
}
pub fn hasFeature(self: *Module, feature: std.Target.spirv.Feature) bool {
return std.Target.spirv.featureSetHas(self.target.cpu.features, feature);
return self.target.cpu.has(.spirv, feature);
}
fn addEntryPointDeps(