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compiler: delete arm backend

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this backend was abandoned before it was completed, and it is not worth
salvaging.
This commit is contained in:
Andrew Kelley
2025-07-02 14:50:41 -07:00
parent 20a543097b
commit a13f0d40eb
8 changed files with 5 additions and 8997 deletions
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13
src/codegen.zig
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@@ -49,7 +49,7 @@ fn importBackend(comptime backend: std.builtin.CompilerBackend) type {
return switch (backend) {
.other, .stage1 => unreachable,
.stage2_aarch64 => unreachable,
.stage2_arm => @import("arch/arm/CodeGen.zig"),
.stage2_arm => unreachable,
.stage2_c => @import("codegen/c.zig"),
.stage2_llvm => @import("codegen/llvm.zig"),
.stage2_powerpc => unreachable,
@@ -70,7 +70,6 @@ pub fn legalizeFeatures(pt: Zcu.PerThread, nav_index: InternPool.Nav.Index) ?*co
inline .stage2_llvm,
.stage2_c,
.stage2_wasm,
.stage2_arm,
.stage2_x86_64,
.stage2_x86,
.stage2_riscv64,
@@ -87,7 +86,6 @@ pub fn legalizeFeatures(pt: Zcu.PerThread, nav_index: InternPool.Nav.Index) ?*co
/// MIR from codegen to the linker *regardless* of which backend is in use. So, we use this: a
/// union of all MIR types. The active tag is known from the backend in use; see `AnyMir.tag`.
pub const AnyMir = union {
arm: @import("arch/arm/Mir.zig"),
riscv64: @import("arch/riscv64/Mir.zig"),
sparc64: @import("arch/sparc64/Mir.zig"),
x86_64: @import("arch/x86_64/Mir.zig"),
@@ -112,8 +110,7 @@ pub const AnyMir = union {
const backend = target_util.zigBackend(&zcu.root_mod.resolved_target.result, zcu.comp.config.use_llvm);
switch (backend) {
else => unreachable,
inline .stage2_arm,
.stage2_riscv64,
inline .stage2_riscv64,
.stage2_sparc64,
.stage2_x86_64,
.stage2_wasm,
@@ -141,8 +138,7 @@ pub fn generateFunction(
const target = &zcu.navFileScope(func.owner_nav).mod.?.resolved_target.result;
switch (target_util.zigBackend(target, false)) {
else => unreachable,
inline .stage2_arm,
.stage2_riscv64,
inline .stage2_riscv64,
.stage2_sparc64,
.stage2_x86_64,
.stage2_wasm,
@@ -177,8 +173,7 @@ pub fn emitFunction(
const target = &zcu.navFileScope(func.owner_nav).mod.?.resolved_target.result;
switch (target_util.zigBackend(target, zcu.comp.config.use_llvm)) {
else => unreachable,
inline .stage2_arm,
.stage2_riscv64,
inline .stage2_riscv64,
.stage2_sparc64,
.stage2_x86_64,
=> |backend| {