motiejus/zig
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basic riscv support

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llvm is giving me `error: couldn't allocate output register for
constraint '{a0}'` which is a bug that needs to be fixed upstream.
This commit is contained in:
Andrew Kelley
2019-07-18 15:03:21 -04:00
parent 07f0de6a8a
commit a3854d042e
9 changed files with 388 additions and 10 deletions
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4
src/target.cpp
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@@ -1320,6 +1320,8 @@ const char *arch_stack_pointer_register_name(ZigLLVM_ArchType arch) {
case ZigLLVM_aarch64:
case ZigLLVM_aarch64_be:
case ZigLLVM_aarch64_32:
case ZigLLVM_riscv32:
case ZigLLVM_riscv64:
return "sp";
case ZigLLVM_arm:
@@ -1350,8 +1352,6 @@ const char *arch_stack_pointer_register_name(ZigLLVM_ArchType arch) {
case ZigLLVM_r600:
case ZigLLVM_renderscript32:
case ZigLLVM_renderscript64:
case ZigLLVM_riscv32:
case ZigLLVM_riscv64:
case ZigLLVM_shave:
case ZigLLVM_sparc:
case ZigLLVM_sparcel: