stage2: fix typo in riscv64/Emit.zig

2022-02-20 22:38:32 +05:30
parent bb05a8a08a
commit bdb5713941
1 changed files with 1 additions and 1 deletions
--- a/src/arch/riscv64/Emit.zig
+++ b/src/arch/riscv64/Emit.zig
@@ -1,4 +1,4 @@
-//! This file contains the functionality for lowering AArch64 MIR into
+//! This file contains the functionality for lowering RISCV64 MIR into
 //! machine code

 const Emit = @This();