stage2 AArch64: add logical (shifted register) instructions
This commit is contained in:
joachimschmidt557
committed by
Andrew Kelley
Andrew Kelley
parent
6c0c275b27
commit
c5ec096b2f
@@ -200,17 +200,6 @@ test "FloatingPointRegister.toX" {
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/// Represents an instruction in the AArch64 instruction set
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pub const Instruction = union(enum) {
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OrShiftedRegister: packed struct {
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rd: u5,
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rn: u5,
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imm6: u6,
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rm: u5,
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n: u1,
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shift: u2,
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fixed: u5 = 0b01010,
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opc: u2 = 0b01,
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sf: u1,
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},
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MoveWideImmediate: packed struct {
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rd: u5,
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imm16: u16,
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@@ -274,10 +263,37 @@ pub const Instruction = union(enum) {
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NoOperation: packed struct {
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fixed: u32 = 0b1101010100_0_00_011_0010_0000_000_11111,
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},
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LogicalShiftedRegister: packed struct {
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rd: u5,
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rn: u5,
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imm6: u6,
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rm: u5,
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n: u1,
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shift: u2,
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fixed: u5 = 0b01010,
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opc: u2,
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sf: u1,
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},
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pub const Shift = struct {
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shift: Type = .lsl,
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amount: u6 = 0,
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pub const Type = enum(u2) {
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lsl,
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lsr,
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asr,
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ror,
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};
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pub const none = Shift{
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.shift = .lsl,
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.amount = 0,
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};
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};
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pub fn toU32(self: Instruction) u32 {
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return switch (self) {
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.OrShiftedRegister => |v| @bitCast(u32, v),
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.MoveWideImmediate => |v| @bitCast(u32, v),
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.PCRelativeAddress => |v| @bitCast(u32, v),
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.LoadStoreRegister => |v| @bitCast(u32, v),
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@@ -287,68 +303,10 @@ pub const Instruction = union(enum) {
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.UnconditionalBranchRegister => |v| @bitCast(u32, v),
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.UnconditionalBranchImmediate => |v| @bitCast(u32, v),
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.NoOperation => |v| @bitCast(u32, v),
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.LogicalShiftedRegister => |v| @bitCast(u32, v),
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};
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}
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pub const RegisterShift = struct {
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rn: u5,
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imm6: u6,
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shift: enum(u2) {
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Lsl = 0,
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Lsr = 1,
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Asr = 2,
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Ror = 3,
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},
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pub fn none() RegisterShift {
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return .{
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.rn = 0b11111,
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.imm6 = 0,
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.shift = .Lsl,
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};
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}
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};
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// Helper functions for assembly syntax functions
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fn orShiftedRegister(
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rd: Register,
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rm: Register,
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shift: RegisterShift,
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invert: bool,
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) Instruction {
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const n: u1 = if (invert) 1 else 0;
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switch (rd.size()) {
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32 => {
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return Instruction{
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.OrShiftedRegister = .{
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.rd = rd.id(),
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.rn = shift.rn,
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.imm6 = shift.imm6,
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.rm = rm.id(),
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.n = n,
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.shift = @enumToInt(shift.shift),
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.sf = 0,
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},
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};
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},
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64 => {
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return Instruction{
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.OrShiftedRegister = .{
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.rd = rd.id(),
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.rn = shift.rn,
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.imm6 = shift.imm6,
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.rm = rm.id(),
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.n = n,
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.shift = @enumToInt(shift.shift),
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.sf = 1,
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},
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};
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},
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else => unreachable, // unexpected register size
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}
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}
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fn moveWideImmediate(
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opc: u2,
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rd: Register,
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@@ -671,15 +629,49 @@ pub const Instruction = union(enum) {
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};
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}
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// Bitwise (inclusive) OR of a register value
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pub fn orr(rd: Register, rm: Register, shift: RegisterShift) Instruction {
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return orShiftedRegister(rd, rm, shift, false);
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fn logicalShiftedRegister(
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opc: u2,
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n: u1,
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shift: Shift,
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rd: Register,
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rn: Register,
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rm: Register,
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) Instruction {
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switch (rd.size()) {
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32 => {
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assert(shift.amount < 32);
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return Instruction{
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.LogicalShiftedRegister = .{
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.rd = rd.id(),
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.rn = rn.id(),
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.imm6 = shift.amount,
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.rm = rm.id(),
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.n = n,
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.shift = @enumToInt(shift.shift),
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.opc = opc,
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.sf = 0b0,
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},
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};
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},
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64 => {
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return Instruction{
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.LogicalShiftedRegister = .{
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.rd = rd.id(),
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.rn = rn.id(),
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.imm6 = shift.amount,
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.rm = rm.id(),
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.n = n,
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.shift = @enumToInt(shift.shift),
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.opc = opc,
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.sf = 0b1,
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},
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};
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},
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else => unreachable, // unexpected register size
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}
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}
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pub fn orn(rd: Register, rm: Register, shift: RegisterShift) Instruction {
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return orShiftedRegister(rd, rm, shift, true);
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}
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// Helper functions for assembly syntax functions
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// Move wide (immediate)
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@@ -823,6 +815,40 @@ pub const Instruction = union(enum) {
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pub fn nop() Instruction {
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return Instruction{ .NoOperation = {} };
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}
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// Logical (shifted register)
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pub fn @"and"(rd: Register, rn: Register, rm: Register, shift: Shift) Instruction {
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return logicalShiftedRegister(0b00, 0b0, shift, rd, rn, rm);
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}
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pub fn bic(rd: Register, rn: Register, rm: Register, shift: Shift) Instruction {
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return logicalShiftedRegister(0b00, 0b1, shift, rd, rn, rm);
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}
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pub fn orr(rd: Register, rn: Register, rm: Register, shift: Shift) Instruction {
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return logicalShiftedRegister(0b01, 0b0, shift, rd, rn, rm);
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}
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pub fn orn(rd: Register, rn: Register, rm: Register, shift: Shift) Instruction {
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return logicalShiftedRegister(0b01, 0b1, shift, rd, rn, rm);
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}
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pub fn eor(rd: Register, rn: Register, rm: Register, shift: Shift) Instruction {
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return logicalShiftedRegister(0b10, 0b0, shift, rd, rn, rm);
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}
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pub fn eon(rd: Register, rn: Register, rm: Register, shift: Shift) Instruction {
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return logicalShiftedRegister(0b10, 0b1, shift, rd, rn, rm);
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}
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pub fn ands(rd: Register, rn: Register, rm: Register, shift: Shift) Instruction {
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return logicalShiftedRegister(0b11, 0b0, shift, rd, rn, rm);
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}
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pub fn bics(rd: Register, rn: Register, rm: Register, shift: Shift) Instruction {
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return logicalShiftedRegister(0b11, 0b1, shift, rd, rn, rm);
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}
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};
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test "" {
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@@ -836,15 +862,15 @@ test "serialize instructions" {
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};
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const testcases = [_]Testcase{
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.{ // orr x0 x1
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.inst = Instruction.orr(.x0, .x1, Instruction.RegisterShift.none()),
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.{ // orr x0, xzr, x1
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.inst = Instruction.orr(.x0, .xzr, .x1, Instruction.Shift.none),
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.expected = 0b1_01_01010_00_0_00001_000000_11111_00000,
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},
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.{ // orn x0 x1
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.inst = Instruction.orn(.x0, .x1, Instruction.RegisterShift.none()),
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.{ // orn x0, xzr, x1
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.inst = Instruction.orn(.x0, .xzr, .x1, Instruction.Shift.none),
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.expected = 0b1_01_01010_00_1_00001_000000_11111_00000,
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},
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.{ // movz x1 #4
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.{ // movz x1, #4
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.inst = Instruction.movz(.x1, 4, 0),
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.expected = 0b1_10_100101_00_0000000000000100_00001,
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},
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@@ -944,6 +970,14 @@ test "serialize instructions" {
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.inst = Instruction.ldp(.x1, .x2, Register.sp, Instruction.LoadStorePairOffset.post_index(16)),
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.expected = 0b10_101_0_001_1_0000010_00010_11111_00001,
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},
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.{ // and x0, x4, x2
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.inst = Instruction.@"and"(.x0, .x4, .x2, .{}),
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.expected = 0b1_00_01010_00_0_00010_000000_00100_00000,
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},
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.{ // and x0, x4, x2, lsl #0x8
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.inst = Instruction.@"and"(.x0, .x4, .x2, .{ .shift = .lsl, .amount = 0x8 }),
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.expected = 0b1_00_01010_00_0_00010_001000_00100_00000,
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},
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};
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for (testcases) |case| {
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