motiejus/zig
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Make sure that ZigTypeVector and ZigTypeArray have the same memory layout

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Throughout the stage1 code it is assumed that these have the same layout,
but that was not the case. This caused an issue on 32-bit hardware.
This commit is contained in:
Timon Kruiper
2020-04-01 20:42:43 +02:00
parent ae6965a4e7
commit d33766e6c7
4 changed files with 10 additions and 3 deletions
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2
src/ir.cpp
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@@ -15953,7 +15953,7 @@ static IrInstGen *ir_analyze_bin_op_cmp_numeric(IrAnalyze *ira, IrInst *source_i
if (op1->value->type->id == ZigTypeIdVector && op2->value->type->id == ZigTypeIdVector) {
if (op1->value->type->data.vector.len != op2->value->type->data.vector.len) {
ir_add_error(ira, source_instr,
buf_sprintf("vector length mismatch: %" PRIu32 " and %" PRIu32,
buf_sprintf("vector length mismatch: %" PRIu64 " and %" PRIu64,
op1->value->type->data.vector.len, op2->value->type->data.vector.len));
return ira->codegen->invalid_inst_gen;
}