riscv: change load_symbol psuedo instruction size to 8

2024-03-25 03:52:13 -07:00
parent 06089fc89a
commit e70584e2f8
1 changed files with 1 additions and 0 deletions
--- a/src/arch/riscv64/Emit.zig
+++ b/src/arch/riscv64/Emit.zig
@@ -517,6 +517,7 @@ fn instructionSize(emit: *Emit, inst: Mir.Inst.Index) usize {
        .cmp_eq,
        .cmp_imm_eq,
        .cmp_gte,
+        .load_symbol,
        => 8,

        else => 4,