Merge pull request #18729 from Vexu/fixes
Fix some generic{Reader,Writer} related issues
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@@ -22368,7 +22368,10 @@ fn zirErrorCast(sema: *Sema, block: *Block, extended: Zir.Inst.Extended.InstData
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try sema.requireRuntimeBlock(block, src, operand_src);
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const err_int_ty = try mod.errorIntType();
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if (block.wantSafety() and !dest_ty.isAnyError(mod) and sema.mod.backendSupportsFeature(.error_set_has_value)) {
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if (block.wantSafety() and !dest_ty.isAnyError(mod) and
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dest_ty.toIntern() != .adhoc_inferred_error_set_type and
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sema.mod.backendSupportsFeature(.error_set_has_value))
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{
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if (dest_tag == .ErrorUnion) {
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const err_code = try sema.analyzeErrUnionCode(block, operand_src, operand);
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const err_int = try block.addBitCast(err_int_ty, err_code);
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@@ -8694,10 +8694,10 @@ pub const FuncGen = struct {
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if (!result_is_ref) {
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return self.dg.todo("implement bitcast vector to non-ref array", .{});
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}
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const array_ptr = try self.buildAllocaWorkaround(inst_ty, .default);
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const alignment = inst_ty.abiAlignment(mod).toLlvm();
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const array_ptr = try self.buildAllocaWorkaround(inst_ty, alignment);
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const bitcast_ok = elem_ty.bitSize(mod) == elem_ty.abiSize(mod) * 8;
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if (bitcast_ok) {
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const alignment = inst_ty.abiAlignment(mod).toLlvm();
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_ = try self.wip.store(.normal, operand, array_ptr, alignment);
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} else {
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// If the ABI size of the element type is not evenly divisible by size in bits;
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@@ -1550,6 +1550,8 @@ pub const Value = struct {
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},
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.ptr => |ptr| switch (ptr.addr) {
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.eu_payload, .opt_payload => |base| Value.fromInterned(base).canMutateComptimeVarState(mod),
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.anon_decl => |anon_decl| Value.fromInterned(anon_decl.val).canMutateComptimeVarState(mod),
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.elem, .field => |base_index| Value.fromInterned(base_index.base).canMutateComptimeVarState(mod),
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else => false,
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},
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.opt => |opt| switch (opt.val) {
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