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Merge pull request #13744 from Vexu/stage2-fixes

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Improve error messages, fix dependency loops
This commit is contained in:
Andrew Kelley
2022-12-03 00:42:11 -05:00
committed by GitHub
parent c43ac67f82 b500e0eb17
commit fdbb0fb7b9
40 changed files with 378 additions and 95 deletions
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2
src/codegen/llvm.zig
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@@ -8932,7 +8932,7 @@ pub const FuncGen = struct {
if (elem.isUndef()) {
val.* = llvm_i32.getUndef();
} else {
const int = elem.toSignedInt();
const int = elem.toSignedInt(self.dg.module.getTarget());
const unsigned = if (int >= 0) @intCast(u32, int) else @intCast(u32, ~int + a_len);
val.* = llvm_i32.constInt(unsigned, .False);
}

4
src/codegen/spirv.zig
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@@ -360,7 +360,7 @@ pub const DeclGen = struct {
// Note, value is required to be sign-extended, so we don't need to mask off the upper bits.
// See https://www.khronos.org/registry/SPIR-V/specs/unified1/SPIRV.html#Literal
var int_bits = if (ty.isSignedInt()) @bitCast(u64, val.toSignedInt()) else val.toUnsignedInt(target);
var int_bits = if (ty.isSignedInt()) @bitCast(u64, val.toSignedInt(target)) else val.toUnsignedInt(target);
const value: spec.LiteralContextDependentNumber = switch (backing_bits) {
1...32 => .{ .uint32 = @truncate(u32, int_bits) },
@@ -763,7 +763,7 @@ pub const DeclGen = struct {
if (elem.isUndef()) {
self.func.body.writeOperand(spec.LiteralInteger, 0xFFFF_FFFF);
} else {
const int = elem.toSignedInt();
const int = elem.toSignedInt(self.getTarget());
const unsigned = if (int >= 0) @intCast(u32, int) else @intCast(u32, ~int + a_len);
self.func.body.writeOperand(spec.LiteralInteger, unsigned);
}