7 Commits

Author	SHA1	Message	Date
Andrew Kelley	af084e537a	add lr register to mips	2025-07-16 10:27:40 -07:00
Andrew Kelley	8a478b4e9e	fix sparc ccr regs	2025-07-16 10:27:40 -07:00
Andrew Kelley	5aa50bcbff	fix mips clobbers	2025-07-16 10:27:40 -07:00
Andrew Kelley	3628137442	add clobbers for more architectures	2025-07-16 10:27:40 -07:00
Andrew Kelley	15f45e89a7	remove condition codes ... LLVM always assumes these are on. Zig backends do not observe them. If Zig backends want to start using them, they can be introduced, one arch at a time, with proper documentation.	2025-07-16 10:27:39 -07:00
Andrew Kelley	de9c0e4580	alexrp suggestions	2025-07-16 10:27:39 -07:00
Andrew Kelley	fcafc63f3d	inline assembly: use types ... until now these were stringly typed. it's kinda obvious when you think about it.	2025-07-16 10:23:02 -07:00