Commit Graph

190 Commits

Author SHA1 Message Date
Jakub Konka
83d89a05b7 coff: compile and link simple exit program on arm64
* make image base target dependent
* fix relocs to imports
2022-11-05 10:15:01 +01:00
Jakub Konka
62ae365308 aarch64: implement airCall for COFF 2022-11-05 10:15:00 +01:00
Jakub Konka
1fe0b58942 aarch64: extract atom index for both COFF and MachO 2022-11-05 10:14:59 +01:00
Jakub Konka
df0212bf47 aarch64: handle register downgrading in truncRegister 2022-11-05 10:14:59 +01:00
joachimschmidt557
3051fab97c stage2 AArch64: misc fixes, enable printing in test runner
- Fixed missing airRetPtr implementation
- Fixed wrong pop_regs order
- Fixed wrong source and destination register in store
2022-11-01 20:44:18 +01:00
joachimschmidt557
4e0779813b stage2 AArch64: add inline memset 2022-11-01 20:43:27 +01:00
joachimschmidt557
8a022d9c92 stage2 AArch64: implement wrap_errunion_{err,payload} 2022-11-01 20:43:27 +01:00
joachimschmidt557
3ecec50f0c stage2 AArch64: implement basic switch statements 2022-11-01 20:43:27 +01:00
joachimschmidt557
d2a5a36cab stage2 AArch64: implement min/max 2022-11-01 20:43:27 +01:00
Veikka Tuominen
d03c47bf85 Sema: use runtime_value instead of creating allocs 2022-10-27 21:08:25 -04:00
Cody Tapscott
724d753638 stage2: Add .save_err_return_trace_index AIR op
This is encoded as a primitive AIR instruction to resolve one corner
case: A function may include a `catch { ... }` or `else |err| { ... }`
block but not call any errorable fn. In that case, there is no error
return trace to save the index of and codegen needs to avoid
interacting with the non-existing error trace.

By using a primitive AIR op, we can depend on Liveness to mark this
unused in this corner case.
2022-10-21 10:44:20 -07:00
joachimschmidt557
67941926b2 stage2 AArch64: Remove remaining legacy binOp code 2022-10-20 16:14:52 +02:00
joachimschmidt557
dd62d5941e stage2 AArch64: move remaining operations out of binOp 2022-10-20 16:14:52 +02:00
joachimschmidt557
3800bb538a stage2 AArch64: mov mul,div,mod to new allocRegs mechanism 2022-10-20 16:14:52 +02:00
joachimschmidt557
ea7a60116d stage2 AArch64: move add+sub to new allocRegs mechanism 2022-10-20 16:14:52 +02:00
joachimschmidt557
d8fddb535c stage2 AArch64: move cmp to new allocRegs mechanism
Remove cmp from binOp in the process
2022-10-20 16:14:52 +02:00
joachimschmidt557
5838fe89c1 stage2 AArch64: introduce ldr_ptr_stack Mir instruction 2022-10-20 16:14:52 +02:00
joachimschmidt557
230bafa1ab stage2 AArch64: simplify allocMem 2022-10-20 16:14:52 +02:00
joachimschmidt557
151e15e444 stage2 AArch64: merge floating-point registers into Register enum 2022-10-20 16:14:50 +02:00
Ali Chraghi
ca27055cda all: rename @maximum to @max and @minimum to @min 2022-10-18 14:15:16 +03:00
Robin Voetter
5d429b03e3 stage2: add @addrSpaceCast builtin 2022-10-12 20:36:12 +02:00
r00ster91
51d9db8569 fix(text): hyphenate "comptime" adjectives 2022-10-05 21:19:30 +02:00
Andrew Kelley
bec70a1a39 stage2: remove pointless discards from source code
Good riddance!
2022-09-13 02:04:20 -07:00
Jakub Konka
485d8819b3 aarch64: update codegen to using a global index rather than local index 2022-09-10 00:57:54 +02:00
Jakub Konka
601f2147e0 coff: cleanup relocations; remove COFF support from other backends
Given that COFF will want to support PIC from ground-up, there is no
point in leaving outdated code for COFF in other backends such as
arm or aarch64. Instead, when we are ready to look into those, we
can start figuring out what to add and where.
2022-08-30 10:42:21 +02:00
Jakub Konka
90b3599c68 coff: reorganize the linker 2022-08-30 10:42:21 +02:00
Veikka Tuominen
7c9979a02e stage2: generate a switch for @errSetCast safety 2022-08-12 11:40:37 +03:00
Andrew Kelley
b3d463c9e6 Merge pull request #12337 from Vexu/stage2-safety
Stage2: implement remaining runtime safety checks
2022-08-06 14:59:10 -07:00
Veikka Tuominen
f46d7304b1 stage2: add runtime safety for invalid enum values 2022-08-05 22:13:58 +03:00
joachimschmidt557
f46c80b267 stage2 AArch64: improve correctness of register aliases
Also implements ptr_elem_ptr
2022-08-05 20:30:52 +02:00
joachimschmidt557
508b90fcfa stage2 AArch64: implement basic integer rem/mod 2022-08-05 20:30:52 +02:00
joachimschmidt557
8b24c783c5 stage2 AArch64: implement basic integer division 2022-08-05 20:30:51 +02:00
joachimschmidt557
dcb236acf4 stage2 AArch64: memcpy support in store and more complete intcast 2022-08-05 20:30:51 +02:00
joachimschmidt557
02738228f2 stage2 AArch64: support returning values by reference
also adds some more support for slices passed as stack arguments
2022-08-05 20:30:51 +02:00
joachimschmidt557
65b3c27f24 stage2 AArch64: all arguments passed via stack from now on
Only in the Undefined calling convention, not in other calling
conventions
2022-08-05 20:30:51 +02:00
joachimschmidt557
cf3aaceed9 stage2 AArch64: introduce MCValue.stack_argument_offset
This new MCValue union member shares the same semantics as the MCValue
type of the same name in the ARM backend.
2022-08-05 20:30:51 +02:00
joachimschmidt557
423bef4dfc stage2 AArch64: Fix struct_field_val for register_with_overflow
Now mirrors the behavior of the native ARM backend
2022-08-05 20:30:47 +02:00
Veikka Tuominen
d75fa86d70 stage2: implement @setFloatMode 2022-07-23 15:40:12 +03:00
Jakub Konka
41b91442f4 macho: improve logs for dyld info 2022-07-22 16:58:21 +02:00
Jakub Konka
9eb7e5182b macho: rework symbol handling to match zld/ELF
Now, each object file will store a mutable table of symbols that it
defines. Upon symbol resolution between object files, the symbol
will be updated with a globally allocated section ordinal and address
in virtual memory. If the object defines a globally available symbol,
its location only (comprising of the symbol index and object index)
will be stored in the globals map for easy access when relocating, etc.
This approach cleans up the symbol management significantly, and matches
the status quo used in zld/ELF.

Additionally, this makes scoping symbol stabs easier too as they are
now naturally contained within each object file.
2022-07-22 16:58:20 +02:00
Andrew Kelley
6bc6e47b15 stage2: lower float negation explicitly
Rather than lowering float negation as `0.0 - x`.

 * Add AIR instruction for float negation.
 * Add compiler-rt functions for f128, f80 negation

closes #11853
2022-06-30 00:02:00 -07:00
Jakub Konka
59359b2547 aarch64: add airRetLoad for register mcv 2022-06-29 17:19:49 +02:00
Luuk de Gram
7c87f9c828 link:clarification & enable MachO getGlobalSymbol
This adds clarification to the getGlobalSymbol doc comments,
as well as renames the `addExternFn` function for MachO to `getGlobalSymbol`.
This function will now be called from 'src/link.zig' as well.

Finally, this also enables compiling zig's libc using LLVM even though
the `fno-LLVM` flag is given.
2022-06-24 08:12:17 +02:00
Veikka Tuominen
0333ff4476 stage2: make error{} the same size as anyerror
Having `error{}` be a zero bit type causes issues when it interracts
with empty inferred error sets which are the same size as `anyerror`.
2022-06-11 23:49:33 +03:00
joachimschmidt557
61844b6bd4 stage2 AArch64: introduce MCValue.condition_flags
Follows 9747303d16 for AArch64
2022-06-07 23:34:42 -04:00
joachimschmidt557
8ca6dc33d1 stage2 AArch64: implement try AIR instruction 2022-06-06 21:27:36 +02:00
Andrew Kelley
ef885a78d6 stage2: implement the new "try" ZIR/AIR instruction
Implements semantic analysis for the new try/try_inline ZIR
instruction. Adds the new try/try_ptr AIR instructions and implements
them for the LLVM backend.

Fixes not calling rvalue() for tryExpr in AstGen.

This is part of an effort to implement #11772.
2022-06-05 10:37:08 +02:00
Ali Chraghi
0e6285c8fc math: make cast return optional instead of an error 2022-05-27 16:43:33 -04:00
joachimschmidt557
ddd5b57045 stage2 AArch64: complete genTypedValue 2022-05-27 16:43:11 -04:00
Jakub Konka
97816e3cb8 aarch64: check lo/cc flag for unsigned sub_with_overflow
With this change, we are now correctly lowering `sub_with_overflow`
for signed and unsigned integers of register-sized integers (32-
or 64-bit precisely). We also match LLVM's behavior and so, the
condition flags we now set are:

* unsigned:
  - `add_with_overflow`: `hs`/`cs` (carry set)
  - `sub_with_overflow`: `lo`/`cc` (carry clear)
* signed:
  - `add_with_overflow`/`sub_with_overflow`: `vs` (overflow)
2022-05-25 23:43:45 +02:00