Commit Graph

17 Commits

Author SHA1 Message Date
Andrew Kelley
2f391df2a7 stage2: Sema improvements and boolean logic astgen
* add `Module.setBlockBody` and related functions
 * redo astgen for `and` and `or` to use fewer ZIR instructions and
   require less processing for comptime known values
 * Sema: rework `analyzeBody` function. See the new doc comments in this
   commit. Divides ZIR instructions up into 3 categories:
   - always noreturn
   - never noreturn
   - sometimes noreturn
2021-03-22 17:29:56 -07:00
Isaac Freund
9f0b9b8da1 stage2: remove all async related code
The current plan is to avoid using async and related features in the
stage2 compiler so that we can bootstrap before implementing them.

Having this untested and incomplete code in the codebase increases
friction while working on stage2, in particular when preforming
larger refactors such as the current zir memory layout rework.

Therefore remove all async related code, leaving only error messages
in astgen.
2021-03-23 00:23:41 +01:00
Isaac Freund
f3770dcc30 astgen: implement pointer types 2021-03-22 16:03:00 +01:00
Andrew Kelley
5769c963e0 Sema: implement arithmetic 2021-03-21 19:23:12 -07:00
Andrew Kelley
07c204393f Sema: no explicit coercion needed for inline asm args
These are now done with result locations.
2021-03-21 17:55:31 -07:00
Isaac Freund
310a44d5be zir: add negate/negate_wrap, implement astgen
These were previously implemented as a sub/sub_wrap instruction with a
lhs of 0. Making this separate instructions however allows us to save
some memory as there is no need to store a lhs.
2021-03-21 20:32:39 +01:00
Andrew Kelley
7598a00f34 stage2: fix memory management of ZIR code
* free Module.Fn ZIR code when destroying the owner Decl
 * unreachable_safe and unreachable_unsafe are collapsed into one ZIR
   instruction with a safety flag.
 * astgen: emit an unreachable instruction for unreachable literals
 * don't forget to call deinit on ZIR code
 * astgen: implement some builtin functions
2021-03-20 22:40:08 -07:00
Andrew Kelley
8bad5dfa72 astgen: implement inline assembly 2021-03-20 21:48:35 -07:00
Andrew Kelley
260c610708 ZIR: move some un_tok tags to un_node instead
Idea here is to prefer un_node to un_tok in order to avoid unnecessary
calls to `tree.firstToken`.
2021-03-20 17:18:44 -07:00
Andrew Kelley
50010447bd astgen: implement function calls 2021-03-20 17:09:06 -07:00
Andrew Kelley
56677f2f2d astgen: support blocks
We are now passing this test:

```zig
export fn _start() noreturn {}
```

```
test.zig:1:30: error: expected noreturn, found void
```

I ran into an issue where we get an integer overflow trying to compute
node index offsets from the containing Decl. The problem is that the
parser adds the Decl node after adding the child nodes. For some things,
it is easy to reserve the node index and then set it later, however, for
this case, it is not a trivial code change, because depending on tokens
after parsing the decl determines whether we want to add a new node or
not.

Possible strategies here:

1. Rework the parser code to make sure that Decl nodes are before
   children nodes in the AST node array.

2. Use signed integers for Decl node offsets.

3. Just flip the order of subtraction and addition. Expect Decl Node
   index to be greater than children Node indexes.

I opted for (3) because it seems like the simplest thing to do. We'll
want to unify the logic for computing the offsets though because if the
logic gets repeated, it will probably get repeated wrong.
2021-03-19 23:15:18 -07:00
Andrew Kelley
bd2154da3d stage2: the code is compiling again
(with a lot of things commented out)
2021-03-18 22:48:28 -07:00
Andrew Kelley
b2682237db stage2: get Module and Sema compiling again
There are some `@panic("TODO")` in there but I'm trying to get the
branch to the point where collaborators can jump in.

Next is to repair the seam between LazySrcLoc and codegen's expected
absolute file offsets.
2021-03-18 22:19:28 -07:00
Andrew Kelley
66245ac834 stage2: Module and Sema are compiling again
Next up is reworking the seam between the LazySrcLoc emitted by Sema
and the byte offsets currently expected by codegen.

And then the big one: updating astgen.zig to use the new memory layout.
2021-03-17 22:54:56 -07:00
Andrew Kelley
38b3d4b00a stage2: work through some compile errors in Module and Sema 2021-03-17 00:56:08 -07:00
jacob gw
e430f3f7e0 zir-memory-layout: fix @setEvalBranchQuota
also make emitBackwardBranch fail correctly
2021-03-16 14:47:54 -07:00
Andrew Kelley
099af0e008 stage2: rename zir_sema.zig to Sema.zig 2021-03-16 00:04:17 -07:00