Commit Graph

27 Commits

Author SHA1 Message Date
joachimschmidt557
77ca77cf14 stage2 ARM: make Mir.Inst.cond = .al default 2022-01-09 14:16:29 +01:00
Robin Voetter
4931b8dc93 stage2: @errorName sema+llvm 2022-01-08 14:30:11 -05:00
joachimschmidt557
c710d5eefe stage2 ARM: implement wrap_errunion_err for empty payloads 2022-01-02 15:15:59 -05:00
joachimschmidt557
a722e1fc0b stage2 codegen: Add generateSymbol for optional stub 2022-01-01 12:51:29 +01:00
joachimschmidt557
845531dde1 stage2 ARM: implement airUnwrapErrErr + airCmp for error sets 2022-01-01 11:16:38 +01:00
joachimschmidt557
f8163f7eaf stage2 ARM: implement airCall for function pointers 2022-01-01 11:16:34 +01:00
joachimschmidt557
69d03d3a29 stage2 ARM: implement struct_field_ptr and struct_field_val 2021-12-30 14:39:06 +01:00
joachimschmidt557
ac7fa95af4 stage2 ARM: add genArmInlineMemcpy for copying types with size > 4 2021-12-30 14:24:03 +01:00
joachimschmidt557
baec07cfcd stage2 ARM: change MCValue.immediate to u32 2021-12-29 11:27:37 +01:00
joachimschmidt557
96e59fd1c2 stage2 ARM: implement slice_elem_val for sizes > 4 2021-12-29 11:08:48 +01:00
joachimschmidt557
c0ae9647f9 stage2 ARM: implement slice_elem_val for types with size <= 4 2021-12-28 20:38:37 -05:00
Andrew Kelley
c8fb36b36c stage2: LLVM backend: implement @tagName for enums
Introduced a new AIR instruction: `tag_name`. Reasons to do this
instead of lowering it in Sema to a switch, function call, array
lookup, or if-else tower:
 * Sema is a bottleneck; do less work in Sema whenever possible.
 * If any optimization passes run, and the operand to becomes
   comptime-known, then it could change to have a comptime result
   value instead of lowering to a function or array or something which
   would then have to be garbage-collected.
 * Backends may want to choose to use a function and a switch branch,
   or they may want to use a different strategy.

Codegen for `@tagName` is implemented for the LLVM backend but not any
others yet.

Introduced some new `Type` tags:
 * `const_slice_u8_sentinel_0`
 * `manyptr_const_u8_sentinel_0`

The motivation for this was to make typeof() on the tag_name AIR
instruction non-allocating.

A bunch more enum tests are passing now.
2021-12-27 01:14:50 -07:00
joachimschmidt557
8a0e86cd5c stage2 ARM: implement load for types with size 8 (e.g. slices) 2021-12-26 17:05:08 +01:00
joachimschmidt557
c55f58d8bb stage2 ARM: implement is_err and is_non_err for simple error unions 2021-12-21 23:13:30 +01:00
joachimschmidt557
edcebe7013 stage2 ARM: implement is_null and is_non_null for ptr-like optionals 2021-12-21 23:13:30 +01:00
joachimschmidt557
44061cd760 stage2 ARM: Refactor airStore 2021-12-21 11:30:56 -08:00
Robin Voetter
e106e18d96 stage2: @shlWithOverflow 2021-12-21 01:47:27 +01:00
Robin Voetter
964dbeb826 stage2: @subWithOverflow 2021-12-21 01:41:51 +01:00
Robin Voetter
c47ed0c912 stage2: @mulWithOverflow 2021-12-21 01:41:51 +01:00
Robin Voetter
ddd2ef822f stage2: @returnAddress() 2021-12-21 01:41:51 +01:00
Robin Voetter
f3d635b668 stage2: @addWithOverflow 2021-12-21 01:41:51 +01:00
joachimschmidt557
9892684d35 stage2 ARM: spill insts currently in compare flags if necessary 2021-12-18 15:23:25 -08:00
joachimschmidt557
2f18c5955a stage2 ARM: Implement calling with stack parameters 2021-12-04 18:16:23 -08:00
Lee Cannon
85de022c56 allocgate: std Allocator interface refactor 2021-11-30 23:32:47 +00:00
joachimschmidt557
d94b032e92 stage2 ARM: Introduce MIR 2021-11-16 19:52:21 -05:00
Andrew Kelley
cb785b9c6b Sema: implement coerce_result_ptr for optionals
New AIR instruction: `optional_payload_ptr_set`
It's like `optional_payload_ptr` except it sets the non-null bit.

When storing to the payload via a result location that is an optional,
`optional_payload_ptr_set` is now emitted. There is a new algorithm in
`zirCoerceResultPtr` which stores a dummy value through the result
pointer into a temporary block, and then pops off the AIR instructions
from the temporary block in order to determine how to transform the
result location pointer in case any in-between coercions need to happen.

Fixes a couple of behavior tests regarding optionals.
2021-11-09 23:01:35 -07:00
joachimschmidt557
6b5e403e5d stage2 ARM: move codegen to separate file
This also removes i386 codegen code, which was unused and untested
2021-11-07 21:20:58 +01:00