Commit Graph

168 Commits

Author SHA1 Message Date
Andrew Kelley
bec70a1a39 stage2: remove pointless discards from source code
Good riddance!
2022-09-13 02:04:20 -07:00
Jakub Konka
485d8819b3 aarch64: update codegen to using a global index rather than local index 2022-09-10 00:57:54 +02:00
Jakub Konka
601f2147e0 coff: cleanup relocations; remove COFF support from other backends
Given that COFF will want to support PIC from ground-up, there is no
point in leaving outdated code for COFF in other backends such as
arm or aarch64. Instead, when we are ready to look into those, we
can start figuring out what to add and where.
2022-08-30 10:42:21 +02:00
Jakub Konka
90b3599c68 coff: reorganize the linker 2022-08-30 10:42:21 +02:00
Veikka Tuominen
7c9979a02e stage2: generate a switch for @errSetCast safety 2022-08-12 11:40:37 +03:00
Andrew Kelley
b3d463c9e6 Merge pull request #12337 from Vexu/stage2-safety
Stage2: implement remaining runtime safety checks
2022-08-06 14:59:10 -07:00
Veikka Tuominen
f46d7304b1 stage2: add runtime safety for invalid enum values 2022-08-05 22:13:58 +03:00
joachimschmidt557
f46c80b267 stage2 AArch64: improve correctness of register aliases
Also implements ptr_elem_ptr
2022-08-05 20:30:52 +02:00
joachimschmidt557
508b90fcfa stage2 AArch64: implement basic integer rem/mod 2022-08-05 20:30:52 +02:00
joachimschmidt557
8b24c783c5 stage2 AArch64: implement basic integer division 2022-08-05 20:30:51 +02:00
joachimschmidt557
dcb236acf4 stage2 AArch64: memcpy support in store and more complete intcast 2022-08-05 20:30:51 +02:00
joachimschmidt557
02738228f2 stage2 AArch64: support returning values by reference
also adds some more support for slices passed as stack arguments
2022-08-05 20:30:51 +02:00
joachimschmidt557
65b3c27f24 stage2 AArch64: all arguments passed via stack from now on
Only in the Undefined calling convention, not in other calling
conventions
2022-08-05 20:30:51 +02:00
joachimschmidt557
cf3aaceed9 stage2 AArch64: introduce MCValue.stack_argument_offset
This new MCValue union member shares the same semantics as the MCValue
type of the same name in the ARM backend.
2022-08-05 20:30:51 +02:00
joachimschmidt557
423bef4dfc stage2 AArch64: Fix struct_field_val for register_with_overflow
Now mirrors the behavior of the native ARM backend
2022-08-05 20:30:47 +02:00
Veikka Tuominen
d75fa86d70 stage2: implement @setFloatMode 2022-07-23 15:40:12 +03:00
Jakub Konka
41b91442f4 macho: improve logs for dyld info 2022-07-22 16:58:21 +02:00
Jakub Konka
9eb7e5182b macho: rework symbol handling to match zld/ELF
Now, each object file will store a mutable table of symbols that it
defines. Upon symbol resolution between object files, the symbol
will be updated with a globally allocated section ordinal and address
in virtual memory. If the object defines a globally available symbol,
its location only (comprising of the symbol index and object index)
will be stored in the globals map for easy access when relocating, etc.
This approach cleans up the symbol management significantly, and matches
the status quo used in zld/ELF.

Additionally, this makes scoping symbol stabs easier too as they are
now naturally contained within each object file.
2022-07-22 16:58:20 +02:00
Andrew Kelley
6bc6e47b15 stage2: lower float negation explicitly
Rather than lowering float negation as `0.0 - x`.

 * Add AIR instruction for float negation.
 * Add compiler-rt functions for f128, f80 negation

closes #11853
2022-06-30 00:02:00 -07:00
Jakub Konka
59359b2547 aarch64: add airRetLoad for register mcv 2022-06-29 17:19:49 +02:00
Luuk de Gram
7c87f9c828 link:clarification & enable MachO getGlobalSymbol
This adds clarification to the getGlobalSymbol doc comments,
as well as renames the `addExternFn` function for MachO to `getGlobalSymbol`.
This function will now be called from 'src/link.zig' as well.

Finally, this also enables compiling zig's libc using LLVM even though
the `fno-LLVM` flag is given.
2022-06-24 08:12:17 +02:00
Veikka Tuominen
0333ff4476 stage2: make error{} the same size as anyerror
Having `error{}` be a zero bit type causes issues when it interracts
with empty inferred error sets which are the same size as `anyerror`.
2022-06-11 23:49:33 +03:00
joachimschmidt557
61844b6bd4 stage2 AArch64: introduce MCValue.condition_flags
Follows 9747303d16 for AArch64
2022-06-07 23:34:42 -04:00
joachimschmidt557
8ca6dc33d1 stage2 AArch64: implement try AIR instruction 2022-06-06 21:27:36 +02:00
Andrew Kelley
ef885a78d6 stage2: implement the new "try" ZIR/AIR instruction
Implements semantic analysis for the new try/try_inline ZIR
instruction. Adds the new try/try_ptr AIR instructions and implements
them for the LLVM backend.

Fixes not calling rvalue() for tryExpr in AstGen.

This is part of an effort to implement #11772.
2022-06-05 10:37:08 +02:00
Ali Chraghi
0e6285c8fc math: make cast return optional instead of an error 2022-05-27 16:43:33 -04:00
joachimschmidt557
ddd5b57045 stage2 AArch64: complete genTypedValue 2022-05-27 16:43:11 -04:00
Jakub Konka
97816e3cb8 aarch64: check lo/cc flag for unsigned sub_with_overflow
With this change, we are now correctly lowering `sub_with_overflow`
for signed and unsigned integers of register-sized integers (32-
or 64-bit precisely). We also match LLVM's behavior and so, the
condition flags we now set are:

* unsigned:
  - `add_with_overflow`: `hs`/`cs` (carry set)
  - `sub_with_overflow`: `lo`/`cc` (carry clear)
* signed:
  - `add_with_overflow`/`sub_with_overflow`: `vs` (overflow)
2022-05-25 23:43:45 +02:00
Andrew Kelley
c711c788f0 stage2: fixes for error unions, optionals, errors
* `?E` where E is an error set with only one field now lowers the same
   as `bool`.
 * Fix implementation of errUnionErrOffset and errUnionPayloadOffset to
   properly compute the offset of each field. Also name them the same
   as the corresponding LLVM functions and have the same function
   signature, to avoid confusion. This fixes a bug where wasm was
   passing the error union type instead of the payload type.
 * Fix C backend handling of optionals with zero-bit payload types.
 * C backend: separate out airOptionalPayload and airOptionalPayloadPtr
   which reduces branching and cleans up control flow.
 * Make Type.isNoReturn return true for error sets with no fields.
 * Make `?error{}` have only one possible value (null).
2022-05-24 15:34:52 -07:00
Jakub Konka
8c49420928 aarch64: update for new error union layout 2022-05-24 15:34:52 -07:00
Jakub Konka
e95dfac03e regalloc: make register class bitmask non-optional 2022-05-19 23:54:48 +02:00
Jakub Konka
549174f743 regalloc: allow for optional selector mask when allocating 2022-05-19 19:39:32 +02:00
Andrew Kelley
b6798c26ef stage2: fix pointer arithmetic result type
This makes it so the result of doing pointer arithmetic creates a new
pointer type that has adjusted alignment.
2022-05-17 23:50:38 -07:00
Veikka Tuominen
66c3988e5e stage2: disable error return tracing on unsupported targets 2022-05-16 17:42:51 -07:00
Veikka Tuominen
eee8fffec7 stage2: implement error return traces 2022-05-16 17:42:51 -07:00
Jakub Konka
852c820841 aarch64: sub_with_overflow should always track V flag 2022-05-16 13:55:26 -07:00
Jakub Konka
f57b059e58 regalloc: refactor locking multiple registers at once 2022-05-07 13:27:11 +02:00
Jakub Konka
197c2a465f regalloc: rename freeze/unfreeze to lock/unlock registers 2022-05-07 10:46:05 +02:00
Jakub Konka
ac954eb539 regalloc: ensure we only freeze/unfreeze at the outermost scope
This prevents a nasty type of bugs where we accidentally unfreeze
a register that was frozen purposely in the outer scope, risking
accidental realloc of a taken register.

Fix CF flags spilling on aarch64 backend.
2022-05-07 00:57:55 +02:00
Jakub Konka
90a8817f55 aarch64: ensure we set correct operand size at codegen stage 2022-05-05 22:33:03 +02:00
Jakub Konka
d112cd52f3 aarch64: fix mul_with_overflow for ints <= 32bits 2022-05-05 21:43:36 +02:00
Jakub Konka
f4421c01e8 aarch64: implement mul_with_overflow for ints in range 33-64 bits incl 2022-05-05 21:43:36 +02:00
Jakub Konka
8715b01005 aarch64: implement mul_with_overflow for <= 32bit ints
Add emitters for `smull`, `umull` and `tst (immediate)` instructions.
2022-05-05 21:43:36 +02:00
joachimschmidt557
aaacda4df9 stage2 AArch64: implement shl_with_overflow 2022-05-05 21:43:35 +02:00
joachimschmidt557
f267e7a8b4 stage2 AArch64: implement {add,sub}_with_overflow for all ints < 64 2022-05-05 21:43:35 +02:00
joachimschmidt557
c2d2307d09 stage2 AArch64: initial implementation of {add,sub}_with_overflow 2022-05-05 21:43:35 +02:00
Andrew Kelley
65389dc280 stage2: improve inline asm stage1 compatibility
* outputs can have names and be referenced with template replacements
   the same as inputs.
 * fix print_air.zig not decoding correctly.
 * LLVM backend: use a table for template names for simplicity
2022-05-02 22:14:17 -07:00
Andrew Kelley
09f1d62bdf add new builtin function @tan
The reason for having `@tan` is that we already have `@sin` and `@cos`
because some targets have machine code instructions for them, but in the
case that the implementation needs to go into compiler-rt, sin, cos, and
tan all share a common dependency which includes a table of data. To
avoid duplicating this table of data, we promote tan to become a builtin
alongside sin and cos.

ZIR: The tag enum is at capacity so this commit moves
`field_call_bind_named` to be `extended`. I measured this as one of
the least used tags in the zig codebase.

Fix libc math suffix for `f32` being wrong in both stage1 and stage2.
stage1: add missing libc prefix for float functions.
2022-04-27 16:45:23 -07:00
Andrew Kelley
f7596ae942 stage2: use indexes for Decl objects
Rather than allocating Decl objects with an Allocator, we instead allocate
them with a SegmentedList. This provides four advantages:
 * Stable memory so that one thread can access a Decl object while another
   thread allocates additional Decl objects from this list.
 * It allows us to use u32 indexes to reference Decl objects rather than
   pointers, saving memory in Type, Value, and dependency sets.
 * Using integers to reference Decl objects rather than pointers makes
   serialization trivial.
 * It provides a unique integer to be used for anonymous symbol names,
   avoiding multi-threaded contention on an atomic counter.
2022-04-20 17:37:35 -07:00
joachimschmidt557
fa85a739d9 stage2 AArch64: fix shl, shr, shl_exact, shr_exact
Introduces the necessary truncation after shift
2022-04-19 22:40:51 +02:00