Commit Graph

255 Commits

Author SHA1 Message Date
David Rubin
c00a5ff792 riscv: implement @floatFromInt 2024-07-26 04:19:16 -07:00
David Rubin
1a7d89a84d riscv: clean up and unify encoding logic 2024-07-26 04:19:13 -07:00
David Rubin
574028ed5e riscv: boilerplate for creating lazy functions 2024-07-26 04:05:44 -07:00
David Rubin
64c6473443 riscv: implement add_sat and ptr_slice_len_ptr
this is enough to use the basic functions of an ArrayList!
2024-07-26 04:05:43 -07:00
David Rubin
6ac1b2d82a riscv: add 32-bit support to integer @abs 2024-07-26 04:05:42 -07:00
David Rubin
1820f44104 riscv: implement sub-byte addition 2024-07-26 04:05:42 -07:00
David Rubin
81ca3a1d59 riscv: fix logic bug in ptr_elem_ptr
I was doing duplicate work with `elemOffset` multiplying by the abi size and then the `ptr_add` `genBinOp` also multiplying.

This led to having writes happening in the wrong place.
2024-07-26 04:05:41 -07:00
David Rubin
cde6956b21 riscv: remove redundant assert in genBinOp 2024-07-26 04:05:41 -07:00
David Rubin
c78ebeb44c riscv: implement ptr_slice_ptr_ptr
just one step closer to allocation
2024-07-26 04:05:40 -07:00
David Rubin
93e9c7a963 riscv: implement @clz 2024-07-26 04:05:39 -07:00
David Rubin
8d30fc45c4 riscv: implement more operators
we can run `std.debug.print` now, with both run-time strings and integers!
2024-07-26 04:05:39 -07:00
David Rubin
9766b68c47 riscv: un-cache the avl and vtype when returning from a function call
the csrs `avl` and `vtype` are considered caller-saved so it could have changed while inside of the function.
the easiest way to handle this is to just set the cached `vtype` and `avl` to null, so that the next time something
needs to set it, it'll emit an instruction instead of relying on a potentially invalid setting.
2024-07-26 04:05:38 -07:00
David Rubin
5ec926cdbf riscv: refactor bin_file and zcu usage 2024-07-14 23:04:05 -07:00
David Rubin
5a2c547fc1 riscv: vectors part 3 2024-07-14 23:02:35 -07:00
David Rubin
09e9812086 riscv: vectors part 2 2024-07-14 23:02:34 -07:00
David Rubin
571aa694fd riscv: vectors part 1 2024-07-14 23:02:34 -07:00
David Rubin
3e73f37d0a riscv: implement @fence 2024-07-14 23:02:33 -07:00
David Rubin
7a02878f4e riscv: truncate airStructFieldVal result 2024-07-14 23:02:33 -07:00
David Rubin
27ceb4ae37 riscv implement @sqrt for f32/f64 2024-07-14 23:02:32 -07:00
David Rubin
0460572899 riscv: @atomicRmw
Now we generate debug undefined constants when the user asks for them to dedup across the function decl. This takes 2 instructions instead of 7 in the RISC-V backend.

TODO, we need to dedupe across function decl boundaries.
2024-07-14 23:02:32 -07:00
David Rubin
ea084e9519 riscv: @atomicLoad and @atomicStore 2024-07-14 23:02:29 -07:00
Jacob Young
a1053e8e1d InternPool: add and use a mutate mutex for each list
This allows the mutate mutex to only be locked during actual grows,
which are rare. For the lists that didn't previously have a mutex, this
change has little effect since grows are rare and there is zero
contention on a mutex that is only ever locked by one thread.  This
change allows `extra` to be mutated without racing with a grow.
2024-07-13 04:47:38 -04:00
mlugg
f93a10f664 Air: store param names directly instead of referencing Zir 2024-07-10 11:20:08 -04:00
Jacob Young
667b4f9054 Zcu: cache fully qualified name on Decl
This avoids needing to mutate the intern pool from backends.
2024-07-10 11:10:49 -04:00
Jacob Young
525f341f33 Zcu: introduce PerThread and pass to all the functions 2024-07-07 22:59:52 -04:00
Andrew Kelley
30ec43a6c7 Zcu: extract permanent state from File
Primarily, this commit removes 2 fields from File, relying on the data
being stored in the `files` field, with the key as the path digest, and
the value as the struct decl corresponding to the File. This table is
serialized into the compiler state that survives between incremental
updates.

Meanwhile, the File struct remains ephemeral data that can be
reconstructed the first time it is needed by the compiler process, as
well as operated on by independent worker threads.

A key outcome of this commit is that there is now a stable index that
can be used to refer to a File. This will be needed when serializing
error messages to survive incremental compilation updates.
2024-07-04 17:51:35 -07:00
mlugg
2f0f1efa6f compiler: type.zig -> Type.zig 2024-07-04 21:01:42 +01:00
mlugg
ded5c759f8 Zcu: store LazySrcLoc in error messages
This change modifies `Zcu.ErrorMsg` to store a `Zcu.LazySrcLoc` rather
than a `Zcu.SrcLoc`. Everything else is dominoes.

The reason for this change is incremental compilation. If a failed
`AnalUnit` is up-to-date on an update, we want to re-use the old error
messages. However, the file containing the error location may have been
modified, and `SrcLoc` cannot survive such a modification. `LazySrcLoc`
is designed to be correct across incremental updates. Therefore, we
defer source location resolution until `Compilation` gathers the compile
errors into the `ErrorBundle`.
2024-07-04 21:01:41 +01:00
David Rubin
e73ae94b36 riscv: remove deprecated Module usages 2024-06-23 15:26:14 +01:00
Andrew Kelley
0fcd59eada rename src/Module.zig to src/Zcu.zig
This patch is a pure rename plus only changing the file path in
`@import` sites, so it is expected to not create version control
conflicts, even when rebasing.
2024-06-22 22:59:56 -04:00
David Rubin
4fd8900337 riscv: rewrite "binOp"
Reorganize how the binOp and genBinOp functions work.

I've spent quite a while here reading exactly through the spec and so many
tests are enabled because of several critical issues the old design had.

There are some regressions that will take a long time to figure out individually
so I will ignore them for now, and pray they get fixed by themselves. When
we're closer to 100% passing is when I will start diving into them one-by-one.
2024-06-13 02:24:39 -07:00
David Rubin
a9ef016943 riscv: implement airArrayToSlice 2024-06-13 02:22:34 -07:00
David Rubin
a270c6f8c8 riscv: implement optional logic 2024-06-13 02:22:33 -07:00
David Rubin
d69c48370a riscv: integer + float @abs 2024-06-13 02:22:06 -07:00
David Rubin
206e66858c riscv: rename Self to Func
Very similar reasoning to the Wasm backend. I believe that "Self" is
not the most descriptive possible name here and "Func" better explains it.

The generation is happening for a Function, and accessing "Func" is like accessing
the context of that current function.
2024-06-13 02:22:05 -07:00
David Rubin
c10d1c6a75 riscv: implement more arithmetic instructions 2024-06-13 02:22:05 -07:00
David Rubin
083b7b483e riscv: zero registers when using register-wide operations
what was happening is that instructions like `lb` were only affecting the lower bytes of the register and leaving the top dirty. this would lead to situtations were `cmp_eq` for example was using `xor`, which was failing because of the left-over stuff in the top of the register.

with this commit, we now zero out or truncate depending on the context, to ensure instructions like xor will provide proper results.
2024-06-13 02:22:04 -07:00
David Rubin
b67995689d riscv: add airAggregateInit for arrays 2024-06-13 02:22:04 -07:00
David Rubin
b2cb090c37 riscv: float args 2024-06-13 02:21:39 -07:00
David Rubin
031d8248e0 riscv: first sign of floats! 2024-06-13 02:21:38 -07:00
David Rubin
7ed2f2156f riscv: fix register clobber in certain edge cases 2024-06-13 02:21:38 -07:00
David Rubin
05de6c279b riscv: std.fmt.format running
- implements `airSlice`, `airBitAnd`, `airBitOr`, `airShr`.

- got a basic design going for the `airErrorName` but for some reason it simply returns
empty bytes. will investigate further.

- only generating `.got.zig` entries when not compiling an object or shared library

- reduced the total amount of ops a mnemonic can have to 3, simplifying the logic
2024-06-13 02:20:47 -07:00
David Rubin
55b28c7e44 riscv: PRO member function calls
this is enough progress for us to be able to call `stdout.write`!
2024-06-13 02:19:40 -07:00
David Rubin
c457f35da5 riscv: arbitrary sized arrays 2024-06-13 02:19:40 -07:00
David Rubin
f34dcd067b riscv: basic libc varargs 2024-06-13 02:19:39 -07:00
David Rubin
fcafaae747 riscv: get basic libc interop 2024-06-13 02:19:39 -07:00
David Rubin
004d0c8978 riscv: switch progress + by-ref return progress 2024-06-13 02:19:38 -07:00
Andrew Kelley
9be8a9000f Revert "implement @expect builtin (#19658)"
This reverts commit a7de02e052.

This did not implement the accepted proposal, and I did not sign off
on the changes. I would like a chance to review this, please.
2024-05-22 09:57:43 -07:00
David Rubin
a7de02e052 implement @expect builtin (#19658)
* implement `@expect`

* add docs

* add a second arg for expected bool

* fix typo

* move `expect` to use BinOp

* update to newer langref format
2024-05-22 10:51:16 -05:00
David Rubin
1dfdc21c31 riscv: intcast got_addr
the recent merge strings PR made `got_addr` `i64` and now requires an `@intCast`.
2024-05-11 02:17:24 -07:00