Robin Voetter
880473dc3f
SPIR-V: Unary not operation
2021-05-16 14:55:09 +02:00
Robin Voetter
489b3ef7d4
SPIR-V: bool binary operations
2021-05-16 14:52:11 +02:00
Robin Voetter
585122b1ac
SPIR-V: comparison and equality operations
2021-05-16 14:46:58 +02:00
Robin Voetter
f14000c7e1
SPIR-V: More bitwise binary operations
2021-05-16 14:20:18 +02:00
Robin Voetter
4735e95d16
SPIR-V: More binary operations
2021-05-16 14:20:12 +02:00
Robin Voetter
10678af876
SPIR-V: genBinOp setup
2021-05-16 14:13:23 +02:00
Robin Voetter
ae2e21639a
SPIR-V: Some initial floating point constant generation
2021-05-16 14:13:23 +02:00
Robin Voetter
cbf5280f54
SPIR-V: Some instructions + constant generation setup
2021-05-16 14:13:23 +02:00
Robin Voetter
da0cc732ea
SPIR-V: Function parameter generation
2021-05-16 14:13:23 +02:00
Robin Voetter
074cb9f1da
SPIR-V: OpFunction/OpFunctionEnd generation
2021-05-16 14:13:23 +02:00
Robin Voetter
4403f3598a
SPIR-V: Proper floating point type generation
2021-05-16 14:13:23 +02:00
Robin Voetter
38cdfebad3
SPIR-V: Function prototype generation
2021-05-16 14:13:23 +02:00
Robin Voetter
458c338aeb
SPIR-V: Compute backing integer bits
2021-05-16 14:13:23 +02:00
Robin Voetter
de6df2bc12
SPIR-V: Restructure codegen a bit
2021-05-16 14:13:23 +02:00
Robin Voetter
42f2ff6ec9
SPIR-V: Re-generate spec.zig
2021-05-14 19:49:32 +02:00
Robin Voetter
d45e7dfc24
SPIR-V: Begin generating types
2021-05-14 19:49:32 +02:00
Andrew Kelley
2299e5ff1d
fix merge conflicts from previous commit
...
Any PRs merged after the one that made testing functions return errors
needs to get rebased!
2021-05-08 23:12:34 -07:00
Andrew Kelley
b88d381dec
Merge pull request #8474 from gracefuu/grace/encode-instruction
...
stage2 x86_64: encoding helpers, fix bugs
2021-05-09 01:36:51 -04:00
Veikka Tuominen
42a95197f3
update usage of std.testing in stage2
2021-05-08 15:15:30 +03:00
joachimschmidt557
bc06e19828
stage2 riscv64: cleanup code and add tests
2021-04-28 07:20:45 +02:00
gracefu
0409f9e024
stage2 x86_64: simplify inst encoder to a set of dumb helper fns
2021-04-16 15:21:17 +08:00
gracefu
e1959ccd4e
stage2 x86_64: add instruction encoder helper fn
2021-04-16 15:21:16 +08:00
Michael Dusan
93cf9560b1
Merge remote-tracking branch 'origin/master' into llvm12
2021-04-11 17:40:19 -04:00
Luuk de Gram
ff5774d93d
Refactor link/wasm.zig to use offset table
...
This refactor inserts an offset table into wasm's data section
where each offset points to the actual data region.
This means we can keep offset indexes consistant and do not
have to perform any computer to determine where in the data section
something like a static string exists. Instead during runtime
it will load the data offset onto the stack.
2021-04-08 22:47:08 +02:00
Luuk de Gram
47f3642788
Cleanup
2021-04-08 22:47:08 +02:00
Luuk de Gram
1bd5552fc1
Calculate data length to ensure correct pointer offsets
2021-04-08 22:47:08 +02:00
Luuk de Gram
00b2e31589
Basic "Hello world" working
2021-04-08 22:47:08 +02:00
Andrew Kelley
9f744f19e7
Merge pull request #8464 from gracefuu/grace/wasm-ops
...
stage2 wasm: Add division and bitwise/boolean ops &, |, ^, and, or
2021-04-08 13:41:49 -07:00
joachimschmidt557
d7a89f9876
stage2 AArch64: Add conditional branch instructions
2021-04-08 13:39:11 -07:00
gracefu
e4a60b63f2
stage2 wasm: Add bitwise/boolean ops &, |, ^, and, or
2021-04-08 05:27:00 +08:00
gracefu
4c71942f84
stage2: Add .div to ir.zig
2021-04-08 05:26:56 +08:00
Andrew Kelley
015599d1ef
C backend: enumerate all the types in renderType
...
Now that we're close to supporting all the types, get rid of the `else`
prong and explicitly list out those types that are not yet implemented.
Thanks @g-w1
2021-04-07 13:17:23 -07:00
Andrew Kelley
19cf987198
C backend: implement Enum types and values
...
They are lowered directly as the integer tag type, with no typedef.
2021-04-06 23:19:46 -07:00
gracefu
ec84742c89
stage2 wasm codegen: refactor to use wasm.buildOpcode
2021-04-05 16:19:52 +08:00
gracefu
3648e43dda
std/wasm: add buildOpcode to help construction of Opcodes
2021-04-05 14:44:00 +08:00
gracefu
869fc06c57
stage2 wasm: codegen mul op
2021-04-05 14:37:04 +08:00
gracefu
d1244d3608
stage2 wasm: codegen sub op
2021-04-05 14:37:04 +08:00
Andrew Kelley
545830c0ff
LLVM sub-arch triple: remove TODO comment
...
See #6542 for more details. Upon investigation, this change is not
needed.
2021-04-04 16:10:54 -07:00
Andrew Kelley
97d7fddfb7
stage2: progress towards basic structs
...
Introduce `ResultLoc.none_or_ref` which is used by field access
expressions to avoid unnecessary loads when the field access itself
will do the load. This turns:
```zig
p.y - p.x - p.x
```
from
```zir
%14 = load(%4) node_offset:8:12
%15 = field_val(%14, "y") node_offset:8:13
%16 = load(%4) node_offset:8:18
%17 = field_val(%16, "x") node_offset:8:19
%18 = sub(%15, %17) node_offset:8:16
%19 = load(%4) node_offset:8:24
%20 = field_val(%19, "x") node_offset:8:25
```
to
```zir
%14 = field_val(%4, "y") node_offset:8:13
%15 = field_val(%4, "x") node_offset:8:19
%16 = sub(%14, %15) node_offset:8:16
%17 = field_val(%4, "x") node_offset:8:25
```
Much more compact. This requires `Sema.zirFieldVal` to support both
pointers and non-pointers.
C backend: Implement typedefs for struct types, as well as the following
TZIR instructions:
* mul
* mulwrap
* addwrap
* subwrap
* ref
* struct_field_ptr
Note that add, addwrap, sub, subwrap, mul, mulwrap instructions are all
incorrect currently and need to be updated to properly handle wrapping
and non wrapping for signed and unsigned.
C backend: change indentation delta to 1, to make the output smaller and
to process fewer bytes.
I promise I will add a test case as soon as I fix those warnings that
are being printed for my test case.
2021-04-02 19:11:51 -07:00
joachimschmidt557
43d364afef
stage2 AArch64: Add ldrh and ldrb instructions
2021-04-02 14:46:30 -07:00
Andrew Kelley
a0e89c9b46
Merge remote-tracking branch 'origin/master' into llvm12
2021-04-02 12:09:38 -07:00
Andrew Kelley
070a28e493
Merge pull request #8266 from ziglang/zir-memory-layout
...
rework ZIR memory layout; overhaul source locations
2021-03-31 23:11:15 -07:00
joachimschmidt557
e088a17f56
stage2 AArch64: implement strb and strh
2021-03-31 23:26:49 +02:00
Andrew Kelley
b85ef2300f
Merge remote-tracking branch 'origin/master' into llvm12
2021-03-28 21:42:56 -07:00
Andrew Kelley
281a7baaea
Merge remote-tracking branch 'origin/master' into zir-memory-layout
...
Wanted to make sure those new test cases still pass.
Also grab that CI fix so we can get those green check marks.
2021-03-28 19:42:43 -07:00
jacob gw
0005b34637
stage2: implement sema for @errorToInt and @intToError
2021-03-28 18:22:01 -07:00
Timon Kruiper
982df37135
stage2: handle void value in genRet in LLVM backend
2021-03-23 11:42:46 -07:00
Timon Kruiper
d73b0473a1
stage2: rename fail to todo in LLVM backend
...
This way we don't have to pass src to every function and we can simply
use the first node as the lazy source location for all the todo
errors.
2021-03-23 11:42:46 -07:00
Luuk de Gram
4b854b75d2
Fix getNot and add test cases
2021-03-22 19:56:38 +01:00
Luuk de Gram
803f9e5dd0
Implement more instructions for more control flow support
2021-03-22 19:56:35 +01:00
