joachimschmidt557
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c4778fc029
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stage2 ARM: implement mul_with_overflow for ints <= 16 bits
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2022-04-01 22:02:56 +02:00 |
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joachimschmidt557
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06058ed6f3
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stage2 regalloc: replace Register.allocIndex with generic indexOfReg
* callee_preserved_regs and other ABI-specific information have been
moved to the respective abi.zig files
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2022-03-11 13:29:16 +01:00 |
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joachimschmidt557
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528008a981
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stage2 ARM: reduce Mir.Inst.Data to 8 bytes
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2022-02-27 21:38:55 +01:00 |
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joachimschmidt557
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f48f4baf67
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stage2 ARM: generate correct variants of ldr instruction
When loading an i16 for example, generate ldrsh instead of ldrh
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2022-02-26 13:00:01 +01:00 |
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joachimschmidt557
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8ef80cfaab
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stage2 ARM: implement truncate to ints with bits <= 32
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2022-02-26 12:59:57 +01:00 |
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joachimschmidt557
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04f379dd41
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stage2 ARM: optimize airSliceElemVal for elem_size 1 or 4
In these cases, the AIR inst can be lowered to only one ldr
instruction.
Also fixes shifts in arm.bits.Offset
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2022-02-04 21:07:10 +01:00 |
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joachimschmidt557
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8f58e2d779
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stage2 codegen: move bit definitions to src/arch
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2021-09-24 13:47:59 -04:00 |
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