Commit Graph

6995 Commits

Author SHA1 Message Date
Andrew Kelley
08c768ad82 pre-merge cleanups
* Annotate workarounds with their corresponding GitHub issue links.
 * Enable test coverage for LTO on Windows with the added c_compiler test.
2021-11-15 16:32:15 -07:00
xavier
564629f704 build: workaround link error with LTO and mingw
The symbol "_tls_index" gets lost when using LTO.
Disabling LTO on the object file that defines it allows the link to work.

fixes https://github.com/ziglang/zig/issues/8531
2021-11-15 16:15:39 -07:00
J.C. Moyer
33889e1974 mingw-w64: add missing file frexp.c to mingwex.lib
Fixes a frexp() segfault on Windows.
2021-11-15 17:28:49 -05:00
Luuk de Gram
d3135f7682 Stage2: wasm - Implement the MIR pass (#10153)
* wasm: Move wasm's codegen to arch/wasm/CodeGen.zig

* wasm: Define Wasm's Mir

This declares the initial most-used instructions for wasm as
well as the data that represents them.
TODO: Add binary operand opcodes.

By re-using the wasm opcode values, we can emit each opcode very easily
by simply using `@enumToInt()`. However, this poses a possible problem:
If we use all of wasm's opcodes, it leaves us no room to use synthetic opcodes such as debugging instructions.
We could use reserved opcodes, but the wasm spec may use them at some point.
TODO: Check if we should perhaps use a 16bit tag where the highest bits are used for synthetic opcodes.

* wasm: Define basic Emit structure

* wasm: Implement corresponding Emit functions for MIR

* wasm: Initial lowering to MIR

- This implements lowering to MIR from AIR for storing and loading of locals
as well as emitting immediates.
- Relocating function indexes has been simplified a lot as well as we no
longer need to patch offsets and we write a relocatable value instead.
- Locals are now emitted at the beginning of the function section entry
meaning all offsets we generate are stable.

* wasm: Lower all AIR instructions to MIR

* wasm: Implement remaining MIR instructions

* wasm: Fix function relocations

* wasm: Get all tests working

* wasm: Make `Data` 4 bytes instead of 8.

- 64bit immediates are now stored in 2 seperate u32's.
- 64bit floats are now stored in 2 seperate u32's.
- `mem_arg` is now stored as a seperate payload in extra.
2021-11-15 18:02:24 +01:00
Daniele Cocca
29f531bec9 CBE: memset(..., 0xaa, ...) undefined values
This commit makes airStore() handle undefined values directly instead of
delegating to renderValue(): the call to renderValue() happens too late,
when "dest = " has already been written to the stream, at which point
there's no sane way to initialize e.g. struct values by assignment.

Instead, we make airStore() use memset(dest, 0xaa, sizeof(dest)), which
should transparently handle all types.

Also moves the newly-passing tests to the top of test/behavior.zig.
2021-11-14 22:49:50 -05:00
Jakub Konka
1d55705fa4 macho: invalidate relocs after relinking relocatables 2021-11-13 07:28:20 -08:00
joachimschmidt557
96e715d5a3 stage2 AArch64: add new load/store from/to stack MIR instructions 2021-11-12 22:23:31 +01:00
joachimschmidt557
8ab90a0b32 stage2 AArch64: split Instruction.ldr into ldr and ldrLiteral 2021-11-12 22:23:29 +01:00
Jakub Konka
71388b980b macho,snapshots: fix how relocs are split
Fixes how relocs are split for symbols contained within the atoms
that represent entire sections extracted from relocatable object
files.
2021-11-11 21:36:40 -08:00
Jacob G-W
08d6876d20 c codegen: fix airIsNull with pointers 2021-11-11 11:36:26 -08:00
Jakub Konka
19e5663869 Merge pull request #9935 from g-w1/plan9-std
add plan9 support to std
2021-11-11 10:45:00 -08:00
Jakub Konka
53523ef5d0 Merge pull request #10129 from joachimschmidt557/stage2-aarch64
stage2 AArch64: Implement conditional branches
2021-11-10 22:19:22 -08:00
Jacob G-W
f3ba72cf5a x86_64/Emit: don't misisel push/pop for extended regs 2021-11-10 21:56:03 -08:00
joachimschmidt557
4168b01e7a stage2 AArch64: implement airCondBr 2021-11-10 20:05:35 +01:00
joachimschmidt557
a5a012e859 stage2 AArch64: implement genSetReg for condition flags 2021-11-10 19:48:16 +01:00
joachimschmidt557
8cb00519cd stage2 AArch64: implement airCmp 2021-11-10 19:48:16 +01:00
Thomas Ives
51efd553ae C backend: Improve lowering of Zig types to C types
1. Changed Zig pointers to functions to be typedef'd so then we can
   treat them the same as other types.

2. Distinguished between const slices (zig_L prefix) and mut slices
   (zig_M prefix).

3. Changed lowering of Zig "const pointers" (e.g. *const u8) to to C
   "pointers to const" (e.g. const char *) rather than C "const
   pointers" (e.g.  char * const)

4. Ensured that all typedefs are "linked" even if the decl doesn't
   require any forward declarations

5. Added test that exercises function pointer type rendering

6. Changed .slice_ptr instruction to allocate pointer local rather than
   a uintptr_t local
2021-11-10 12:39:47 -05:00
Jakub Konka
91c3206b45 macho: use start.zig for macOS entrypoint
This effectively allows us to compile

```zig
pub fn main() void {}
```

which then calls into `std.start`.

Changes required to make this happen:
* handle signed int to immediate in x86_64 and aarch64 codegen
* ensure that on arm64 macOS, `.x19` is a caller-preserved register -
  I'm not sure about that one at all and would like to brainstorm it
  with anyone interested and especially Joachim.
* finally, fix a bug in the linker - mark new got entry as dirty upon
  atom growth.
2021-11-10 11:33:24 -05:00
Andrew Kelley
e89e3735f3 wasm: respect stack_size_override for build-obj and build-lib
Related: #8633
2021-11-10 09:20:35 -07:00
Andrew Kelley
cb785b9c6b Sema: implement coerce_result_ptr for optionals
New AIR instruction: `optional_payload_ptr_set`
It's like `optional_payload_ptr` except it sets the non-null bit.

When storing to the payload via a result location that is an optional,
`optional_payload_ptr_set` is now emitted. There is a new algorithm in
`zirCoerceResultPtr` which stores a dummy value through the result
pointer into a temporary block, and then pops off the AIR instructions
from the temporary block in order to determine how to transform the
result location pointer in case any in-between coercions need to happen.

Fixes a couple of behavior tests regarding optionals.
2021-11-09 23:01:35 -07:00
Andrew Kelley
008b0ec5e5 std.Thread.Mutex: change API to lock() and unlock()
This is a breaking change. Before, usage looked like this:

```zig
const held = mutex.acquire();
defer held.release();
```

Now it looks like this:

```zig
mutex.lock();
defer mutex.unlock();
```

The `Held` type was an idea to make mutexes slightly safer by making it
more difficult to forget to release an aquired lock. However, this
ultimately caused more problems than it solved, when any data structures
needed to store a held mutex. Simplify everything by reducing the API
down to the primitives: lock() and unlock().

Closes #8051
Closes #8246
Closes #10105
2021-11-09 18:31:03 -07:00
Zen1th
6869bc9ff8 stage2: Add support for floats in the C backend (#10059)
* Implement float type
* Fix int and float undefined value
* Handle NaN constants, preserving bit pattern
2021-11-09 18:56:01 -05:00
Zen1th
0d7359ca9b stage2: Implement Sema.floatToInt (#10097) 2021-11-09 18:52:30 -05:00
Andrew Kelley
7afa220f92 Merge pull request #10102 from rainbowbismuth/c-while-tests
C backend: while, struct tests, better undefined global handling
2021-11-09 18:24:38 -05:00
Žiga Željko
b24e475717 stage1: fix type mapping for integers and c_longdouble on nvptx 2021-11-09 16:43:03 -05:00
Andrew Kelley
d2cdfb9490 stage2: add 4 new linker flags for WebAssembly
--import-memory          import memory from the environment
--initial-memory=[bytes] initial size of the linear memory
--max-memory=[bytes]     maximum size of the linear memory
--global-base=[addr]     where to start to place global data

See #8633
2021-11-09 14:29:20 -07:00
Jacob G-W
09992f8acc add initial plan9 support to std 2021-11-09 07:08:23 -05:00
Emily Bellows
684d9532c5 C backend: restore handling of .NoReturn in function signature 2021-11-08 14:23:55 -05:00
Emily Bellows
e3d638a49e C backend: while, struct tests, better undefined global handling
1. Function signatures that return a no member struct return void
2. Undefined var decls don't get a value generated for them
3. Don't generate bitcast code if the result isn't used, since
   bitcast is a pure function. Right now struct handling code
   generates some weird unused bitcast AIR, and this optimization
   side steps that issue.
2021-11-08 14:23:55 -05:00
Jakub Konka
3c7310f8cc stage2 x86_64: add MIR->Isel lowering step for x86_64
* incorporate Andrew's MIR draft as Mir.zig
* add skeleton for Emit.zig module - Emit will lower MIR into
  machine code or textual ASM.
* implement push
* implement ret
* implement mov r/m, r
* implement sub r/m imm and sub r/m, r
* put encoding common ops together - some ops share impl such as
  MOV and cmp so put them together and vary the actual opcode
  with modRM ext only.
* implement pop
* implement movabs - movabs being a special-case of mov not
  handled by general mov MIR instruction due to requirement to
  handle 64bit immediates.
* store imm64 as a struct `Imm64{ msb: u32, lsb: u32 }` in extra data
  for use with for instance movabs inst
* implement more mov variations
* implement adc
* implement add
* implement sub
* implement xor
* implement and
* implement or
* implement sbb
* implement cmp
* implement lea - lea doesn't follow the scheme as other inst above. Similarly, I
  think bit shifts and rotates should be put in a separate basket too.
* implement adc_scale_src
* implement add_scale_src
* implement sub_scale_src
* implement xor_scale_src
* implement and_scale_src
* implement or_scale_src
* implement sbb_scale_src
* implement cmp_scale_src
* implement adc_scale_dst
* implement add_scale_dst
* implement sub_scale_dst
* implement xor_scale_dst
* implement and_scale_dst
* implement or_scale_dst
* implement sbb_scale_dst
* implement cmp_scale_dst
* implement mov_scale_src
* implement mov_scale_dst
* implement adc_scale_imm
* implement add_scale_imm
* implement sub_scale_imm
* implement xor_scale_imm
* implement and_scale_imm
* implement or_scale_imm
* implement sbb_scale_imm
* implement cmp_scale_imm
* port bin math to MIR
* backpatch stack size into prev MIR inst
* implement Function.gen() (minus dbg info)
* implement jmp/call [imm] - we can now call functions using indirect absolute
  addressing, or via registers.
* port airRet to use MIR
* port airLoop to use MIR
* patch up performReloc to use inst indices
* implement conditional jumps (without relocs)
* implement set byte on condition
* implement basic lea r64, [rip + imm]
* implement calling externs
* implement callq in PIE
* implement lea RIP in PIE context
* remove all refs to Encoder from CodeGen
* implement basic imul ops
* pass all Linux tests!
* enable most of dbg info gen
* generate arg dbg info in Emit
2021-11-08 13:27:49 -05:00
joachimschmidt557
6b5e403e5d stage2 ARM: move codegen to separate file
This also removes i386 codegen code, which was unused and untested
2021-11-07 21:20:58 +01:00
joachimschmidt557
0fb26b0369 stage2 RISCV64: introduce MIR 2021-11-05 15:30:28 -04:00
LemonBoy
2551946a51 std: Fix path resolution on Windows
GetCurrentDirectory returns a path with a trailing slash iff the cwd is
a root directory, making the code in `resolveWindows` return an invalid
path with two consecutive slashes.

Closes #10093
2021-11-04 21:05:14 -04:00
Ryan Liptak
e97feb96e4 Replace ArrayList.init/ensureTotalCapacity pairs with initCapacity
Because ArrayList.initCapacity uses 'precise' capacity allocation, this should save memory on average, and definitely will save memory in cases where ArrayList is used where a regular allocated slice could have also be used.
2021-11-04 14:54:25 -04:00
Andrew Kelley
a55dc4a3bc Merge pull request #10079 from mattbork/astgen-temp-allocs
stage2: Reduce temporary allocations in AstGen
2021-11-03 18:30:08 -04:00
joachimschmidt557
5ebdc8c46c stage2 RISCV64: move codegen to separate file 2021-11-02 13:05:01 -04:00
Emily Bellows
674932e503 C backend: implement ?void, and other zero sized types 2021-11-02 12:45:29 -04:00
Ryan Liptak
70ef9bc75c Fix ensureTotalCapacity calls that should be ensureUnusedCapacity calls
If these functions are called more than once, then the array list would no longer be guaranteed to have enough capacity during the appendAssumeCapacity calls. With ensureUnusedCapacity, they will always be guaranteed to have enough capacity regardless of how many times the function is called.
2021-11-01 15:08:41 -04:00
Andrew Kelley
77eefebe65 Merge pull request #10077 from squeek502/arraylist-capacity
std.ArrayList: add ensureTotalCapacityPrecise and update doc comments
2021-11-01 14:28:27 -04:00
joachimschmidt557
002fbb0af0 stage2 AArch64: implement unconditional branches 2021-11-01 14:23:38 -04:00
Lee Cannon
f951bf8aeb correct bug with omit frame pointer logic 2021-11-01 14:14:07 -04:00
Matthew Borkowski
01842a6ead astgen.zig: avoid temporary allocations by sharing the instructions ArrayList between a GenZir and its sub-blocks wherever their use of it is strictly nested 2021-11-01 05:42:39 -04:00
Matthew Borkowski
65c27e8e66 astgen.zig: delay adding closure_capture instructions to preserve GenZir nesting. Only containers create Namespaces, so the declaring_gz is always the GenZir passed to containerDecl, and containerDecl will always add exactly one instruction (an extended *_decl) to that GenZir. Thus, closure_capture instructions are always lined up immediately after a container decl instruction, so rather than adding them at the point of first mention, where we're nested arbitrarily deep, simply walk through the Namespace captures hash map at the end of each containerDecl branch and add them then. 2021-11-01 05:42:32 -04:00
Matthew Borkowski
92d2aa1b48 astgen.zig: use scratch buffer for temporary allocations in switchExpr and WipMembers 2021-11-01 05:42:25 -04:00
Matthew Borkowski
5760ba949f astgen.zig: simplify container functions by pulling out common processing of members 2021-11-01 05:42:19 -04:00
Matthew Borkowski
e712f87a66 astgen.zig: replace WipDecls with WipMembers, use one allocation to collect container decls, fields, and bits, instead of up to four 2021-11-01 05:41:37 -04:00
Matthew Borkowski
f0260555d6 astgen.zig: simplify switchExpr and collect payload in one ArrayList instead of three 2021-11-01 05:28:03 -04:00
Matthew Borkowski
a0bf620fbf astgen.zig: avoid unnecessary allocation in identifier for @"" syntax 2021-11-01 05:27:52 -04:00
Matthew Borkowski
2561be2e34 astgen.zig: avoid temporary allocations in arrayInit* and structInit*, callExpr, errorSetDecl, typeOf, and builtinCall's compile_log branch 2021-11-01 05:09:19 -04:00
Ryan Liptak
a343758141 Update ensureTotalCapacity to ensureTotalCapacityPrecise where it makes sense
These calls are all late-initialization of ArrayList's that were initialized outside the current scope. This allows us to still get the potential memory-saving benefits of the 'precision' of initCapacity.
2021-11-01 00:57:33 -07:00