Commit Graph

107 Commits

Author SHA1 Message Date
John Schmidt
f47db0a0db sema: use pl_op for @select 2022-03-25 16:13:54 +01:00
John Schmidt
12d5efcbe6 stage2: implement @select 2022-03-25 16:13:54 +01:00
Andrew Kelley
98b932cfab fix merge conflicts 2022-03-22 20:17:43 -07:00
joachimschmidt557
be1cca3416 stage2 ARM: implement comparison of optional pointers 2022-03-22 20:16:05 -07:00
joachimschmidt557
95e166b2e1 stage2 ARM: implement min, max for integers <= 32 bits 2022-03-22 20:16:05 -07:00
joachimschmidt557
62529a291b stage2 ARM: More support for error unions 2022-03-22 20:16:05 -07:00
joachimschmidt557
a4e8294c91 stage2 ARM: change semantics of MCValue.stack_argument_offset
MCValue.stack_argument_offset now has the same semantics as
MCValue.stack_offset
2022-03-22 20:16:05 -07:00
joachimschmidt557
6ac04d8fd7 stage2 ARM: change semantics of MCValue.stack_offset
A stack_offset will now denote the exact offset applied to the start
of the stack frame (=fp when frame pointer is emitted)
2022-03-22 20:16:05 -07:00
Andrew Kelley
593130ce0a stage2: lazy @alignOf
Add a `target` parameter to every function that deals with Type and
Value.
2022-03-22 15:45:58 -07:00
William Sengir
0f48307041 stage2: add AIR instruction cmp_vector
The existing `cmp_*` instructions get their result type from `lhs`, but
vector comparison will always return a vector of bools with only the
length derived from its operands. This necessitates the creation of a
new AIR instruction.
2022-03-21 16:54:19 -07:00
Veikka Tuominen
a8520fbd0f stage2: add dbg_block_{begin,end} instruction 2022-03-19 11:20:38 +02:00
joachimschmidt557
c32e2c4d3c stage2 ARM: remove MCValue.embedded_in_code 2022-03-18 12:19:22 +01:00
joachimschmidt557
3ecba7d7a2 stage2 ARM: implement slice_elem_ptr, ptr_elem_ptr 2022-03-18 12:12:14 +01:00
Andrew Kelley
7233a3324a stage2: implement @reduce
Notably, Value.eql and Value.hash are improved to treat NaN as equal to
itself, so that Type/Value can be hash map keys. Likewise float hashing
normalizes the float value before computing the hash.
2022-03-17 17:24:35 -07:00
joachimschmidt557
dcc1de12b0 stage2 ARM: implement addwrap, subwrap, mulwrap 2022-03-16 20:20:07 +01:00
joachimschmidt557
2412ac2c5f stage2 ARM: fix shl for ints with bits < 32 2022-03-16 20:20:07 +01:00
joachimschmidt557
0eebdfcad3 stage2 ARM: fix bitwise negation of ints with bits < 32 2022-03-16 20:20:07 +01:00
joachimschmidt557
ca1ffb0951 stage2 ARM: genSetStack for stack_argument_offset 2022-03-16 20:19:58 +01:00
Veikka Tuominen
d83a26f068 stage2 llvm: keep track of inlined functions 2022-03-16 10:53:41 +02:00
Veikka Tuominen
0343811836 Sema: emit dbg_func around inline calls 2022-03-16 09:34:26 +02:00
Andrew Kelley
0bc9635490 stage2: add debug info for locals in the LLVM backend
Adds 2 new AIR instructions:
 * dbg_var_ptr
 * dbg_var_val

Sema no longer emits dbg_stmt AIR instructions when strip=true.

LLVM backend: fixed lowerPtrToVoid when calling ptrAlignment on
the element type is problematic.

LLVM backend: fixed alloca instructions improperly getting debug
location annotated, causing chaotic debug info behavior.

zig_llvm.cpp: fixed incorrect bindings for a function that should use
unsigned integers for line and column.

A bunch of C test cases regressed because the new dbg_var AIR
instructions caused their operands to be alive, exposing latent bugs.
Mostly it's just a problem that the C backend lowers mutable
and const slices to the same C type, so we need to represent that in the
C backend instead of printing two duplicate typedefs.
2022-03-13 03:41:31 -04:00
Andrew Kelley
4c1cc4d8d9 Merge pull request #11120 from Vexu/stage2
Stage2: make std.rand tests pass
2022-03-11 13:48:28 -05:00
joachimschmidt557
4590e980f7 stage2 ARM: implement caller-saved registers 2022-03-11 14:12:11 +01:00
joachimschmidt557
06058ed6f3 stage2 regalloc: replace Register.allocIndex with generic indexOfReg
* callee_preserved_regs and other ABI-specific information have been
moved to the respective abi.zig files
2022-03-11 13:29:16 +01:00
Veikka Tuominen
cba68090a6 stage2: implement @shuffle at runtime 2022-03-11 13:12:32 +02:00
Andrew Kelley
078037ab9b stage2: passing threadlocal tests for x86_64-linux
* use the real start code for LLVM backend with x86_64-linux
   - there is still a check for zig_backend after initializing the TLS
     area to skip some stuff.
 * introduce new AIR instructions and implement them for the LLVM
   backend. They are the same as `call` except with a modifier.
   - call_always_tail
   - call_never_tail
   - call_never_inline
 * LLVM backend calls hasRuntimeBitsIgnoringComptime in more places to
   avoid unnecessarily depending on comptimeOnly being resolved for some
   types.
 * LLVM backend: remove duplicate code for setting linkage and value
   name. The canonical place for this is in `updateDeclExports`.
 * LLVM backend: do some assembly template massaging to make `%%`
   rendered as `%`. More hacks will be needed to make inline assembly
   catch up with stage1.
2022-03-11 00:04:42 -07:00
joachimschmidt557
95fc41b2b4 stage2 ARM: implement ret_load 2022-03-08 21:10:04 +01:00
joachimschmidt557
3ea603c82a stage2 ARM: implement ptr_add, ptr_sub for all element sizes
Also reduces slice_elem_val to ptr_add, simplifying the implementation
2022-03-08 10:54:08 +01:00
Andrew Kelley
71b8760d3b stage2: rework @mulAdd
* mul_add AIR instruction: use `pl_op` instead of `ty_pl`. The type is
   always the same as the operand; no need to waste bytes redundantly
   storing the type.
 * AstGen: use coerced_ty for all the operands except for one which we
   use to communicate the type.
 * Sema: use the correct source location for requireRuntimeBlock in
   handling of `@mulAdd`.
 * native backends: handle liveness even for the functions that are
   TODO.
 * C backend: implement `@mulAdd`. It lowers to libc calls.
 * LLVM backend: make `@mulAdd` handle all float types.
   - improved fptrunc and fpext to handle f80 with compiler-rt calls.
 * Value.mulAdd: handle all float types and use the `@mulAdd` builtin.
 * behavior tests: revert the changes to testing `@mulAdd`. These
   changes broke the test coverage, making it only tested at
   compile-time.

Improved f80 support:
 * std.math.fma handles f80
 * move fma functions from freestanding libc to compiler-rt
   - add __fmax and fmal
   - make __fmax and fmaq only exported when they don't alias fmal.
   - make their linkage weak just like the rest of compiler-rt symbols.
 * removed `longDoubleIsF128` and replaced it with `longDoubleIs` which
   takes a type as a parameter. The implementation is now more accurate
   and handles more targets. Similarly, in stage2 the function
   CTypes.sizeInBits is more accurate for long double for more targets.
2022-03-06 16:11:39 -07:00
John Schmidt
6637335981 stage2: implement @mulAdd for scalar floats 2022-03-06 15:36:56 -07:00
joachimschmidt557
d486a7b811 stage2 ARM: generate less no-op branches
The checks detecting such no-op branches (essentially instructions
that branch to the instruction immediately following the branch) were
tightened to catch more of these occurrences.
2022-03-04 23:28:14 +01:00
Luuk de Gram
43cb19ea4d wasm: Implement @wasmMemoryGrow builtin
Similarly to the other wasm builtin, this implements the grow variation where the memory
index is a comptime known value. The operand as well as the result are runtime values.
This also verifies during semantic analysis the target we're building for is wasm, or else
emits a compilation error. This means that other backends do not have to handle this AIR instruction,
other than the wasm and LLVM backends.
2022-03-03 16:33:46 -07:00
joachimschmidt557
ca97caab8a stage2 ARM: implement return types with abi size > 4 2022-03-01 09:14:52 +01:00
Andrew Kelley
d5100dc815 stage2: fix frame_address AIR instruction
Various places were assuming different union tags. Now it is
consistently a no-op instruction, just like the similar
instruction ret_addr.
2022-02-28 13:38:33 -07:00
Veikka Tuominen
90bce11f62 stage2: implement @frameAddress 2022-02-28 13:09:14 -07:00
joachimschmidt557
1bf8da19e1 stage2 ARM: implement slice and array_to_slice 2022-02-27 21:38:56 +01:00
joachimschmidt557
91fbcf7093 stage2 ARM: enable more behavior tests 2022-02-27 21:38:56 +01:00
Andrew Kelley
2687b8f7f4 stage2: implement @unionInit
The ZIR instruction `union_init_ptr` is renamed to `union_init`.
I made it always use by-value semantics for now, not taking the time to
invest in result location semantics, in case we decide to change the
rules for unions. This way is much simpler.

There is a new AIR instruction: union_init. This is for a comptime known
tag, runtime-known field value.
vector_init is renamed to aggregate_init, which solves a TODO comment.
2022-02-26 20:59:36 -07:00
joachimschmidt557
f48f4baf67 stage2 ARM: generate correct variants of ldr instruction
When loading an i16 for example, generate ldrsh instead of ldrh
2022-02-26 13:00:01 +01:00
joachimschmidt557
8ef80cfaab stage2 ARM: implement truncate to ints with bits <= 32 2022-02-26 12:59:57 +01:00
Veikka Tuominen
b034c45b2b stage2: implement fieldParentPtr 2022-02-24 19:48:34 +02:00
Andrew Kelley
74303a3d95 Merge pull request #10925 from Vexu/stage2
stage2: support anon init through error unions and optionals
2022-02-21 14:18:17 -05:00
Veikka Tuominen
27c63bf433 stage2: implement errunion_payload_ptr_set 2022-02-19 20:48:00 +02:00
joachimschmidt557
669603029e stage2 ARM: implement airCmp with binOp lowering mechanism 2022-02-19 12:12:29 +01:00
joachimschmidt557
c29bf2f51a stage2 ARM: move shl, shr to binOp lowering mechanism 2022-02-19 12:06:34 +01:00
joachimschmidt557
3b1762bb47 stage2 ARM: fix boolean and bitwise not 2022-02-19 12:06:34 +01:00
joachimschmidt557
7b833b2fba stage2 ARM: move {bool,bit}_{or,and} to binOp lowering mechanism 2022-02-19 12:06:34 +01:00
joachimschmidt557
985a442f46 stage2 ARM: move mul to binOp lowering mechanism 2022-02-19 12:06:34 +01:00
joachimschmidt557
67e3346633 stage2 ARM: move add and sub to new binOp lowering mechanism 2022-02-19 12:06:30 +01:00
joachimschmidt557
23915c2c44 stage2 ARM: simplify invocations of genInlineMemcpy 2022-02-19 12:04:54 +01:00