cpu.h (9011B) - Raw
1 /*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * Copyright (c) 2014-2016 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * William Jolitz. 8 * 9 * Portions of this software were developed by Andrew Turner 10 * under sponsorship from the FreeBSD Foundation 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)cpu.h 5.4 (Berkeley) 5/9/91 37 * from: FreeBSD: src/sys/i386/include/cpu.h,v 1.62 2001/06/29 38 */ 39 40 #ifdef __arm__ 41 #include <arm/cpu.h> 42 #else /* !__arm__ */ 43 44 #ifndef _MACHINE_CPU_H_ 45 #define _MACHINE_CPU_H_ 46 47 #if !defined(__ASSEMBLER__) 48 #include <machine/atomic.h> 49 #include <machine/frame.h> 50 #endif 51 #include <machine/armreg.h> 52 53 #define TRAPF_PC(tfp) ((tfp)->tf_elr) 54 #define TRAPF_USERMODE(tfp) (((tfp)->tf_spsr & PSR_M_MASK) == PSR_M_EL0t) 55 56 #define cpu_getstack(td) ((td)->td_frame->tf_sp) 57 #define cpu_setstack(td, sp) ((td)->td_frame->tf_sp = (sp)) 58 #define cpu_spinwait() __asm __volatile("yield" ::: "memory") 59 #define cpu_lock_delay() DELAY(1) 60 61 /* Extract CPU affinity levels 0-3 */ 62 #define CPU_AFF0(mpidr) (u_int)(((mpidr) >> 0) & 0xff) 63 #define CPU_AFF1(mpidr) (u_int)(((mpidr) >> 8) & 0xff) 64 #define CPU_AFF2(mpidr) (u_int)(((mpidr) >> 16) & 0xff) 65 #define CPU_AFF3(mpidr) (u_int)(((mpidr) >> 32) & 0xff) 66 #define CPU_AFF0_MASK 0xffUL 67 #define CPU_AFF1_MASK 0xff00UL 68 #define CPU_AFF2_MASK 0xff0000UL 69 #define CPU_AFF3_MASK 0xff00000000UL 70 #define CPU_AFF_MASK (CPU_AFF0_MASK | CPU_AFF1_MASK | \ 71 CPU_AFF2_MASK| CPU_AFF3_MASK) /* Mask affinity fields in MPIDR_EL1 */ 72 73 #ifdef _KERNEL 74 75 #define CPU_IMPL_ARM 0x41 76 #define CPU_IMPL_BROADCOM 0x42 77 #define CPU_IMPL_CAVIUM 0x43 78 #define CPU_IMPL_DEC 0x44 79 #define CPU_IMPL_FUJITSU 0x46 80 #define CPU_IMPL_INFINEON 0x49 81 #define CPU_IMPL_FREESCALE 0x4D 82 #define CPU_IMPL_NVIDIA 0x4E 83 #define CPU_IMPL_APM 0x50 84 #define CPU_IMPL_QUALCOMM 0x51 85 #define CPU_IMPL_MARVELL 0x56 86 #define CPU_IMPL_APPLE 0x61 87 #define CPU_IMPL_INTEL 0x69 88 #define CPU_IMPL_AMPERE 0xC0 89 90 /* ARM Part numbers */ 91 #define CPU_PART_FOUNDATION 0xD00 92 #define CPU_PART_CORTEX_A34 0xD02 93 #define CPU_PART_CORTEX_A53 0xD03 94 #define CPU_PART_CORTEX_A35 0xD04 95 #define CPU_PART_CORTEX_A55 0xD05 96 #define CPU_PART_CORTEX_A65 0xD06 97 #define CPU_PART_CORTEX_A57 0xD07 98 #define CPU_PART_CORTEX_A72 0xD08 99 #define CPU_PART_CORTEX_A73 0xD09 100 #define CPU_PART_CORTEX_A75 0xD0A 101 #define CPU_PART_CORTEX_A76 0xD0B 102 #define CPU_PART_NEOVERSE_N1 0xD0C 103 #define CPU_PART_CORTEX_A77 0xD0D 104 #define CPU_PART_CORTEX_A76AE 0xD0E 105 #define CPU_PART_AEM_V8 0xD0F 106 #define CPU_PART_NEOVERSE_V1 0xD40 107 #define CPU_PART_CORTEX_A78 0xD41 108 #define CPU_PART_CORTEX_A65AE 0xD43 109 #define CPU_PART_CORTEX_X1 0xD44 110 #define CPU_PART_CORTEX_A510 0xD46 111 #define CPU_PART_CORTEX_A710 0xD47 112 #define CPU_PART_CORTEX_X2 0xD48 113 #define CPU_PART_NEOVERSE_N2 0xD49 114 #define CPU_PART_NEOVERSE_E1 0xD4A 115 #define CPU_PART_CORTEX_A78C 0xD4B 116 #define CPU_PART_CORTEX_X1C 0xD4C 117 #define CPU_PART_CORTEX_A715 0xD4D 118 #define CPU_PART_CORTEX_X3 0xD4E 119 #define CPU_PART_NEOVERSE_V2 0xD4F 120 121 /* Cavium Part numbers */ 122 #define CPU_PART_THUNDERX 0x0A1 123 #define CPU_PART_THUNDERX_81XX 0x0A2 124 #define CPU_PART_THUNDERX_83XX 0x0A3 125 #define CPU_PART_THUNDERX2 0x0AF 126 127 #define CPU_REV_THUNDERX_1_0 0x00 128 #define CPU_REV_THUNDERX_1_1 0x01 129 130 #define CPU_REV_THUNDERX2_0 0x00 131 132 /* APM / Ampere Part Number */ 133 #define CPU_PART_EMAG8180 0x000 134 135 /* Qualcomm */ 136 #define CPU_PART_KRYO400_GOLD 0x804 137 #define CPU_PART_KRYO400_SILVER 0x805 138 139 /* Apple part numbers */ 140 #define CPU_PART_M1_ICESTORM 0x022 141 #define CPU_PART_M1_FIRESTORM 0x023 142 #define CPU_PART_M1_ICESTORM_PRO 0x024 143 #define CPU_PART_M1_FIRESTORM_PRO 0x025 144 #define CPU_PART_M1_ICESTORM_MAX 0x028 145 #define CPU_PART_M1_FIRESTORM_MAX 0x029 146 #define CPU_PART_M2_BLIZZARD 0x032 147 #define CPU_PART_M2_AVALANCHE 0x033 148 #define CPU_PART_M2_BLIZZARD_PRO 0x034 149 #define CPU_PART_M2_AVALANCHE_PRO 0x035 150 #define CPU_PART_M2_BLIZZARD_MAX 0x038 151 #define CPU_PART_M2_AVALANCHE_MAX 0x039 152 153 #define CPU_IMPL(midr) (((midr) >> 24) & 0xff) 154 #define CPU_PART(midr) (((midr) >> 4) & 0xfff) 155 #define CPU_VAR(midr) (((midr) >> 20) & 0xf) 156 #define CPU_ARCH(midr) (((midr) >> 16) & 0xf) 157 #define CPU_REV(midr) (((midr) >> 0) & 0xf) 158 159 #define CPU_IMPL_TO_MIDR(val) (((val) & 0xff) << 24) 160 #define CPU_PART_TO_MIDR(val) (((val) & 0xfff) << 4) 161 #define CPU_VAR_TO_MIDR(val) (((val) & 0xf) << 20) 162 #define CPU_ARCH_TO_MIDR(val) (((val) & 0xf) << 16) 163 #define CPU_REV_TO_MIDR(val) (((val) & 0xf) << 0) 164 165 #define CPU_IMPL_MASK (0xff << 24) 166 #define CPU_PART_MASK (0xfff << 4) 167 #define CPU_VAR_MASK (0xf << 20) 168 #define CPU_ARCH_MASK (0xf << 16) 169 #define CPU_REV_MASK (0xf << 0) 170 171 #define CPU_ID_RAW(impl, part, var, rev) \ 172 (CPU_IMPL_TO_MIDR((impl)) | \ 173 CPU_PART_TO_MIDR((part)) | CPU_VAR_TO_MIDR((var)) | \ 174 CPU_REV_TO_MIDR((rev))) 175 176 #define CPU_MATCH(mask, impl, part, var, rev) \ 177 (((mask) & PCPU_GET(midr)) == \ 178 ((mask) & CPU_ID_RAW((impl), (part), (var), (rev)))) 179 180 #define CPU_MATCH_RAW(mask, devid) \ 181 (((mask) & PCPU_GET(midr)) == ((mask) & (devid))) 182 183 /* 184 * Chip-specific errata. This defines are intended to be 185 * booleans used within if statements. When an appropriate 186 * kernel option is disabled, these defines must be defined 187 * as 0 to allow the compiler to remove a dead code thus 188 * produce better optimized kernel image. 189 */ 190 /* 191 * Vendor: Cavium 192 * Chip: ThunderX 193 * Revision(s): Pass 1.0, Pass 1.1 194 */ 195 #ifdef THUNDERX_PASS_1_1_ERRATA 196 #define CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 \ 197 (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK | CPU_REV_MASK, \ 198 CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, CPU_REV_THUNDERX_1_0) || \ 199 CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK | CPU_REV_MASK, \ 200 CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, CPU_REV_THUNDERX_1_1)) 201 #else 202 #define CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 0 203 #endif 204 205 #if !defined(__ASSEMBLER__) 206 extern char btext[]; 207 extern char etext[]; 208 209 extern uint64_t __cpu_affinity[]; 210 211 struct arm64_addr_mask; 212 extern struct arm64_addr_mask elf64_addr_mask; 213 214 void cpu_halt(void) __dead2; 215 void cpu_reset(void) __dead2; 216 void fork_trampoline(void); 217 void identify_cache(uint64_t); 218 void identify_cpu(u_int); 219 void install_cpu_errata(void); 220 221 /* Pointer Authentication Code (PAC) support */ 222 void ptrauth_init(void); 223 void ptrauth_fork(struct thread *, struct thread *); 224 void ptrauth_exec(struct thread *); 225 void ptrauth_copy_thread(struct thread *, struct thread *); 226 void ptrauth_thread_alloc(struct thread *); 227 void ptrauth_thread0(struct thread *); 228 #ifdef SMP 229 void ptrauth_mp_start(uint64_t); 230 #endif 231 232 /* Functions to read the sanitised view of the special registers */ 233 void update_special_regs(u_int); 234 bool extract_user_id_field(u_int, u_int, uint8_t *); 235 bool get_kernel_reg(u_int, uint64_t *); 236 bool get_kernel_reg_masked(u_int, uint64_t *, uint64_t); 237 238 void cpu_desc_init(void); 239 240 #define CPU_AFFINITY(cpu) __cpu_affinity[(cpu)] 241 #define CPU_CURRENT_SOCKET \ 242 (CPU_AFF2(CPU_AFFINITY(PCPU_GET(cpuid)))) 243 244 static __inline uint64_t 245 get_cyclecount(void) 246 { 247 uint64_t ret; 248 249 ret = READ_SPECIALREG(cntvct_el0); 250 251 return (ret); 252 } 253 254 #define ADDRESS_TRANSLATE_FUNC(stage) \ 255 static inline uint64_t \ 256 arm64_address_translate_ ##stage (uint64_t addr) \ 257 { \ 258 uint64_t ret; \ 259 \ 260 __asm __volatile( \ 261 "at " __STRING(stage) ", %1 \n" \ 262 "isb \n" \ 263 "mrs %0, par_el1" : "=r"(ret) : "r"(addr)); \ 264 \ 265 return (ret); \ 266 } 267 268 ADDRESS_TRANSLATE_FUNC(s1e0r) 269 ADDRESS_TRANSLATE_FUNC(s1e0w) 270 ADDRESS_TRANSLATE_FUNC(s1e1r) 271 ADDRESS_TRANSLATE_FUNC(s1e1w) 272 273 #endif /* !__ASSEMBLER__ */ 274 #endif 275 276 #endif /* !_MACHINE_CPU_H_ */ 277 278 #endif /* !__arm__ */