amdgpu_drm.h (40793B) - Raw
1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * Copyright 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 #ifndef __AMDGPU_DRM_H__ 33 #define __AMDGPU_DRM_H__ 34 35 #include "drm.h" 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif 40 41 #define DRM_AMDGPU_GEM_CREATE 0x00 42 #define DRM_AMDGPU_GEM_MMAP 0x01 43 #define DRM_AMDGPU_CTX 0x02 44 #define DRM_AMDGPU_BO_LIST 0x03 45 #define DRM_AMDGPU_CS 0x04 46 #define DRM_AMDGPU_INFO 0x05 47 #define DRM_AMDGPU_GEM_METADATA 0x06 48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 49 #define DRM_AMDGPU_GEM_VA 0x08 50 #define DRM_AMDGPU_WAIT_CS 0x09 51 #define DRM_AMDGPU_GEM_OP 0x10 52 #define DRM_AMDGPU_GEM_USERPTR 0x11 53 #define DRM_AMDGPU_WAIT_FENCES 0x12 54 #define DRM_AMDGPU_VM 0x13 55 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 56 #define DRM_AMDGPU_SCHED 0x15 57 58 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 59 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 60 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 61 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 62 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 63 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 64 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 65 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 66 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 67 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 68 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 69 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 70 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 71 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 72 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 73 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 74 75 /** 76 * DOC: memory domains 77 * 78 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. 79 * Memory in this pool could be swapped out to disk if there is pressure. 80 * 81 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the 82 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous 83 * pages of system memory, allows GPU access system memory in a linearized 84 * fashion. 85 * 86 * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory 87 * carved out by the BIOS. 88 * 89 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data 90 * across shader threads. 91 * 92 * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the 93 * execution of all the waves on a device. 94 * 95 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines 96 * for appending data. 97 * 98 * %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for 99 * signalling user mode queues. 100 */ 101 #define AMDGPU_GEM_DOMAIN_CPU 0x1 102 #define AMDGPU_GEM_DOMAIN_GTT 0x2 103 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 104 #define AMDGPU_GEM_DOMAIN_GDS 0x8 105 #define AMDGPU_GEM_DOMAIN_GWS 0x10 106 #define AMDGPU_GEM_DOMAIN_OA 0x20 107 #define AMDGPU_GEM_DOMAIN_DOORBELL 0x40 108 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 109 AMDGPU_GEM_DOMAIN_GTT | \ 110 AMDGPU_GEM_DOMAIN_VRAM | \ 111 AMDGPU_GEM_DOMAIN_GDS | \ 112 AMDGPU_GEM_DOMAIN_GWS | \ 113 AMDGPU_GEM_DOMAIN_OA | \ 114 AMDGPU_GEM_DOMAIN_DOORBELL) 115 116 /* Flag that CPU access will be required for the case of VRAM domain */ 117 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 118 /* Flag that CPU access will not work, this VRAM domain is invisible */ 119 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 120 /* Flag that USWC attributes should be used for GTT */ 121 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 122 /* Flag that the memory should be in VRAM and cleared */ 123 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 124 /* Flag that allocating the BO should use linear VRAM */ 125 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 126 /* Flag that BO is always valid in this VM */ 127 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 128 /* Flag that BO sharing will be explicitly synchronized */ 129 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 130 /* Flag that indicates allocating MQD gart on GFX9, where the mtype 131 * for the second page onward should be set to NC. It should never 132 * be used by user space applications. 133 */ 134 #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) 135 /* Flag that BO may contain sensitive data that must be wiped before 136 * releasing the memory 137 */ 138 #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 139 /* Flag that BO will be encrypted and that the TMZ bit should be 140 * set in the PTEs when mapping this buffer via GPUVM or 141 * accessing it with various hw blocks 142 */ 143 #define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) 144 /* Flag that BO will be used only in preemptible context, which does 145 * not require GTT memory accounting 146 */ 147 #define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11) 148 /* Flag that BO can be discarded under memory pressure without keeping the 149 * content. 150 */ 151 #define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12) 152 /* Flag that BO is shared coherently between multiple devices or CPU threads. 153 * May depend on GPU instructions to flush caches to system scope explicitly. 154 * 155 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 156 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 157 */ 158 #define AMDGPU_GEM_CREATE_COHERENT (1 << 13) 159 /* Flag that BO should not be cached by GPU. Coherent without having to flush 160 * GPU caches explicitly 161 * 162 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 163 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 164 */ 165 #define AMDGPU_GEM_CREATE_UNCACHED (1 << 14) 166 /* Flag that BO should be coherent across devices when using device-level 167 * atomics. May depend on GPU instructions to flush caches to device scope 168 * explicitly, promoting them to system scope automatically. 169 * 170 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 171 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 172 */ 173 #define AMDGPU_GEM_CREATE_EXT_COHERENT (1 << 15) 174 /* Set PTE.D and recompress during GTT->VRAM moves according to TILING flags. */ 175 #define AMDGPU_GEM_CREATE_GFX12_DCC (1 << 16) 176 177 struct drm_amdgpu_gem_create_in { 178 /** the requested memory size */ 179 __u64 bo_size; 180 /** physical start_addr alignment in bytes for some HW requirements */ 181 __u64 alignment; 182 /** the requested memory domains */ 183 __u64 domains; 184 /** allocation flags */ 185 __u64 domain_flags; 186 }; 187 188 struct drm_amdgpu_gem_create_out { 189 /** returned GEM object handle */ 190 __u32 handle; 191 __u32 _pad; 192 }; 193 194 union drm_amdgpu_gem_create { 195 struct drm_amdgpu_gem_create_in in; 196 struct drm_amdgpu_gem_create_out out; 197 }; 198 199 /** Opcode to create new residency list. */ 200 #define AMDGPU_BO_LIST_OP_CREATE 0 201 /** Opcode to destroy previously created residency list */ 202 #define AMDGPU_BO_LIST_OP_DESTROY 1 203 /** Opcode to update resource information in the list */ 204 #define AMDGPU_BO_LIST_OP_UPDATE 2 205 206 struct drm_amdgpu_bo_list_in { 207 /** Type of operation */ 208 __u32 operation; 209 /** Handle of list or 0 if we want to create one */ 210 __u32 list_handle; 211 /** Number of BOs in list */ 212 __u32 bo_number; 213 /** Size of each element describing BO */ 214 __u32 bo_info_size; 215 /** Pointer to array describing BOs */ 216 __u64 bo_info_ptr; 217 }; 218 219 struct drm_amdgpu_bo_list_entry { 220 /** Handle of BO */ 221 __u32 bo_handle; 222 /** New (if specified) BO priority to be used during migration */ 223 __u32 bo_priority; 224 }; 225 226 struct drm_amdgpu_bo_list_out { 227 /** Handle of resource list */ 228 __u32 list_handle; 229 __u32 _pad; 230 }; 231 232 union drm_amdgpu_bo_list { 233 struct drm_amdgpu_bo_list_in in; 234 struct drm_amdgpu_bo_list_out out; 235 }; 236 237 /* context related */ 238 #define AMDGPU_CTX_OP_ALLOC_CTX 1 239 #define AMDGPU_CTX_OP_FREE_CTX 2 240 #define AMDGPU_CTX_OP_QUERY_STATE 3 241 #define AMDGPU_CTX_OP_QUERY_STATE2 4 242 #define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5 243 #define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6 244 245 /* GPU reset status */ 246 #define AMDGPU_CTX_NO_RESET 0 247 /* this the context caused it */ 248 #define AMDGPU_CTX_GUILTY_RESET 1 249 /* some other context caused it */ 250 #define AMDGPU_CTX_INNOCENT_RESET 2 251 /* unknown cause */ 252 #define AMDGPU_CTX_UNKNOWN_RESET 3 253 254 /* indicate gpu reset occurred after ctx created */ 255 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 256 /* indicate vram lost occurred after ctx created */ 257 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 258 /* indicate some job from this context once cause gpu hang */ 259 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 260 /* indicate some errors are detected by RAS */ 261 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) 262 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) 263 /* indicate that the reset hasn't completed yet */ 264 #define AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS (1<<5) 265 266 /* Context priority level */ 267 #define AMDGPU_CTX_PRIORITY_UNSET -2048 268 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 269 #define AMDGPU_CTX_PRIORITY_LOW -512 270 #define AMDGPU_CTX_PRIORITY_NORMAL 0 271 /* 272 * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires 273 * CAP_SYS_NICE or DRM_MASTER 274 */ 275 #define AMDGPU_CTX_PRIORITY_HIGH 512 276 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 277 278 /* select a stable profiling pstate for perfmon tools */ 279 #define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf 280 #define AMDGPU_CTX_STABLE_PSTATE_NONE 0 281 #define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1 282 #define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2 283 #define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3 284 #define AMDGPU_CTX_STABLE_PSTATE_PEAK 4 285 286 struct drm_amdgpu_ctx_in { 287 /** AMDGPU_CTX_OP_* */ 288 __u32 op; 289 /** Flags */ 290 __u32 flags; 291 __u32 ctx_id; 292 /** AMDGPU_CTX_PRIORITY_* */ 293 __s32 priority; 294 }; 295 296 union drm_amdgpu_ctx_out { 297 struct { 298 __u32 ctx_id; 299 __u32 _pad; 300 } alloc; 301 302 struct { 303 /** For future use, no flags defined so far */ 304 __u64 flags; 305 /** Number of resets caused by this context so far. */ 306 __u32 hangs; 307 /** Reset status since the last call of the ioctl. */ 308 __u32 reset_status; 309 } state; 310 311 struct { 312 __u32 flags; 313 __u32 _pad; 314 } pstate; 315 }; 316 317 union drm_amdgpu_ctx { 318 struct drm_amdgpu_ctx_in in; 319 union drm_amdgpu_ctx_out out; 320 }; 321 322 /* vm ioctl */ 323 #define AMDGPU_VM_OP_RESERVE_VMID 1 324 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 325 326 struct drm_amdgpu_vm_in { 327 /** AMDGPU_VM_OP_* */ 328 __u32 op; 329 __u32 flags; 330 }; 331 332 struct drm_amdgpu_vm_out { 333 /** For future use, no flags defined so far */ 334 __u64 flags; 335 }; 336 337 union drm_amdgpu_vm { 338 struct drm_amdgpu_vm_in in; 339 struct drm_amdgpu_vm_out out; 340 }; 341 342 /* sched ioctl */ 343 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 344 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 345 346 struct drm_amdgpu_sched_in { 347 /* AMDGPU_SCHED_OP_* */ 348 __u32 op; 349 __u32 fd; 350 /** AMDGPU_CTX_PRIORITY_* */ 351 __s32 priority; 352 __u32 ctx_id; 353 }; 354 355 union drm_amdgpu_sched { 356 struct drm_amdgpu_sched_in in; 357 }; 358 359 /* 360 * This is not a reliable API and you should expect it to fail for any 361 * number of reasons and have fallback path that do not use userptr to 362 * perform any operation. 363 */ 364 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 365 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 366 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 367 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 368 369 struct drm_amdgpu_gem_userptr { 370 __u64 addr; 371 __u64 size; 372 /* AMDGPU_GEM_USERPTR_* */ 373 __u32 flags; 374 /* Resulting GEM handle */ 375 __u32 handle; 376 }; 377 378 /* SI-CI-VI: */ 379 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 380 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 381 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 382 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 383 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 384 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 385 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 386 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 387 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 388 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 389 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 390 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 391 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 392 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 393 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 394 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 395 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 396 397 /* GFX9 - GFX11: */ 398 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 399 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 400 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 401 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 402 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 403 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 404 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 405 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 406 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 407 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 408 #define AMDGPU_TILING_SCANOUT_SHIFT 63 409 #define AMDGPU_TILING_SCANOUT_MASK 0x1 410 411 /* GFX12 and later: */ 412 #define AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT 0 413 #define AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK 0x7 414 /* These are DCC recompression settings for memory management: */ 415 #define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3 416 #define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* 0:64B, 1:128B, 2:256B */ 417 #define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT 5 418 #define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK 0x7 /* CB_COLOR0_INFO.NUMBER_TYPE */ 419 #define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT 8 420 #define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK 0x3f /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */ 421 /* When clearing the buffer or moving it from VRAM to GTT, don't compress and set DCC metadata 422 * to uncompressed. Set when parts of an allocation bypass DCC and read raw data. */ 423 #define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_SHIFT 14 424 #define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_MASK 0x1 425 /* bit gap */ 426 #define AMDGPU_TILING_GFX12_SCANOUT_SHIFT 63 427 #define AMDGPU_TILING_GFX12_SCANOUT_MASK 0x1 428 429 /* Set/Get helpers for tiling flags. */ 430 #define AMDGPU_TILING_SET(field, value) \ 431 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 432 #define AMDGPU_TILING_GET(value, field) \ 433 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 434 435 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 436 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 437 438 /** The same structure is shared for input/output */ 439 struct drm_amdgpu_gem_metadata { 440 /** GEM Object handle */ 441 __u32 handle; 442 /** Do we want get or set metadata */ 443 __u32 op; 444 struct { 445 /** For future use, no flags defined so far */ 446 __u64 flags; 447 /** family specific tiling info */ 448 __u64 tiling_info; 449 __u32 data_size_bytes; 450 __u32 data[64]; 451 } data; 452 }; 453 454 struct drm_amdgpu_gem_mmap_in { 455 /** the GEM object handle */ 456 __u32 handle; 457 __u32 _pad; 458 }; 459 460 struct drm_amdgpu_gem_mmap_out { 461 /** mmap offset from the vma offset manager */ 462 __u64 addr_ptr; 463 }; 464 465 union drm_amdgpu_gem_mmap { 466 struct drm_amdgpu_gem_mmap_in in; 467 struct drm_amdgpu_gem_mmap_out out; 468 }; 469 470 struct drm_amdgpu_gem_wait_idle_in { 471 /** GEM object handle */ 472 __u32 handle; 473 /** For future use, no flags defined so far */ 474 __u32 flags; 475 /** Absolute timeout to wait */ 476 __u64 timeout; 477 }; 478 479 struct drm_amdgpu_gem_wait_idle_out { 480 /** BO status: 0 - BO is idle, 1 - BO is busy */ 481 __u32 status; 482 /** Returned current memory domain */ 483 __u32 domain; 484 }; 485 486 union drm_amdgpu_gem_wait_idle { 487 struct drm_amdgpu_gem_wait_idle_in in; 488 struct drm_amdgpu_gem_wait_idle_out out; 489 }; 490 491 struct drm_amdgpu_wait_cs_in { 492 /* Command submission handle 493 * handle equals 0 means none to wait for 494 * handle equals ~0ull means wait for the latest sequence number 495 */ 496 __u64 handle; 497 /** Absolute timeout to wait */ 498 __u64 timeout; 499 __u32 ip_type; 500 __u32 ip_instance; 501 __u32 ring; 502 __u32 ctx_id; 503 }; 504 505 struct drm_amdgpu_wait_cs_out { 506 /** CS status: 0 - CS completed, 1 - CS still busy */ 507 __u64 status; 508 }; 509 510 union drm_amdgpu_wait_cs { 511 struct drm_amdgpu_wait_cs_in in; 512 struct drm_amdgpu_wait_cs_out out; 513 }; 514 515 struct drm_amdgpu_fence { 516 __u32 ctx_id; 517 __u32 ip_type; 518 __u32 ip_instance; 519 __u32 ring; 520 __u64 seq_no; 521 }; 522 523 struct drm_amdgpu_wait_fences_in { 524 /** This points to uint64_t * which points to fences */ 525 __u64 fences; 526 __u32 fence_count; 527 __u32 wait_all; 528 __u64 timeout_ns; 529 }; 530 531 struct drm_amdgpu_wait_fences_out { 532 __u32 status; 533 __u32 first_signaled; 534 }; 535 536 union drm_amdgpu_wait_fences { 537 struct drm_amdgpu_wait_fences_in in; 538 struct drm_amdgpu_wait_fences_out out; 539 }; 540 541 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 542 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 543 544 /* Sets or returns a value associated with a buffer. */ 545 struct drm_amdgpu_gem_op { 546 /** GEM object handle */ 547 __u32 handle; 548 /** AMDGPU_GEM_OP_* */ 549 __u32 op; 550 /** Input or return value */ 551 __u64 value; 552 }; 553 554 #define AMDGPU_VA_OP_MAP 1 555 #define AMDGPU_VA_OP_UNMAP 2 556 #define AMDGPU_VA_OP_CLEAR 3 557 #define AMDGPU_VA_OP_REPLACE 4 558 559 /* Delay the page table update till the next CS */ 560 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 561 562 /* Mapping flags */ 563 /* readable mapping */ 564 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 565 /* writable mapping */ 566 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 567 /* executable mapping, new for VI */ 568 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 569 /* partially resident texture */ 570 #define AMDGPU_VM_PAGE_PRT (1 << 4) 571 /* MTYPE flags use bit 5 to 8 */ 572 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 573 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 574 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 575 /* Use Non Coherent MTYPE instead of default MTYPE */ 576 #define AMDGPU_VM_MTYPE_NC (1 << 5) 577 /* Use Write Combine MTYPE instead of default MTYPE */ 578 #define AMDGPU_VM_MTYPE_WC (2 << 5) 579 /* Use Cache Coherent MTYPE instead of default MTYPE */ 580 #define AMDGPU_VM_MTYPE_CC (3 << 5) 581 /* Use UnCached MTYPE instead of default MTYPE */ 582 #define AMDGPU_VM_MTYPE_UC (4 << 5) 583 /* Use Read Write MTYPE instead of default MTYPE */ 584 #define AMDGPU_VM_MTYPE_RW (5 << 5) 585 /* don't allocate MALL */ 586 #define AMDGPU_VM_PAGE_NOALLOC (1 << 9) 587 588 struct drm_amdgpu_gem_va { 589 /** GEM object handle */ 590 __u32 handle; 591 __u32 _pad; 592 /** AMDGPU_VA_OP_* */ 593 __u32 operation; 594 /** AMDGPU_VM_PAGE_* */ 595 __u32 flags; 596 /** va address to assign . Must be correctly aligned.*/ 597 __u64 va_address; 598 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 599 __u64 offset_in_bo; 600 /** Specify mapping size. Must be correctly aligned. */ 601 __u64 map_size; 602 }; 603 604 #define AMDGPU_HW_IP_GFX 0 605 #define AMDGPU_HW_IP_COMPUTE 1 606 #define AMDGPU_HW_IP_DMA 2 607 #define AMDGPU_HW_IP_UVD 3 608 #define AMDGPU_HW_IP_VCE 4 609 #define AMDGPU_HW_IP_UVD_ENC 5 610 #define AMDGPU_HW_IP_VCN_DEC 6 611 /* 612 * From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support 613 * both encoding and decoding jobs. 614 */ 615 #define AMDGPU_HW_IP_VCN_ENC 7 616 #define AMDGPU_HW_IP_VCN_JPEG 8 617 #define AMDGPU_HW_IP_VPE 9 618 #define AMDGPU_HW_IP_NUM 10 619 620 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 621 622 #define AMDGPU_CHUNK_ID_IB 0x01 623 #define AMDGPU_CHUNK_ID_FENCE 0x02 624 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 625 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 626 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 627 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 628 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 629 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 630 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 631 #define AMDGPU_CHUNK_ID_CP_GFX_SHADOW 0x0a 632 633 struct drm_amdgpu_cs_chunk { 634 __u32 chunk_id; 635 __u32 length_dw; 636 __u64 chunk_data; 637 }; 638 639 struct drm_amdgpu_cs_in { 640 /** Rendering context id */ 641 __u32 ctx_id; 642 /** Handle of resource list associated with CS */ 643 __u32 bo_list_handle; 644 __u32 num_chunks; 645 __u32 flags; 646 /** this points to __u64 * which point to cs chunks */ 647 __u64 chunks; 648 }; 649 650 struct drm_amdgpu_cs_out { 651 __u64 handle; 652 }; 653 654 union drm_amdgpu_cs { 655 struct drm_amdgpu_cs_in in; 656 struct drm_amdgpu_cs_out out; 657 }; 658 659 /* Specify flags to be used for IB */ 660 661 /* This IB should be submitted to CE */ 662 #define AMDGPU_IB_FLAG_CE (1<<0) 663 664 /* Preamble flag, which means the IB could be dropped if no context switch */ 665 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 666 667 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 668 #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 669 670 /* The IB fence should do the L2 writeback but not invalidate any shader 671 * caches (L2/vL1/sL1/I$). */ 672 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 673 674 /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. 675 * This will reset wave ID counters for the IB. 676 */ 677 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 678 679 /* Flag the IB as secure (TMZ) 680 */ 681 #define AMDGPU_IB_FLAGS_SECURE (1 << 5) 682 683 /* Tell KMD to flush and invalidate caches 684 */ 685 #define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) 686 687 struct drm_amdgpu_cs_chunk_ib { 688 __u32 _pad; 689 /** AMDGPU_IB_FLAG_* */ 690 __u32 flags; 691 /** Virtual address to begin IB execution */ 692 __u64 va_start; 693 /** Size of submission */ 694 __u32 ib_bytes; 695 /** HW IP to submit to */ 696 __u32 ip_type; 697 /** HW IP index of the same type to submit to */ 698 __u32 ip_instance; 699 /** Ring index to submit to */ 700 __u32 ring; 701 }; 702 703 struct drm_amdgpu_cs_chunk_dep { 704 __u32 ip_type; 705 __u32 ip_instance; 706 __u32 ring; 707 __u32 ctx_id; 708 __u64 handle; 709 }; 710 711 struct drm_amdgpu_cs_chunk_fence { 712 __u32 handle; 713 __u32 offset; 714 }; 715 716 struct drm_amdgpu_cs_chunk_sem { 717 __u32 handle; 718 }; 719 720 struct drm_amdgpu_cs_chunk_syncobj { 721 __u32 handle; 722 __u32 flags; 723 __u64 point; 724 }; 725 726 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 727 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 728 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 729 730 union drm_amdgpu_fence_to_handle { 731 struct { 732 struct drm_amdgpu_fence fence; 733 __u32 what; 734 __u32 pad; 735 } in; 736 struct { 737 __u32 handle; 738 } out; 739 }; 740 741 struct drm_amdgpu_cs_chunk_data { 742 union { 743 struct drm_amdgpu_cs_chunk_ib ib_data; 744 struct drm_amdgpu_cs_chunk_fence fence_data; 745 }; 746 }; 747 748 #define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW 0x1 749 750 struct drm_amdgpu_cs_chunk_cp_gfx_shadow { 751 __u64 shadow_va; 752 __u64 csa_va; 753 __u64 gds_va; 754 __u64 flags; 755 }; 756 757 /* 758 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 759 * 760 */ 761 #define AMDGPU_IDS_FLAGS_FUSION 0x1 762 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 763 #define AMDGPU_IDS_FLAGS_TMZ 0x4 764 #define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8 765 766 /* indicate if acceleration can be working */ 767 #define AMDGPU_INFO_ACCEL_WORKING 0x00 768 /* get the crtc_id from the mode object id? */ 769 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 770 /* query hw IP info */ 771 #define AMDGPU_INFO_HW_IP_INFO 0x02 772 /* query hw IP instance count for the specified type */ 773 #define AMDGPU_INFO_HW_IP_COUNT 0x03 774 /* timestamp for GL_ARB_timer_query */ 775 #define AMDGPU_INFO_TIMESTAMP 0x05 776 /* Query the firmware version */ 777 #define AMDGPU_INFO_FW_VERSION 0x0e 778 /* Subquery id: Query VCE firmware version */ 779 #define AMDGPU_INFO_FW_VCE 0x1 780 /* Subquery id: Query UVD firmware version */ 781 #define AMDGPU_INFO_FW_UVD 0x2 782 /* Subquery id: Query GMC firmware version */ 783 #define AMDGPU_INFO_FW_GMC 0x03 784 /* Subquery id: Query GFX ME firmware version */ 785 #define AMDGPU_INFO_FW_GFX_ME 0x04 786 /* Subquery id: Query GFX PFP firmware version */ 787 #define AMDGPU_INFO_FW_GFX_PFP 0x05 788 /* Subquery id: Query GFX CE firmware version */ 789 #define AMDGPU_INFO_FW_GFX_CE 0x06 790 /* Subquery id: Query GFX RLC firmware version */ 791 #define AMDGPU_INFO_FW_GFX_RLC 0x07 792 /* Subquery id: Query GFX MEC firmware version */ 793 #define AMDGPU_INFO_FW_GFX_MEC 0x08 794 /* Subquery id: Query SMC firmware version */ 795 #define AMDGPU_INFO_FW_SMC 0x0a 796 /* Subquery id: Query SDMA firmware version */ 797 #define AMDGPU_INFO_FW_SDMA 0x0b 798 /* Subquery id: Query PSP SOS firmware version */ 799 #define AMDGPU_INFO_FW_SOS 0x0c 800 /* Subquery id: Query PSP ASD firmware version */ 801 #define AMDGPU_INFO_FW_ASD 0x0d 802 /* Subquery id: Query VCN firmware version */ 803 #define AMDGPU_INFO_FW_VCN 0x0e 804 /* Subquery id: Query GFX RLC SRLC firmware version */ 805 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 806 /* Subquery id: Query GFX RLC SRLG firmware version */ 807 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 808 /* Subquery id: Query GFX RLC SRLS firmware version */ 809 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 810 /* Subquery id: Query DMCU firmware version */ 811 #define AMDGPU_INFO_FW_DMCU 0x12 812 #define AMDGPU_INFO_FW_TA 0x13 813 /* Subquery id: Query DMCUB firmware version */ 814 #define AMDGPU_INFO_FW_DMCUB 0x14 815 /* Subquery id: Query TOC firmware version */ 816 #define AMDGPU_INFO_FW_TOC 0x15 817 /* Subquery id: Query CAP firmware version */ 818 #define AMDGPU_INFO_FW_CAP 0x16 819 /* Subquery id: Query GFX RLCP firmware version */ 820 #define AMDGPU_INFO_FW_GFX_RLCP 0x17 821 /* Subquery id: Query GFX RLCV firmware version */ 822 #define AMDGPU_INFO_FW_GFX_RLCV 0x18 823 /* Subquery id: Query MES_KIQ firmware version */ 824 #define AMDGPU_INFO_FW_MES_KIQ 0x19 825 /* Subquery id: Query MES firmware version */ 826 #define AMDGPU_INFO_FW_MES 0x1a 827 /* Subquery id: Query IMU firmware version */ 828 #define AMDGPU_INFO_FW_IMU 0x1b 829 /* Subquery id: Query VPE firmware version */ 830 #define AMDGPU_INFO_FW_VPE 0x1c 831 832 /* number of bytes moved for TTM migration */ 833 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 834 /* the used VRAM size */ 835 #define AMDGPU_INFO_VRAM_USAGE 0x10 836 /* the used GTT size */ 837 #define AMDGPU_INFO_GTT_USAGE 0x11 838 /* Information about GDS, etc. resource configuration */ 839 #define AMDGPU_INFO_GDS_CONFIG 0x13 840 /* Query information about VRAM and GTT domains */ 841 #define AMDGPU_INFO_VRAM_GTT 0x14 842 /* Query information about register in MMR address space*/ 843 #define AMDGPU_INFO_READ_MMR_REG 0x15 844 /* Query information about device: rev id, family, etc. */ 845 #define AMDGPU_INFO_DEV_INFO 0x16 846 /* visible vram usage */ 847 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 848 /* number of TTM buffer evictions */ 849 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 850 /* Query memory about VRAM and GTT domains */ 851 #define AMDGPU_INFO_MEMORY 0x19 852 /* Query vce clock table */ 853 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 854 /* Query vbios related information */ 855 #define AMDGPU_INFO_VBIOS 0x1B 856 /* Subquery id: Query vbios size */ 857 #define AMDGPU_INFO_VBIOS_SIZE 0x1 858 /* Subquery id: Query vbios image */ 859 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 860 /* Subquery id: Query vbios info */ 861 #define AMDGPU_INFO_VBIOS_INFO 0x3 862 /* Query UVD handles */ 863 #define AMDGPU_INFO_NUM_HANDLES 0x1C 864 /* Query sensor related information */ 865 #define AMDGPU_INFO_SENSOR 0x1D 866 /* Subquery id: Query GPU shader clock */ 867 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 868 /* Subquery id: Query GPU memory clock */ 869 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 870 /* Subquery id: Query GPU temperature */ 871 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 872 /* Subquery id: Query GPU load */ 873 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 874 /* Subquery id: Query average GPU power */ 875 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 876 /* Subquery id: Query northbridge voltage */ 877 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 878 /* Subquery id: Query graphics voltage */ 879 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 880 /* Subquery id: Query GPU stable pstate shader clock */ 881 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 882 /* Subquery id: Query GPU stable pstate memory clock */ 883 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 884 /* Subquery id: Query GPU peak pstate shader clock */ 885 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa 886 /* Subquery id: Query GPU peak pstate memory clock */ 887 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb 888 /* Subquery id: Query input GPU power */ 889 #define AMDGPU_INFO_SENSOR_GPU_INPUT_POWER 0xc 890 /* Number of VRAM page faults on CPU access. */ 891 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 892 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 893 /* query ras mask of enabled features*/ 894 #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 895 /* RAS MASK: UMC (VRAM) */ 896 #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 897 /* RAS MASK: SDMA */ 898 #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 899 /* RAS MASK: GFX */ 900 #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 901 /* RAS MASK: MMHUB */ 902 #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 903 /* RAS MASK: ATHUB */ 904 #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 905 /* RAS MASK: PCIE */ 906 #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 907 /* RAS MASK: HDP */ 908 #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 909 /* RAS MASK: XGMI */ 910 #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 911 /* RAS MASK: DF */ 912 #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 913 /* RAS MASK: SMN */ 914 #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 915 /* RAS MASK: SEM */ 916 #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 917 /* RAS MASK: MP0 */ 918 #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 919 /* RAS MASK: MP1 */ 920 #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 921 /* RAS MASK: FUSE */ 922 #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 923 /* query video encode/decode caps */ 924 #define AMDGPU_INFO_VIDEO_CAPS 0x21 925 /* Subquery id: Decode */ 926 #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 927 /* Subquery id: Encode */ 928 #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 929 /* Query the max number of IBs per gang per submission */ 930 #define AMDGPU_INFO_MAX_IBS 0x22 931 /* query last page fault info */ 932 #define AMDGPU_INFO_GPUVM_FAULT 0x23 933 934 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 935 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 936 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 937 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 938 939 struct drm_amdgpu_query_fw { 940 /** AMDGPU_INFO_FW_* */ 941 __u32 fw_type; 942 /** 943 * Index of the IP if there are more IPs of 944 * the same type. 945 */ 946 __u32 ip_instance; 947 /** 948 * Index of the engine. Whether this is used depends 949 * on the firmware type. (e.g. MEC, SDMA) 950 */ 951 __u32 index; 952 __u32 _pad; 953 }; 954 955 /* Input structure for the INFO ioctl */ 956 struct drm_amdgpu_info { 957 /* Where the return value will be stored */ 958 __u64 return_pointer; 959 /* The size of the return value. Just like "size" in "snprintf", 960 * it limits how many bytes the kernel can write. */ 961 __u32 return_size; 962 /* The query request id. */ 963 __u32 query; 964 965 union { 966 struct { 967 __u32 id; 968 __u32 _pad; 969 } mode_crtc; 970 971 struct { 972 /** AMDGPU_HW_IP_* */ 973 __u32 type; 974 /** 975 * Index of the IP if there are more IPs of the same 976 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 977 */ 978 __u32 ip_instance; 979 } query_hw_ip; 980 981 struct { 982 __u32 dword_offset; 983 /** number of registers to read */ 984 __u32 count; 985 __u32 instance; 986 /** For future use, no flags defined so far */ 987 __u32 flags; 988 } read_mmr_reg; 989 990 struct drm_amdgpu_query_fw query_fw; 991 992 struct { 993 __u32 type; 994 __u32 offset; 995 } vbios_info; 996 997 struct { 998 __u32 type; 999 } sensor_info; 1000 1001 struct { 1002 __u32 type; 1003 } video_cap; 1004 }; 1005 }; 1006 1007 struct drm_amdgpu_info_gds { 1008 /** GDS GFX partition size */ 1009 __u32 gds_gfx_partition_size; 1010 /** GDS compute partition size */ 1011 __u32 compute_partition_size; 1012 /** total GDS memory size */ 1013 __u32 gds_total_size; 1014 /** GWS size per GFX partition */ 1015 __u32 gws_per_gfx_partition; 1016 /** GSW size per compute partition */ 1017 __u32 gws_per_compute_partition; 1018 /** OA size per GFX partition */ 1019 __u32 oa_per_gfx_partition; 1020 /** OA size per compute partition */ 1021 __u32 oa_per_compute_partition; 1022 __u32 _pad; 1023 }; 1024 1025 struct drm_amdgpu_info_vram_gtt { 1026 __u64 vram_size; 1027 __u64 vram_cpu_accessible_size; 1028 __u64 gtt_size; 1029 }; 1030 1031 struct drm_amdgpu_heap_info { 1032 /** max. physical memory */ 1033 __u64 total_heap_size; 1034 1035 /** Theoretical max. available memory in the given heap */ 1036 __u64 usable_heap_size; 1037 1038 /** 1039 * Number of bytes allocated in the heap. This includes all processes 1040 * and private allocations in the kernel. It changes when new buffers 1041 * are allocated, freed, and moved. It cannot be larger than 1042 * heap_size. 1043 */ 1044 __u64 heap_usage; 1045 1046 /** 1047 * Theoretical possible max. size of buffer which 1048 * could be allocated in the given heap 1049 */ 1050 __u64 max_allocation; 1051 }; 1052 1053 struct drm_amdgpu_memory_info { 1054 struct drm_amdgpu_heap_info vram; 1055 struct drm_amdgpu_heap_info cpu_accessible_vram; 1056 struct drm_amdgpu_heap_info gtt; 1057 }; 1058 1059 struct drm_amdgpu_info_firmware { 1060 __u32 ver; 1061 __u32 feature; 1062 }; 1063 1064 struct drm_amdgpu_info_vbios { 1065 __u8 name[64]; 1066 __u8 vbios_pn[64]; 1067 __u32 version; 1068 __u32 pad; 1069 __u8 vbios_ver_str[32]; 1070 __u8 date[32]; 1071 }; 1072 1073 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 1074 #define AMDGPU_VRAM_TYPE_GDDR1 1 1075 #define AMDGPU_VRAM_TYPE_DDR2 2 1076 #define AMDGPU_VRAM_TYPE_GDDR3 3 1077 #define AMDGPU_VRAM_TYPE_GDDR4 4 1078 #define AMDGPU_VRAM_TYPE_GDDR5 5 1079 #define AMDGPU_VRAM_TYPE_HBM 6 1080 #define AMDGPU_VRAM_TYPE_DDR3 7 1081 #define AMDGPU_VRAM_TYPE_DDR4 8 1082 #define AMDGPU_VRAM_TYPE_GDDR6 9 1083 #define AMDGPU_VRAM_TYPE_DDR5 10 1084 #define AMDGPU_VRAM_TYPE_LPDDR4 11 1085 #define AMDGPU_VRAM_TYPE_LPDDR5 12 1086 1087 struct drm_amdgpu_info_device { 1088 /** PCI Device ID */ 1089 __u32 device_id; 1090 /** Internal chip revision: A0, A1, etc.) */ 1091 __u32 chip_rev; 1092 __u32 external_rev; 1093 /** Revision id in PCI Config space */ 1094 __u32 pci_rev; 1095 __u32 family; 1096 __u32 num_shader_engines; 1097 __u32 num_shader_arrays_per_engine; 1098 /* in KHz */ 1099 __u32 gpu_counter_freq; 1100 __u64 max_engine_clock; 1101 __u64 max_memory_clock; 1102 /* cu information */ 1103 __u32 cu_active_number; 1104 /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 1105 __u32 cu_ao_mask; 1106 __u32 cu_bitmap[4][4]; 1107 /** Render backend pipe mask. One render backend is CB+DB. */ 1108 __u32 enabled_rb_pipes_mask; 1109 __u32 num_rb_pipes; 1110 __u32 num_hw_gfx_contexts; 1111 /* PCIe version (the smaller of the GPU and the CPU/motherboard) */ 1112 __u32 pcie_gen; 1113 __u64 ids_flags; 1114 /** Starting virtual address for UMDs. */ 1115 __u64 virtual_address_offset; 1116 /** The maximum virtual address */ 1117 __u64 virtual_address_max; 1118 /** Required alignment of virtual addresses. */ 1119 __u32 virtual_address_alignment; 1120 /** Page table entry - fragment size */ 1121 __u32 pte_fragment_size; 1122 __u32 gart_page_size; 1123 /** constant engine ram size*/ 1124 __u32 ce_ram_size; 1125 /** video memory type info*/ 1126 __u32 vram_type; 1127 /** video memory bit width*/ 1128 __u32 vram_bit_width; 1129 /* vce harvesting instance */ 1130 __u32 vce_harvest_config; 1131 /* gfx double offchip LDS buffers */ 1132 __u32 gc_double_offchip_lds_buf; 1133 /* NGG Primitive Buffer */ 1134 __u64 prim_buf_gpu_addr; 1135 /* NGG Position Buffer */ 1136 __u64 pos_buf_gpu_addr; 1137 /* NGG Control Sideband */ 1138 __u64 cntl_sb_buf_gpu_addr; 1139 /* NGG Parameter Cache */ 1140 __u64 param_buf_gpu_addr; 1141 __u32 prim_buf_size; 1142 __u32 pos_buf_size; 1143 __u32 cntl_sb_buf_size; 1144 __u32 param_buf_size; 1145 /* wavefront size*/ 1146 __u32 wave_front_size; 1147 /* shader visible vgprs*/ 1148 __u32 num_shader_visible_vgprs; 1149 /* CU per shader array*/ 1150 __u32 num_cu_per_sh; 1151 /* number of tcc blocks*/ 1152 __u32 num_tcc_blocks; 1153 /* gs vgt table depth*/ 1154 __u32 gs_vgt_table_depth; 1155 /* gs primitive buffer depth*/ 1156 __u32 gs_prim_buffer_depth; 1157 /* max gs wavefront per vgt*/ 1158 __u32 max_gs_waves_per_vgt; 1159 /* PCIe number of lanes (the smaller of the GPU and the CPU/motherboard) */ 1160 __u32 pcie_num_lanes; 1161 /* always on cu bitmap */ 1162 __u32 cu_ao_bitmap[4][4]; 1163 /** Starting high virtual address for UMDs. */ 1164 __u64 high_va_offset; 1165 /** The maximum high virtual address */ 1166 __u64 high_va_max; 1167 /* gfx10 pa_sc_tile_steering_override */ 1168 __u32 pa_sc_tile_steering_override; 1169 /* disabled TCCs */ 1170 __u64 tcc_disabled_mask; 1171 __u64 min_engine_clock; 1172 __u64 min_memory_clock; 1173 /* The following fields are only set on gfx11+, older chips set 0. */ 1174 __u32 tcp_cache_size; /* AKA GL0, VMEM cache */ 1175 __u32 num_sqc_per_wgp; 1176 __u32 sqc_data_cache_size; /* AKA SMEM cache */ 1177 __u32 sqc_inst_cache_size; 1178 __u32 gl1c_cache_size; 1179 __u32 gl2c_cache_size; 1180 __u64 mall_size; /* AKA infinity cache */ 1181 /* high 32 bits of the rb pipes mask */ 1182 __u32 enabled_rb_pipes_mask_hi; 1183 /* shadow area size for gfx11 */ 1184 __u32 shadow_size; 1185 /* shadow area base virtual alignment for gfx11 */ 1186 __u32 shadow_alignment; 1187 /* context save area size for gfx11 */ 1188 __u32 csa_size; 1189 /* context save area base virtual alignment for gfx11 */ 1190 __u32 csa_alignment; 1191 }; 1192 1193 struct drm_amdgpu_info_hw_ip { 1194 /** Version of h/w IP */ 1195 __u32 hw_ip_version_major; 1196 __u32 hw_ip_version_minor; 1197 /** Capabilities */ 1198 __u64 capabilities_flags; 1199 /** command buffer address start alignment*/ 1200 __u32 ib_start_alignment; 1201 /** command buffer size alignment*/ 1202 __u32 ib_size_alignment; 1203 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 1204 __u32 available_rings; 1205 /** version info: bits 23:16 major, 15:8 minor, 7:0 revision */ 1206 __u32 ip_discovery_version; 1207 }; 1208 1209 struct drm_amdgpu_info_num_handles { 1210 /** Max handles as supported by firmware for UVD */ 1211 __u32 uvd_max_handles; 1212 /** Handles currently in use for UVD */ 1213 __u32 uvd_used_handles; 1214 }; 1215 1216 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 1217 1218 struct drm_amdgpu_info_vce_clock_table_entry { 1219 /** System clock */ 1220 __u32 sclk; 1221 /** Memory clock */ 1222 __u32 mclk; 1223 /** VCE clock */ 1224 __u32 eclk; 1225 __u32 pad; 1226 }; 1227 1228 struct drm_amdgpu_info_vce_clock_table { 1229 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 1230 __u32 num_valid_entries; 1231 __u32 pad; 1232 }; 1233 1234 /* query video encode/decode caps */ 1235 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 1236 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 1237 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 1238 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 1239 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 1240 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 1241 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 1242 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 1243 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 1244 1245 struct drm_amdgpu_info_video_codec_info { 1246 __u32 valid; 1247 __u32 max_width; 1248 __u32 max_height; 1249 __u32 max_pixels_per_frame; 1250 __u32 max_level; 1251 __u32 pad; 1252 }; 1253 1254 struct drm_amdgpu_info_video_caps { 1255 struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; 1256 }; 1257 1258 #define AMDGPU_VMHUB_TYPE_MASK 0xff 1259 #define AMDGPU_VMHUB_TYPE_SHIFT 0 1260 #define AMDGPU_VMHUB_TYPE_GFX 0 1261 #define AMDGPU_VMHUB_TYPE_MM0 1 1262 #define AMDGPU_VMHUB_TYPE_MM1 2 1263 #define AMDGPU_VMHUB_IDX_MASK 0xff00 1264 #define AMDGPU_VMHUB_IDX_SHIFT 8 1265 1266 struct drm_amdgpu_info_gpuvm_fault { 1267 __u64 addr; 1268 __u32 status; 1269 __u32 vmhub; 1270 }; 1271 1272 /* 1273 * Supported GPU families 1274 */ 1275 #define AMDGPU_FAMILY_UNKNOWN 0 1276 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 1277 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 1278 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 1279 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 1280 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 1281 #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 1282 #define AMDGPU_FAMILY_RV 142 /* Raven */ 1283 #define AMDGPU_FAMILY_NV 143 /* Navi10 */ 1284 #define AMDGPU_FAMILY_VGH 144 /* Van Gogh */ 1285 #define AMDGPU_FAMILY_GC_11_0_0 145 /* GC 11.0.0 */ 1286 #define AMDGPU_FAMILY_YC 146 /* Yellow Carp */ 1287 #define AMDGPU_FAMILY_GC_11_0_1 148 /* GC 11.0.1 */ 1288 #define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */ 1289 #define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */ 1290 #define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */ 1291 #define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */ 1292 1293 /* FIXME wrong namespace! */ 1294 struct drm_color_ctm_3x4 { 1295 /* 1296 * Conversion matrix with 3x4 dimensions in S31.32 sign-magnitude 1297 * (not two's complement!) format. 1298 */ 1299 __u64 matrix[12]; 1300 }; 1301 1302 #if defined(__cplusplus) 1303 } 1304 #endif 1305 1306 #endif