v3d_drm.h (23714B) - Raw
1 /* 2 * Copyright © 2014-2018 Broadcom 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #ifndef _V3D_DRM_H_ 25 #define _V3D_DRM_H_ 26 27 #include "drm.h" 28 29 #if defined(__cplusplus) 30 extern "C" { 31 #endif 32 33 #define DRM_V3D_SUBMIT_CL 0x00 34 #define DRM_V3D_WAIT_BO 0x01 35 #define DRM_V3D_CREATE_BO 0x02 36 #define DRM_V3D_MMAP_BO 0x03 37 #define DRM_V3D_GET_PARAM 0x04 38 #define DRM_V3D_GET_BO_OFFSET 0x05 39 #define DRM_V3D_SUBMIT_TFU 0x06 40 #define DRM_V3D_SUBMIT_CSD 0x07 41 #define DRM_V3D_PERFMON_CREATE 0x08 42 #define DRM_V3D_PERFMON_DESTROY 0x09 43 #define DRM_V3D_PERFMON_GET_VALUES 0x0a 44 #define DRM_V3D_SUBMIT_CPU 0x0b 45 #define DRM_V3D_PERFMON_GET_COUNTER 0x0c 46 47 #define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl) 48 #define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo) 49 #define DRM_IOCTL_V3D_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_CREATE_BO, struct drm_v3d_create_bo) 50 #define DRM_IOCTL_V3D_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo) 51 #define DRM_IOCTL_V3D_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param) 52 #define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset) 53 #define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu) 54 #define DRM_IOCTL_V3D_SUBMIT_CSD DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd) 55 #define DRM_IOCTL_V3D_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_CREATE, \ 56 struct drm_v3d_perfmon_create) 57 #define DRM_IOCTL_V3D_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_DESTROY, \ 58 struct drm_v3d_perfmon_destroy) 59 #define DRM_IOCTL_V3D_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_VALUES, \ 60 struct drm_v3d_perfmon_get_values) 61 #define DRM_IOCTL_V3D_SUBMIT_CPU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CPU, struct drm_v3d_submit_cpu) 62 #define DRM_IOCTL_V3D_PERFMON_GET_COUNTER DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_COUNTER, \ 63 struct drm_v3d_perfmon_get_counter) 64 65 #define DRM_V3D_SUBMIT_CL_FLUSH_CACHE 0x01 66 #define DRM_V3D_SUBMIT_EXTENSION 0x02 67 68 /* struct drm_v3d_extension - ioctl extensions 69 * 70 * Linked-list of generic extensions where the id identify which struct is 71 * pointed by ext_data. Therefore, DRM_V3D_EXT_ID_* is used on id to identify 72 * the extension type. 73 */ 74 struct drm_v3d_extension { 75 __u64 next; 76 __u32 id; 77 #define DRM_V3D_EXT_ID_MULTI_SYNC 0x01 78 #define DRM_V3D_EXT_ID_CPU_INDIRECT_CSD 0x02 79 #define DRM_V3D_EXT_ID_CPU_TIMESTAMP_QUERY 0x03 80 #define DRM_V3D_EXT_ID_CPU_RESET_TIMESTAMP_QUERY 0x04 81 #define DRM_V3D_EXT_ID_CPU_COPY_TIMESTAMP_QUERY 0x05 82 #define DRM_V3D_EXT_ID_CPU_RESET_PERFORMANCE_QUERY 0x06 83 #define DRM_V3D_EXT_ID_CPU_COPY_PERFORMANCE_QUERY 0x07 84 __u32 flags; /* mbz */ 85 }; 86 87 /* struct drm_v3d_sem - wait/signal semaphore 88 * 89 * If binary semaphore, it only takes syncobj handle and ignores flags and 90 * point fields. Point is defined for timeline syncobj feature. 91 */ 92 struct drm_v3d_sem { 93 __u32 handle; /* syncobj */ 94 /* rsv below, for future uses */ 95 __u32 flags; 96 __u64 point; /* for timeline sem support */ 97 __u64 mbz[2]; /* must be zero, rsv */ 98 }; 99 100 /* Enum for each of the V3D queues. */ 101 enum v3d_queue { 102 V3D_BIN, 103 V3D_RENDER, 104 V3D_TFU, 105 V3D_CSD, 106 V3D_CACHE_CLEAN, 107 V3D_CPU, 108 }; 109 110 /** 111 * struct drm_v3d_multi_sync - ioctl extension to add support multiples 112 * syncobjs for commands submission. 113 * 114 * When an extension of DRM_V3D_EXT_ID_MULTI_SYNC id is defined, it points to 115 * this extension to define wait and signal dependencies, instead of single 116 * in/out sync entries on submitting commands. The field flags is used to 117 * determine the stage to set wait dependencies. 118 */ 119 struct drm_v3d_multi_sync { 120 struct drm_v3d_extension base; 121 /* Array of wait and signal semaphores */ 122 __u64 in_syncs; 123 __u64 out_syncs; 124 125 /* Number of entries */ 126 __u32 in_sync_count; 127 __u32 out_sync_count; 128 129 /* set the stage (v3d_queue) to sync */ 130 __u32 wait_stage; 131 132 __u32 pad; /* mbz */ 133 }; 134 135 /** 136 * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D 137 * engine. 138 * 139 * This asks the kernel to have the GPU execute an optional binner 140 * command list, and a render command list. 141 * 142 * The L1T, slice, L2C, L2T, and GCA caches will be flushed before 143 * each CL executes. The VCD cache should be flushed (if necessary) 144 * by the submitted CLs. The TLB writes are guaranteed to have been 145 * flushed by the time the render done IRQ happens, which is the 146 * trigger for out_sync. Any dirtying of cachelines by the job (only 147 * possible using TMU writes) must be flushed by the caller using the 148 * DRM_V3D_SUBMIT_CL_FLUSH_CACHE_FLAG flag. 149 */ 150 struct drm_v3d_submit_cl { 151 /* Pointer to the binner command list. 152 * 153 * This is the first set of commands executed, which runs the 154 * coordinate shader to determine where primitives land on the screen, 155 * then writes out the state updates and draw calls necessary per tile 156 * to the tile allocation BO. 157 * 158 * This BCL will block on any previous BCL submitted on the 159 * same FD, but not on any RCL or BCLs submitted by other 160 * clients -- that is left up to the submitter to control 161 * using in_sync_bcl if necessary. 162 */ 163 __u32 bcl_start; 164 165 /** End address of the BCL (first byte after the BCL) */ 166 __u32 bcl_end; 167 168 /* Offset of the render command list. 169 * 170 * This is the second set of commands executed, which will either 171 * execute the tiles that have been set up by the BCL, or a fixed set 172 * of tiles (in the case of RCL-only blits). 173 * 174 * This RCL will block on this submit's BCL, and any previous 175 * RCL submitted on the same FD, but not on any RCL or BCLs 176 * submitted by other clients -- that is left up to the 177 * submitter to control using in_sync_rcl if necessary. 178 */ 179 __u32 rcl_start; 180 181 /** End address of the RCL (first byte after the RCL) */ 182 __u32 rcl_end; 183 184 /** An optional sync object to wait on before starting the BCL. */ 185 __u32 in_sync_bcl; 186 /** An optional sync object to wait on before starting the RCL. */ 187 __u32 in_sync_rcl; 188 /** An optional sync object to place the completion fence in. */ 189 __u32 out_sync; 190 191 /* Offset of the tile alloc memory 192 * 193 * This is optional on V3D 3.3 (where the CL can set the value) but 194 * required on V3D 4.1. 195 */ 196 __u32 qma; 197 198 /** Size of the tile alloc memory. */ 199 __u32 qms; 200 201 /** Offset of the tile state data array. */ 202 __u32 qts; 203 204 /* Pointer to a u32 array of the BOs that are referenced by the job. 205 */ 206 __u64 bo_handles; 207 208 /* Number of BO handles passed in (size is that times 4). */ 209 __u32 bo_handle_count; 210 211 /* DRM_V3D_SUBMIT_* properties */ 212 __u32 flags; 213 214 /* ID of the perfmon to attach to this job. 0 means no perfmon. */ 215 __u32 perfmon_id; 216 217 __u32 pad; 218 219 /* Pointer to an array of ioctl extensions*/ 220 __u64 extensions; 221 }; 222 223 /** 224 * struct drm_v3d_wait_bo - ioctl argument for waiting for 225 * completion of the last DRM_V3D_SUBMIT_CL on a BO. 226 * 227 * This is useful for cases where multiple processes might be 228 * rendering to a BO and you want to wait for all rendering to be 229 * completed. 230 */ 231 struct drm_v3d_wait_bo { 232 __u32 handle; 233 __u32 pad; 234 __u64 timeout_ns; 235 }; 236 237 /** 238 * struct drm_v3d_create_bo - ioctl argument for creating V3D BOs. 239 * 240 * There are currently no values for the flags argument, but it may be 241 * used in a future extension. 242 */ 243 struct drm_v3d_create_bo { 244 __u32 size; 245 __u32 flags; 246 /** Returned GEM handle for the BO. */ 247 __u32 handle; 248 /** 249 * Returned offset for the BO in the V3D address space. This offset 250 * is private to the DRM fd and is valid for the lifetime of the GEM 251 * handle. 252 * 253 * This offset value will always be nonzero, since various HW 254 * units treat 0 specially. 255 */ 256 __u32 offset; 257 }; 258 259 /** 260 * struct drm_v3d_mmap_bo - ioctl argument for mapping V3D BOs. 261 * 262 * This doesn't actually perform an mmap. Instead, it returns the 263 * offset you need to use in an mmap on the DRM device node. This 264 * means that tools like valgrind end up knowing about the mapped 265 * memory. 266 * 267 * There are currently no values for the flags argument, but it may be 268 * used in a future extension. 269 */ 270 struct drm_v3d_mmap_bo { 271 /** Handle for the object being mapped. */ 272 __u32 handle; 273 __u32 flags; 274 /** offset into the drm node to use for subsequent mmap call. */ 275 __u64 offset; 276 }; 277 278 enum drm_v3d_param { 279 DRM_V3D_PARAM_V3D_UIFCFG, 280 DRM_V3D_PARAM_V3D_HUB_IDENT1, 281 DRM_V3D_PARAM_V3D_HUB_IDENT2, 282 DRM_V3D_PARAM_V3D_HUB_IDENT3, 283 DRM_V3D_PARAM_V3D_CORE0_IDENT0, 284 DRM_V3D_PARAM_V3D_CORE0_IDENT1, 285 DRM_V3D_PARAM_V3D_CORE0_IDENT2, 286 DRM_V3D_PARAM_SUPPORTS_TFU, 287 DRM_V3D_PARAM_SUPPORTS_CSD, 288 DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH, 289 DRM_V3D_PARAM_SUPPORTS_PERFMON, 290 DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT, 291 DRM_V3D_PARAM_SUPPORTS_CPU_QUEUE, 292 DRM_V3D_PARAM_MAX_PERF_COUNTERS, 293 DRM_V3D_PARAM_SUPPORTS_SUPER_PAGES, 294 }; 295 296 struct drm_v3d_get_param { 297 __u32 param; 298 __u32 pad; 299 __u64 value; 300 }; 301 302 /** 303 * Returns the offset for the BO in the V3D address space for this DRM fd. 304 * This is the same value returned by drm_v3d_create_bo, if that was called 305 * from this DRM fd. 306 */ 307 struct drm_v3d_get_bo_offset { 308 __u32 handle; 309 __u32 offset; 310 }; 311 312 struct drm_v3d_submit_tfu { 313 __u32 icfg; 314 __u32 iia; 315 __u32 iis; 316 __u32 ica; 317 __u32 iua; 318 __u32 ioa; 319 __u32 ios; 320 __u32 coef[4]; 321 /* First handle is the output BO, following are other inputs. 322 * 0 for unused. 323 */ 324 __u32 bo_handles[4]; 325 /* sync object to block on before running the TFU job. Each TFU 326 * job will execute in the order submitted to its FD. Synchronization 327 * against rendering jobs requires using sync objects. 328 */ 329 __u32 in_sync; 330 /* Sync object to signal when the TFU job is done. */ 331 __u32 out_sync; 332 333 __u32 flags; 334 335 /* Pointer to an array of ioctl extensions*/ 336 __u64 extensions; 337 338 struct { 339 __u32 ioc; 340 __u32 pad; 341 } v71; 342 }; 343 344 /* Submits a compute shader for dispatch. This job will block on any 345 * previous compute shaders submitted on this fd, and any other 346 * synchronization must be performed with in_sync/out_sync. 347 */ 348 struct drm_v3d_submit_csd { 349 __u32 cfg[7]; 350 __u32 coef[4]; 351 352 /* Pointer to a u32 array of the BOs that are referenced by the job. 353 */ 354 __u64 bo_handles; 355 356 /* Number of BO handles passed in (size is that times 4). */ 357 __u32 bo_handle_count; 358 359 /* sync object to block on before running the CSD job. Each 360 * CSD job will execute in the order submitted to its FD. 361 * Synchronization against rendering/TFU jobs or CSD from 362 * other fds requires using sync objects. 363 */ 364 __u32 in_sync; 365 /* Sync object to signal when the CSD job is done. */ 366 __u32 out_sync; 367 368 /* ID of the perfmon to attach to this job. 0 means no perfmon. */ 369 __u32 perfmon_id; 370 371 /* Pointer to an array of ioctl extensions*/ 372 __u64 extensions; 373 374 __u32 flags; 375 376 __u32 pad; 377 }; 378 379 /** 380 * struct drm_v3d_indirect_csd - ioctl extension for the CPU job to create an 381 * indirect CSD 382 * 383 * When an extension of DRM_V3D_EXT_ID_CPU_INDIRECT_CSD id is defined, it 384 * points to this extension to define a indirect CSD submission. It creates a 385 * CPU job linked to a CSD job. The CPU job waits for the indirect CSD 386 * dependencies and, once they are signaled, it updates the CSD job config 387 * before allowing the CSD job execution. 388 */ 389 struct drm_v3d_indirect_csd { 390 struct drm_v3d_extension base; 391 392 /* Indirect CSD */ 393 struct drm_v3d_submit_csd submit; 394 395 /* Handle of the indirect BO, that should be also attached to the 396 * indirect CSD. 397 */ 398 __u32 indirect; 399 400 /* Offset within the BO where the workgroup counts are stored */ 401 __u32 offset; 402 403 /* Workgroups size */ 404 __u32 wg_size; 405 406 /* Indices of the uniforms with the workgroup dispatch counts 407 * in the uniform stream. If the uniform rewrite is not needed, 408 * the offset must be 0xffffffff. 409 */ 410 __u32 wg_uniform_offsets[3]; 411 }; 412 413 /** 414 * struct drm_v3d_timestamp_query - ioctl extension for the CPU job to calculate 415 * a timestamp query 416 * 417 * When an extension DRM_V3D_EXT_ID_TIMESTAMP_QUERY is defined, it points to 418 * this extension to define a timestamp query submission. This CPU job will 419 * calculate the timestamp query and update the query value within the 420 * timestamp BO. Moreover, it will signal the timestamp syncobj to indicate 421 * query availability. 422 */ 423 struct drm_v3d_timestamp_query { 424 struct drm_v3d_extension base; 425 426 /* Array of queries' offsets within the timestamp BO for their value */ 427 __u64 offsets; 428 429 /* Array of timestamp's syncobjs to indicate its availability */ 430 __u64 syncs; 431 432 /* Number of queries */ 433 __u32 count; 434 435 /* mbz */ 436 __u32 pad; 437 }; 438 439 /** 440 * struct drm_v3d_reset_timestamp_query - ioctl extension for the CPU job to 441 * reset timestamp queries 442 * 443 * When an extension DRM_V3D_EXT_ID_CPU_RESET_TIMESTAMP_QUERY is defined, it 444 * points to this extension to define a reset timestamp submission. This CPU 445 * job will reset the timestamp queries based on value offset of the first 446 * query. Moreover, it will reset the timestamp syncobj to reset query 447 * availability. 448 */ 449 struct drm_v3d_reset_timestamp_query { 450 struct drm_v3d_extension base; 451 452 /* Array of timestamp's syncobjs to indicate its availability */ 453 __u64 syncs; 454 455 /* Offset of the first query within the timestamp BO for its value */ 456 __u32 offset; 457 458 /* Number of queries */ 459 __u32 count; 460 }; 461 462 /** 463 * struct drm_v3d_copy_timestamp_query - ioctl extension for the CPU job to copy 464 * query results to a buffer 465 * 466 * When an extension DRM_V3D_EXT_ID_CPU_COPY_TIMESTAMP_QUERY is defined, it 467 * points to this extension to define a copy timestamp query submission. This 468 * CPU job will copy the timestamp queries results to a BO with the offset 469 * and stride defined in the extension. 470 */ 471 struct drm_v3d_copy_timestamp_query { 472 struct drm_v3d_extension base; 473 474 /* Define if should write to buffer using 64 or 32 bits */ 475 __u8 do_64bit; 476 477 /* Define if it can write to buffer even if the query is not available */ 478 __u8 do_partial; 479 480 /* Define if it should write availability bit to buffer */ 481 __u8 availability_bit; 482 483 /* mbz */ 484 __u8 pad; 485 486 /* Offset of the buffer in the BO */ 487 __u32 offset; 488 489 /* Stride of the buffer in the BO */ 490 __u32 stride; 491 492 /* Number of queries */ 493 __u32 count; 494 495 /* Array of queries' offsets within the timestamp BO for their value */ 496 __u64 offsets; 497 498 /* Array of timestamp's syncobjs to indicate its availability */ 499 __u64 syncs; 500 }; 501 502 /** 503 * struct drm_v3d_reset_performance_query - ioctl extension for the CPU job to 504 * reset performance queries 505 * 506 * When an extension DRM_V3D_EXT_ID_CPU_RESET_PERFORMANCE_QUERY is defined, it 507 * points to this extension to define a reset performance submission. This CPU 508 * job will reset the performance queries by resetting the values of the 509 * performance monitors. Moreover, it will reset the syncobj to reset query 510 * availability. 511 */ 512 struct drm_v3d_reset_performance_query { 513 struct drm_v3d_extension base; 514 515 /* Array of performance queries's syncobjs to indicate its availability */ 516 __u64 syncs; 517 518 /* Number of queries */ 519 __u32 count; 520 521 /* Number of performance monitors */ 522 __u32 nperfmons; 523 524 /* Array of u64 user-pointers that point to an array of kperfmon_ids */ 525 __u64 kperfmon_ids; 526 }; 527 528 /** 529 * struct drm_v3d_copy_performance_query - ioctl extension for the CPU job to copy 530 * performance query results to a buffer 531 * 532 * When an extension DRM_V3D_EXT_ID_CPU_COPY_PERFORMANCE_QUERY is defined, it 533 * points to this extension to define a copy performance query submission. This 534 * CPU job will copy the performance queries results to a BO with the offset 535 * and stride defined in the extension. 536 */ 537 struct drm_v3d_copy_performance_query { 538 struct drm_v3d_extension base; 539 540 /* Define if should write to buffer using 64 or 32 bits */ 541 __u8 do_64bit; 542 543 /* Define if it can write to buffer even if the query is not available */ 544 __u8 do_partial; 545 546 /* Define if it should write availability bit to buffer */ 547 __u8 availability_bit; 548 549 /* mbz */ 550 __u8 pad; 551 552 /* Offset of the buffer in the BO */ 553 __u32 offset; 554 555 /* Stride of the buffer in the BO */ 556 __u32 stride; 557 558 /* Number of performance monitors */ 559 __u32 nperfmons; 560 561 /* Number of performance counters related to this query pool */ 562 __u32 ncounters; 563 564 /* Number of queries */ 565 __u32 count; 566 567 /* Array of performance queries's syncobjs to indicate its availability */ 568 __u64 syncs; 569 570 /* Array of u64 user-pointers that point to an array of kperfmon_ids */ 571 __u64 kperfmon_ids; 572 }; 573 574 struct drm_v3d_submit_cpu { 575 /* Pointer to a u32 array of the BOs that are referenced by the job. 576 * 577 * For DRM_V3D_EXT_ID_CPU_INDIRECT_CSD, it must contain only one BO, 578 * that contains the workgroup counts. 579 * 580 * For DRM_V3D_EXT_ID_TIMESTAMP_QUERY, it must contain only one BO, 581 * that will contain the timestamp. 582 * 583 * For DRM_V3D_EXT_ID_CPU_RESET_TIMESTAMP_QUERY, it must contain only 584 * one BO, that contains the timestamp. 585 * 586 * For DRM_V3D_EXT_ID_CPU_COPY_TIMESTAMP_QUERY, it must contain two 587 * BOs. The first is the BO where the timestamp queries will be written 588 * to. The second is the BO that contains the timestamp. 589 * 590 * For DRM_V3D_EXT_ID_CPU_RESET_PERFORMANCE_QUERY, it must contain no 591 * BOs. 592 * 593 * For DRM_V3D_EXT_ID_CPU_COPY_PERFORMANCE_QUERY, it must contain one 594 * BO, where the performance queries will be written. 595 */ 596 __u64 bo_handles; 597 598 /* Number of BO handles passed in (size is that times 4). */ 599 __u32 bo_handle_count; 600 601 __u32 flags; 602 603 /* Pointer to an array of ioctl extensions*/ 604 __u64 extensions; 605 }; 606 607 /* The performance counters index represented by this enum are deprecated and 608 * must no longer be used. These counters are only valid for V3D 4.2. 609 * 610 * In order to check for performance counter information, 611 * use DRM_IOCTL_V3D_PERFMON_GET_COUNTER. 612 * 613 * Don't use V3D_PERFCNT_NUM to retrieve the maximum number of performance 614 * counters. You should use DRM_IOCTL_V3D_GET_PARAM with the following 615 * parameter: DRM_V3D_PARAM_MAX_PERF_COUNTERS. 616 */ 617 enum { 618 V3D_PERFCNT_FEP_VALID_PRIMTS_NO_PIXELS, 619 V3D_PERFCNT_FEP_VALID_PRIMS, 620 V3D_PERFCNT_FEP_EZ_NFCLIP_QUADS, 621 V3D_PERFCNT_FEP_VALID_QUADS, 622 V3D_PERFCNT_TLB_QUADS_STENCIL_FAIL, 623 V3D_PERFCNT_TLB_QUADS_STENCILZ_FAIL, 624 V3D_PERFCNT_TLB_QUADS_STENCILZ_PASS, 625 V3D_PERFCNT_TLB_QUADS_ZERO_COV, 626 V3D_PERFCNT_TLB_QUADS_NONZERO_COV, 627 V3D_PERFCNT_TLB_QUADS_WRITTEN, 628 V3D_PERFCNT_PTB_PRIM_VIEWPOINT_DISCARD, 629 V3D_PERFCNT_PTB_PRIM_CLIP, 630 V3D_PERFCNT_PTB_PRIM_REV, 631 V3D_PERFCNT_QPU_IDLE_CYCLES, 632 V3D_PERFCNT_QPU_ACTIVE_CYCLES_VERTEX_COORD_USER, 633 V3D_PERFCNT_QPU_ACTIVE_CYCLES_FRAG, 634 V3D_PERFCNT_QPU_CYCLES_VALID_INSTR, 635 V3D_PERFCNT_QPU_CYCLES_TMU_STALL, 636 V3D_PERFCNT_QPU_CYCLES_SCOREBOARD_STALL, 637 V3D_PERFCNT_QPU_CYCLES_VARYINGS_STALL, 638 V3D_PERFCNT_QPU_IC_HIT, 639 V3D_PERFCNT_QPU_IC_MISS, 640 V3D_PERFCNT_QPU_UC_HIT, 641 V3D_PERFCNT_QPU_UC_MISS, 642 V3D_PERFCNT_TMU_TCACHE_ACCESS, 643 V3D_PERFCNT_TMU_TCACHE_MISS, 644 V3D_PERFCNT_VPM_VDW_STALL, 645 V3D_PERFCNT_VPM_VCD_STALL, 646 V3D_PERFCNT_BIN_ACTIVE, 647 V3D_PERFCNT_RDR_ACTIVE, 648 V3D_PERFCNT_L2T_HITS, 649 V3D_PERFCNT_L2T_MISSES, 650 V3D_PERFCNT_CYCLE_COUNT, 651 V3D_PERFCNT_QPU_CYCLES_STALLED_VERTEX_COORD_USER, 652 V3D_PERFCNT_QPU_CYCLES_STALLED_FRAGMENT, 653 V3D_PERFCNT_PTB_PRIMS_BINNED, 654 V3D_PERFCNT_AXI_WRITES_WATCH_0, 655 V3D_PERFCNT_AXI_READS_WATCH_0, 656 V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_0, 657 V3D_PERFCNT_AXI_READ_STALLS_WATCH_0, 658 V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_0, 659 V3D_PERFCNT_AXI_READ_BYTES_WATCH_0, 660 V3D_PERFCNT_AXI_WRITES_WATCH_1, 661 V3D_PERFCNT_AXI_READS_WATCH_1, 662 V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_1, 663 V3D_PERFCNT_AXI_READ_STALLS_WATCH_1, 664 V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_1, 665 V3D_PERFCNT_AXI_READ_BYTES_WATCH_1, 666 V3D_PERFCNT_TLB_PARTIAL_QUADS, 667 V3D_PERFCNT_TMU_CONFIG_ACCESSES, 668 V3D_PERFCNT_L2T_NO_ID_STALL, 669 V3D_PERFCNT_L2T_COM_QUE_STALL, 670 V3D_PERFCNT_L2T_TMU_WRITES, 671 V3D_PERFCNT_TMU_ACTIVE_CYCLES, 672 V3D_PERFCNT_TMU_STALLED_CYCLES, 673 V3D_PERFCNT_CLE_ACTIVE, 674 V3D_PERFCNT_L2T_TMU_READS, 675 V3D_PERFCNT_L2T_CLE_READS, 676 V3D_PERFCNT_L2T_VCD_READS, 677 V3D_PERFCNT_L2T_TMUCFG_READS, 678 V3D_PERFCNT_L2T_SLC0_READS, 679 V3D_PERFCNT_L2T_SLC1_READS, 680 V3D_PERFCNT_L2T_SLC2_READS, 681 V3D_PERFCNT_L2T_TMU_W_MISSES, 682 V3D_PERFCNT_L2T_TMU_R_MISSES, 683 V3D_PERFCNT_L2T_CLE_MISSES, 684 V3D_PERFCNT_L2T_VCD_MISSES, 685 V3D_PERFCNT_L2T_TMUCFG_MISSES, 686 V3D_PERFCNT_L2T_SLC0_MISSES, 687 V3D_PERFCNT_L2T_SLC1_MISSES, 688 V3D_PERFCNT_L2T_SLC2_MISSES, 689 V3D_PERFCNT_CORE_MEM_WRITES, 690 V3D_PERFCNT_L2T_MEM_WRITES, 691 V3D_PERFCNT_PTB_MEM_WRITES, 692 V3D_PERFCNT_TLB_MEM_WRITES, 693 V3D_PERFCNT_CORE_MEM_READS, 694 V3D_PERFCNT_L2T_MEM_READS, 695 V3D_PERFCNT_PTB_MEM_READS, 696 V3D_PERFCNT_PSE_MEM_READS, 697 V3D_PERFCNT_TLB_MEM_READS, 698 V3D_PERFCNT_GMP_MEM_READS, 699 V3D_PERFCNT_PTB_W_MEM_WORDS, 700 V3D_PERFCNT_TLB_W_MEM_WORDS, 701 V3D_PERFCNT_PSE_R_MEM_WORDS, 702 V3D_PERFCNT_TLB_R_MEM_WORDS, 703 V3D_PERFCNT_TMU_MRU_HITS, 704 V3D_PERFCNT_COMPUTE_ACTIVE, 705 V3D_PERFCNT_NUM, 706 }; 707 708 #define DRM_V3D_MAX_PERF_COUNTERS 32 709 710 struct drm_v3d_perfmon_create { 711 __u32 id; 712 __u32 ncounters; 713 __u8 counters[DRM_V3D_MAX_PERF_COUNTERS]; 714 }; 715 716 struct drm_v3d_perfmon_destroy { 717 __u32 id; 718 }; 719 720 /* 721 * Returns the values of the performance counters tracked by this 722 * perfmon (as an array of ncounters u64 values). 723 * 724 * No implicit synchronization is performed, so the user has to 725 * guarantee that any jobs using this perfmon have already been 726 * completed (probably by blocking on the seqno returned by the 727 * last exec that used the perfmon). 728 */ 729 struct drm_v3d_perfmon_get_values { 730 __u32 id; 731 __u32 pad; 732 __u64 values_ptr; 733 }; 734 735 #define DRM_V3D_PERFCNT_MAX_NAME 64 736 #define DRM_V3D_PERFCNT_MAX_CATEGORY 32 737 #define DRM_V3D_PERFCNT_MAX_DESCRIPTION 256 738 739 /** 740 * struct drm_v3d_perfmon_get_counter - ioctl to get the description of a 741 * performance counter 742 * 743 * As userspace needs to retrieve information about the performance counters 744 * available, this IOCTL allows users to get information about a performance 745 * counter (name, category and description). 746 */ 747 struct drm_v3d_perfmon_get_counter { 748 /* 749 * Counter ID 750 * 751 * Must be smaller than the maximum number of performance counters, which 752 * can be retrieve through DRM_V3D_PARAM_MAX_PERF_COUNTERS. 753 */ 754 __u8 counter; 755 756 /* Name of the counter */ 757 __u8 name[DRM_V3D_PERFCNT_MAX_NAME]; 758 759 /* Category of the counter */ 760 __u8 category[DRM_V3D_PERFCNT_MAX_CATEGORY]; 761 762 /* Description of the counter */ 763 __u8 description[DRM_V3D_PERFCNT_MAX_DESCRIPTION]; 764 765 /* mbz */ 766 __u8 reserved[7]; 767 }; 768 769 #if defined(__cplusplus) 770 } 771 #endif 772 773 #endif /* _V3D_DRM_H_ */