xe_drm.h (58816B) - Raw
1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef _XE_DRM_H_ 7 #define _XE_DRM_H_ 8 9 #include "drm.h" 10 11 #if defined(__cplusplus) 12 extern "C" { 13 #endif 14 15 /* 16 * Please note that modifications to all structs defined here are 17 * subject to backwards-compatibility constraints. 18 * Sections in this file are organized as follows: 19 * 1. IOCTL definition 20 * 2. Extension definition and helper structs 21 * 3. IOCTL's Query structs in the order of the Query's entries. 22 * 4. The rest of IOCTL structs in the order of IOCTL declaration. 23 */ 24 25 /** 26 * DOC: Xe Device Block Diagram 27 * 28 * The diagram below represents a high-level simplification of a discrete 29 * GPU supported by the Xe driver. It shows some device components which 30 * are necessary to understand this API, as well as how their relations 31 * to each other. This diagram does not represent real hardware:: 32 * 33 * ┌──────────────────────────────────────────────────────────────────┐ 34 * │ ┌──────────────────────────────────────────────────┐ ┌─────────┐ │ 35 * │ │ ┌───────────────────────┐ ┌─────┐ │ │ ┌─────┐ │ │ 36 * │ │ │ VRAM0 ├───┤ ... │ │ │ │VRAM1│ │ │ 37 * │ │ └───────────┬───────────┘ └─GT1─┘ │ │ └──┬──┘ │ │ 38 * │ │ ┌──────────────────┴───────────────────────────┐ │ │ ┌──┴──┐ │ │ 39 * │ │ │ ┌─────────────────────┐ ┌─────────────────┐ │ │ │ │ │ │ │ 40 * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ 41 * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │RCS0 │ │BCS0 │ │ │ │ │ │ │ │ │ 42 * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ 43 * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ 44 * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VCS0 │ │VCS1 │ │ │ │ │ │ │ │ │ 45 * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ 46 * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ 47 * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VECS0│ │VECS1│ │ │ │ │ │ ... │ │ │ 48 * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ 49 * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ 50 * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │CCS0 │ │CCS1 │ │ │ │ │ │ │ │ │ 51 * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ 52 * │ │ │ └─────────DSS─────────┘ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ 53 * │ │ │ │ │CCS2 │ │CCS3 │ │ │ │ │ │ │ │ │ 54 * │ │ │ ┌─────┐ ┌─────┐ ┌─────┐ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ 55 * │ │ │ │ ... │ │ ... │ │ ... │ │ │ │ │ │ │ │ │ │ 56 * │ │ │ └─DSS─┘ └─DSS─┘ └─DSS─┘ └─────Engines─────┘ │ │ │ │ │ │ │ 57 * │ │ └───────────────────────────GT0────────────────┘ │ │ └─GT2─┘ │ │ 58 * │ └────────────────────────────Tile0─────────────────┘ └─ Tile1──┘ │ 59 * └─────────────────────────────Device0───────┬──────────────────────┘ 60 * │ 61 * ───────────────────────┴────────── PCI bus 62 */ 63 64 /** 65 * DOC: Xe uAPI Overview 66 * 67 * This section aims to describe the Xe's IOCTL entries, its structs, and other 68 * Xe related uAPI such as uevents and PMU (Platform Monitoring Unit) related 69 * entries and usage. 70 * 71 * List of supported IOCTLs: 72 * - &DRM_IOCTL_XE_DEVICE_QUERY 73 * - &DRM_IOCTL_XE_GEM_CREATE 74 * - &DRM_IOCTL_XE_GEM_MMAP_OFFSET 75 * - &DRM_IOCTL_XE_VM_CREATE 76 * - &DRM_IOCTL_XE_VM_DESTROY 77 * - &DRM_IOCTL_XE_VM_BIND 78 * - &DRM_IOCTL_XE_EXEC_QUEUE_CREATE 79 * - &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY 80 * - &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY 81 * - &DRM_IOCTL_XE_EXEC 82 * - &DRM_IOCTL_XE_WAIT_USER_FENCE 83 * - &DRM_IOCTL_XE_OBSERVATION 84 */ 85 86 /* 87 * xe specific ioctls. 88 * 89 * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie 90 * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset 91 * against DRM_COMMAND_BASE and should be between [0x0, 0x60). 92 */ 93 #define DRM_XE_DEVICE_QUERY 0x00 94 #define DRM_XE_GEM_CREATE 0x01 95 #define DRM_XE_GEM_MMAP_OFFSET 0x02 96 #define DRM_XE_VM_CREATE 0x03 97 #define DRM_XE_VM_DESTROY 0x04 98 #define DRM_XE_VM_BIND 0x05 99 #define DRM_XE_EXEC_QUEUE_CREATE 0x06 100 #define DRM_XE_EXEC_QUEUE_DESTROY 0x07 101 #define DRM_XE_EXEC_QUEUE_GET_PROPERTY 0x08 102 #define DRM_XE_EXEC 0x09 103 #define DRM_XE_WAIT_USER_FENCE 0x0a 104 #define DRM_XE_OBSERVATION 0x0b 105 106 /* Must be kept compact -- no holes */ 107 108 #define DRM_IOCTL_XE_DEVICE_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, struct drm_xe_device_query) 109 #define DRM_IOCTL_XE_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_CREATE, struct drm_xe_gem_create) 110 #define DRM_IOCTL_XE_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_MMAP_OFFSET, struct drm_xe_gem_mmap_offset) 111 #define DRM_IOCTL_XE_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create) 112 #define DRM_IOCTL_XE_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy) 113 #define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind) 114 #define DRM_IOCTL_XE_EXEC_QUEUE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_CREATE, struct drm_xe_exec_queue_create) 115 #define DRM_IOCTL_XE_EXEC_QUEUE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_DESTROY, struct drm_xe_exec_queue_destroy) 116 #define DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_GET_PROPERTY, struct drm_xe_exec_queue_get_property) 117 #define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec) 118 #define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence) 119 #define DRM_IOCTL_XE_OBSERVATION DRM_IOW(DRM_COMMAND_BASE + DRM_XE_OBSERVATION, struct drm_xe_observation_param) 120 121 /** 122 * DOC: Xe IOCTL Extensions 123 * 124 * Before detailing the IOCTLs and its structs, it is important to highlight 125 * that every IOCTL in Xe is extensible. 126 * 127 * Many interfaces need to grow over time. In most cases we can simply 128 * extend the struct and have userspace pass in more data. Another option, 129 * as demonstrated by Vulkan's approach to providing extensions for forward 130 * and backward compatibility, is to use a list of optional structs to 131 * provide those extra details. 132 * 133 * The key advantage to using an extension chain is that it allows us to 134 * redefine the interface more easily than an ever growing struct of 135 * increasing complexity, and for large parts of that interface to be 136 * entirely optional. The downside is more pointer chasing; chasing across 137 * the boundary with pointers encapsulated inside u64. 138 * 139 * Example chaining: 140 * 141 * .. code-block:: C 142 * 143 * struct drm_xe_user_extension ext3 { 144 * .next_extension = 0, // end 145 * .name = ..., 146 * }; 147 * struct drm_xe_user_extension ext2 { 148 * .next_extension = (uintptr_t)&ext3, 149 * .name = ..., 150 * }; 151 * struct drm_xe_user_extension ext1 { 152 * .next_extension = (uintptr_t)&ext2, 153 * .name = ..., 154 * }; 155 * 156 * Typically the struct drm_xe_user_extension would be embedded in some uAPI 157 * struct, and in this case we would feed it the head of the chain(i.e ext1), 158 * which would then apply all of the above extensions. 159 */ 160 161 /** 162 * struct drm_xe_user_extension - Base class for defining a chain of extensions 163 */ 164 struct drm_xe_user_extension { 165 /** 166 * @next_extension: 167 * 168 * Pointer to the next struct drm_xe_user_extension, or zero if the end. 169 */ 170 __u64 next_extension; 171 172 /** 173 * @name: Name of the extension. 174 * 175 * Note that the name here is just some integer. 176 * 177 * Also note that the name space for this is not global for the whole 178 * driver, but rather its scope/meaning is limited to the specific piece 179 * of uAPI which has embedded the struct drm_xe_user_extension. 180 */ 181 __u32 name; 182 183 /** 184 * @pad: MBZ 185 * 186 * All undefined bits must be zero. 187 */ 188 __u32 pad; 189 }; 190 191 /** 192 * struct drm_xe_ext_set_property - Generic set property extension 193 * 194 * A generic struct that allows any of the Xe's IOCTL to be extended 195 * with a set_property operation. 196 */ 197 struct drm_xe_ext_set_property { 198 /** @base: base user extension */ 199 struct drm_xe_user_extension base; 200 201 /** @property: property to set */ 202 __u32 property; 203 204 /** @pad: MBZ */ 205 __u32 pad; 206 207 /** @value: property value */ 208 __u64 value; 209 210 /** @reserved: Reserved */ 211 __u64 reserved[2]; 212 }; 213 214 /** 215 * struct drm_xe_engine_class_instance - instance of an engine class 216 * 217 * It is returned as part of the @drm_xe_engine, but it also is used as 218 * the input of engine selection for both @drm_xe_exec_queue_create and 219 * @drm_xe_query_engine_cycles 220 * 221 * The @engine_class can be: 222 * - %DRM_XE_ENGINE_CLASS_RENDER 223 * - %DRM_XE_ENGINE_CLASS_COPY 224 * - %DRM_XE_ENGINE_CLASS_VIDEO_DECODE 225 * - %DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 226 * - %DRM_XE_ENGINE_CLASS_COMPUTE 227 * - %DRM_XE_ENGINE_CLASS_VM_BIND - Kernel only classes (not actual 228 * hardware engine class). Used for creating ordered queues of VM 229 * bind operations. 230 */ 231 struct drm_xe_engine_class_instance { 232 #define DRM_XE_ENGINE_CLASS_RENDER 0 233 #define DRM_XE_ENGINE_CLASS_COPY 1 234 #define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2 235 #define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3 236 #define DRM_XE_ENGINE_CLASS_COMPUTE 4 237 #define DRM_XE_ENGINE_CLASS_VM_BIND 5 238 /** @engine_class: engine class id */ 239 __u16 engine_class; 240 /** @engine_instance: engine instance id */ 241 __u16 engine_instance; 242 /** @gt_id: Unique ID of this GT within the PCI Device */ 243 __u16 gt_id; 244 /** @pad: MBZ */ 245 __u16 pad; 246 }; 247 248 /** 249 * struct drm_xe_engine - describe hardware engine 250 */ 251 struct drm_xe_engine { 252 /** @instance: The @drm_xe_engine_class_instance */ 253 struct drm_xe_engine_class_instance instance; 254 255 /** @reserved: Reserved */ 256 __u64 reserved[3]; 257 }; 258 259 /** 260 * struct drm_xe_query_engines - describe engines 261 * 262 * If a query is made with a struct @drm_xe_device_query where .query 263 * is equal to %DRM_XE_DEVICE_QUERY_ENGINES, then the reply uses an array of 264 * struct @drm_xe_query_engines in .data. 265 */ 266 struct drm_xe_query_engines { 267 /** @num_engines: number of engines returned in @engines */ 268 __u32 num_engines; 269 /** @pad: MBZ */ 270 __u32 pad; 271 /** @engines: The returned engines for this device */ 272 struct drm_xe_engine engines[]; 273 }; 274 275 /** 276 * enum drm_xe_memory_class - Supported memory classes. 277 */ 278 enum drm_xe_memory_class { 279 /** @DRM_XE_MEM_REGION_CLASS_SYSMEM: Represents system memory. */ 280 DRM_XE_MEM_REGION_CLASS_SYSMEM = 0, 281 /** 282 * @DRM_XE_MEM_REGION_CLASS_VRAM: On discrete platforms, this 283 * represents the memory that is local to the device, which we 284 * call VRAM. Not valid on integrated platforms. 285 */ 286 DRM_XE_MEM_REGION_CLASS_VRAM 287 }; 288 289 /** 290 * struct drm_xe_mem_region - Describes some region as known to 291 * the driver. 292 */ 293 struct drm_xe_mem_region { 294 /** 295 * @mem_class: The memory class describing this region. 296 * 297 * See enum drm_xe_memory_class for supported values. 298 */ 299 __u16 mem_class; 300 /** 301 * @instance: The unique ID for this region, which serves as the 302 * index in the placement bitmask used as argument for 303 * &DRM_IOCTL_XE_GEM_CREATE 304 */ 305 __u16 instance; 306 /** 307 * @min_page_size: Min page-size in bytes for this region. 308 * 309 * When the kernel allocates memory for this region, the 310 * underlying pages will be at least @min_page_size in size. 311 * Buffer objects with an allowable placement in this region must be 312 * created with a size aligned to this value. 313 * GPU virtual address mappings of (parts of) buffer objects that 314 * may be placed in this region must also have their GPU virtual 315 * address and range aligned to this value. 316 * Affected IOCTLS will return %-EINVAL if alignment restrictions are 317 * not met. 318 */ 319 __u32 min_page_size; 320 /** 321 * @total_size: The usable size in bytes for this region. 322 */ 323 __u64 total_size; 324 /** 325 * @used: Estimate of the memory used in bytes for this region. 326 * 327 * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable 328 * accounting. Without this the value here will always equal 329 * zero. 330 */ 331 __u64 used; 332 /** 333 * @cpu_visible_size: How much of this region can be CPU 334 * accessed, in bytes. 335 * 336 * This will always be <= @total_size, and the remainder (if 337 * any) will not be CPU accessible. If the CPU accessible part 338 * is smaller than @total_size then this is referred to as a 339 * small BAR system. 340 * 341 * On systems without small BAR (full BAR), the probed_size will 342 * always equal the @total_size, since all of it will be CPU 343 * accessible. 344 * 345 * Note this is only tracked for DRM_XE_MEM_REGION_CLASS_VRAM 346 * regions (for other types the value here will always equal 347 * zero). 348 */ 349 __u64 cpu_visible_size; 350 /** 351 * @cpu_visible_used: Estimate of CPU visible memory used, in 352 * bytes. 353 * 354 * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable 355 * accounting. Without this the value here will always equal 356 * zero. Note this is only currently tracked for 357 * DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value 358 * here will always be zero). 359 */ 360 __u64 cpu_visible_used; 361 /** @reserved: Reserved */ 362 __u64 reserved[6]; 363 }; 364 365 /** 366 * struct drm_xe_query_mem_regions - describe memory regions 367 * 368 * If a query is made with a struct drm_xe_device_query where .query 369 * is equal to DRM_XE_DEVICE_QUERY_MEM_REGIONS, then the reply uses 370 * struct drm_xe_query_mem_regions in .data. 371 */ 372 struct drm_xe_query_mem_regions { 373 /** @num_mem_regions: number of memory regions returned in @mem_regions */ 374 __u32 num_mem_regions; 375 /** @pad: MBZ */ 376 __u32 pad; 377 /** @mem_regions: The returned memory regions for this device */ 378 struct drm_xe_mem_region mem_regions[]; 379 }; 380 381 /** 382 * struct drm_xe_query_config - describe the device configuration 383 * 384 * If a query is made with a struct drm_xe_device_query where .query 385 * is equal to DRM_XE_DEVICE_QUERY_CONFIG, then the reply uses 386 * struct drm_xe_query_config in .data. 387 * 388 * The index in @info can be: 389 * - %DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID - Device ID (lower 16 bits) 390 * and the device revision (next 8 bits) 391 * - %DRM_XE_QUERY_CONFIG_FLAGS - Flags describing the device 392 * configuration, see list below 393 * 394 * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM - Flag is set if the device 395 * has usable VRAM 396 * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment 397 * required by this device, typically SZ_4K or SZ_64K 398 * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address 399 * - %DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY - Value of the highest 400 * available exec queue priority 401 */ 402 struct drm_xe_query_config { 403 /** @num_params: number of parameters returned in info */ 404 __u32 num_params; 405 406 /** @pad: MBZ */ 407 __u32 pad; 408 409 #define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0 410 #define DRM_XE_QUERY_CONFIG_FLAGS 1 411 #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0) 412 #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2 413 #define DRM_XE_QUERY_CONFIG_VA_BITS 3 414 #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4 415 /** @info: array of elements containing the config info */ 416 __u64 info[]; 417 }; 418 419 /** 420 * struct drm_xe_gt - describe an individual GT. 421 * 422 * To be used with drm_xe_query_gt_list, which will return a list with all the 423 * existing GT individual descriptions. 424 * Graphics Technology (GT) is a subset of a GPU/tile that is responsible for 425 * implementing graphics and/or media operations. 426 * 427 * The index in @type can be: 428 * - %DRM_XE_QUERY_GT_TYPE_MAIN 429 * - %DRM_XE_QUERY_GT_TYPE_MEDIA 430 */ 431 struct drm_xe_gt { 432 #define DRM_XE_QUERY_GT_TYPE_MAIN 0 433 #define DRM_XE_QUERY_GT_TYPE_MEDIA 1 434 /** @type: GT type: Main or Media */ 435 __u16 type; 436 /** @tile_id: Tile ID where this GT lives (Information only) */ 437 __u16 tile_id; 438 /** @gt_id: Unique ID of this GT within the PCI Device */ 439 __u16 gt_id; 440 /** @pad: MBZ */ 441 __u16 pad[3]; 442 /** @reference_clock: A clock frequency for timestamp */ 443 __u32 reference_clock; 444 /** 445 * @near_mem_regions: Bit mask of instances from 446 * drm_xe_query_mem_regions that are nearest to the current engines 447 * of this GT. 448 * Each index in this mask refers directly to the struct 449 * drm_xe_query_mem_regions' instance, no assumptions should 450 * be made about order. The type of each region is described 451 * by struct drm_xe_query_mem_regions' mem_class. 452 */ 453 __u64 near_mem_regions; 454 /** 455 * @far_mem_regions: Bit mask of instances from 456 * drm_xe_query_mem_regions that are far from the engines of this GT. 457 * In general, they have extra indirections when compared to the 458 * @near_mem_regions. For a discrete device this could mean system 459 * memory and memory living in a different tile. 460 * Each index in this mask refers directly to the struct 461 * drm_xe_query_mem_regions' instance, no assumptions should 462 * be made about order. The type of each region is described 463 * by struct drm_xe_query_mem_regions' mem_class. 464 */ 465 __u64 far_mem_regions; 466 /** @ip_ver_major: Graphics/media IP major version on GMD_ID platforms */ 467 __u16 ip_ver_major; 468 /** @ip_ver_minor: Graphics/media IP minor version on GMD_ID platforms */ 469 __u16 ip_ver_minor; 470 /** @ip_ver_rev: Graphics/media IP revision version on GMD_ID platforms */ 471 __u16 ip_ver_rev; 472 /** @pad2: MBZ */ 473 __u16 pad2; 474 /** @reserved: Reserved */ 475 __u64 reserved[7]; 476 }; 477 478 /** 479 * struct drm_xe_query_gt_list - A list with GT description items. 480 * 481 * If a query is made with a struct drm_xe_device_query where .query 482 * is equal to DRM_XE_DEVICE_QUERY_GT_LIST, then the reply uses struct 483 * drm_xe_query_gt_list in .data. 484 */ 485 struct drm_xe_query_gt_list { 486 /** @num_gt: number of GT items returned in gt_list */ 487 __u32 num_gt; 488 /** @pad: MBZ */ 489 __u32 pad; 490 /** @gt_list: The GT list returned for this device */ 491 struct drm_xe_gt gt_list[]; 492 }; 493 494 /** 495 * struct drm_xe_query_topology_mask - describe the topology mask of a GT 496 * 497 * This is the hardware topology which reflects the internal physical 498 * structure of the GPU. 499 * 500 * If a query is made with a struct drm_xe_device_query where .query 501 * is equal to DRM_XE_DEVICE_QUERY_GT_TOPOLOGY, then the reply uses 502 * struct drm_xe_query_topology_mask in .data. 503 * 504 * The @type can be: 505 * - %DRM_XE_TOPO_DSS_GEOMETRY - To query the mask of Dual Sub Slices 506 * (DSS) available for geometry operations. For example a query response 507 * containing the following in mask: 508 * ``DSS_GEOMETRY ff ff ff ff 00 00 00 00`` 509 * means 32 DSS are available for geometry. 510 * - %DRM_XE_TOPO_DSS_COMPUTE - To query the mask of Dual Sub Slices 511 * (DSS) available for compute operations. For example a query response 512 * containing the following in mask: 513 * ``DSS_COMPUTE ff ff ff ff 00 00 00 00`` 514 * means 32 DSS are available for compute. 515 * - %DRM_XE_TOPO_L3_BANK - To query the mask of enabled L3 banks. This type 516 * may be omitted if the driver is unable to query the mask from the 517 * hardware. 518 * - %DRM_XE_TOPO_EU_PER_DSS - To query the mask of Execution Units (EU) 519 * available per Dual Sub Slices (DSS). For example a query response 520 * containing the following in mask: 521 * ``EU_PER_DSS ff ff 00 00 00 00 00 00`` 522 * means each DSS has 16 SIMD8 EUs. This type may be omitted if device 523 * doesn't have SIMD8 EUs. 524 * - %DRM_XE_TOPO_SIMD16_EU_PER_DSS - To query the mask of SIMD16 Execution 525 * Units (EU) available per Dual Sub Slices (DSS). For example a query 526 * response containing the following in mask: 527 * ``SIMD16_EU_PER_DSS ff ff 00 00 00 00 00 00`` 528 * means each DSS has 16 SIMD16 EUs. This type may be omitted if device 529 * doesn't have SIMD16 EUs. 530 */ 531 struct drm_xe_query_topology_mask { 532 /** @gt_id: GT ID the mask is associated with */ 533 __u16 gt_id; 534 535 #define DRM_XE_TOPO_DSS_GEOMETRY 1 536 #define DRM_XE_TOPO_DSS_COMPUTE 2 537 #define DRM_XE_TOPO_L3_BANK 3 538 #define DRM_XE_TOPO_EU_PER_DSS 4 539 #define DRM_XE_TOPO_SIMD16_EU_PER_DSS 5 540 /** @type: type of mask */ 541 __u16 type; 542 543 /** @num_bytes: number of bytes in requested mask */ 544 __u32 num_bytes; 545 546 /** @mask: little-endian mask of @num_bytes */ 547 __u8 mask[]; 548 }; 549 550 /** 551 * struct drm_xe_query_engine_cycles - correlate CPU and GPU timestamps 552 * 553 * If a query is made with a struct drm_xe_device_query where .query is equal to 554 * DRM_XE_DEVICE_QUERY_ENGINE_CYCLES, then the reply uses struct drm_xe_query_engine_cycles 555 * in .data. struct drm_xe_query_engine_cycles is allocated by the user and 556 * .data points to this allocated structure. 557 * 558 * The query returns the engine cycles, which along with GT's @reference_clock, 559 * can be used to calculate the engine timestamp. In addition the 560 * query returns a set of cpu timestamps that indicate when the command 561 * streamer cycle count was captured. 562 */ 563 struct drm_xe_query_engine_cycles { 564 /** 565 * @eci: This is input by the user and is the engine for which command 566 * streamer cycles is queried. 567 */ 568 struct drm_xe_engine_class_instance eci; 569 570 /** 571 * @clockid: This is input by the user and is the reference clock id for 572 * CPU timestamp. For definition, see clock_gettime(2) and 573 * perf_event_open(2). Supported clock ids are CLOCK_MONOTONIC, 574 * CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, CLOCK_TAI. 575 */ 576 __s32 clockid; 577 578 /** @width: Width of the engine cycle counter in bits. */ 579 __u32 width; 580 581 /** 582 * @engine_cycles: Engine cycles as read from its register 583 * at 0x358 offset. 584 */ 585 __u64 engine_cycles; 586 587 /** 588 * @cpu_timestamp: CPU timestamp in ns. The timestamp is captured before 589 * reading the engine_cycles register using the reference clockid set by the 590 * user. 591 */ 592 __u64 cpu_timestamp; 593 594 /** 595 * @cpu_delta: Time delta in ns captured around reading the lower dword 596 * of the engine_cycles register. 597 */ 598 __u64 cpu_delta; 599 }; 600 601 /** 602 * struct drm_xe_query_uc_fw_version - query a micro-controller firmware version 603 * 604 * Given a uc_type this will return the branch, major, minor and patch version 605 * of the micro-controller firmware. 606 */ 607 struct drm_xe_query_uc_fw_version { 608 /** @uc_type: The micro-controller type to query firmware version */ 609 #define XE_QUERY_UC_TYPE_GUC_SUBMISSION 0 610 #define XE_QUERY_UC_TYPE_HUC 1 611 __u16 uc_type; 612 613 /** @pad: MBZ */ 614 __u16 pad; 615 616 /** @branch_ver: branch uc fw version */ 617 __u32 branch_ver; 618 /** @major_ver: major uc fw version */ 619 __u32 major_ver; 620 /** @minor_ver: minor uc fw version */ 621 __u32 minor_ver; 622 /** @patch_ver: patch uc fw version */ 623 __u32 patch_ver; 624 625 /** @pad2: MBZ */ 626 __u32 pad2; 627 628 /** @reserved: Reserved */ 629 __u64 reserved; 630 }; 631 632 /** 633 * struct drm_xe_device_query - Input of &DRM_IOCTL_XE_DEVICE_QUERY - main 634 * structure to query device information 635 * 636 * The user selects the type of data to query among DRM_XE_DEVICE_QUERY_* 637 * and sets the value in the query member. This determines the type of 638 * the structure provided by the driver in data, among struct drm_xe_query_*. 639 * 640 * The @query can be: 641 * - %DRM_XE_DEVICE_QUERY_ENGINES 642 * - %DRM_XE_DEVICE_QUERY_MEM_REGIONS 643 * - %DRM_XE_DEVICE_QUERY_CONFIG 644 * - %DRM_XE_DEVICE_QUERY_GT_LIST 645 * - %DRM_XE_DEVICE_QUERY_HWCONFIG - Query type to retrieve the hardware 646 * configuration of the device such as information on slices, memory, 647 * caches, and so on. It is provided as a table of key / value 648 * attributes. 649 * - %DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 650 * - %DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 651 * 652 * If size is set to 0, the driver fills it with the required size for 653 * the requested type of data to query. If size is equal to the required 654 * size, the queried information is copied into data. If size is set to 655 * a value different from 0 and different from the required size, the 656 * IOCTL call returns -EINVAL. 657 * 658 * For example the following code snippet allows retrieving and printing 659 * information about the device engines with DRM_XE_DEVICE_QUERY_ENGINES: 660 * 661 * .. code-block:: C 662 * 663 * struct drm_xe_query_engines *engines; 664 * struct drm_xe_device_query query = { 665 * .extensions = 0, 666 * .query = DRM_XE_DEVICE_QUERY_ENGINES, 667 * .size = 0, 668 * .data = 0, 669 * }; 670 * ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query); 671 * engines = malloc(query.size); 672 * query.data = (uintptr_t)engines; 673 * ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query); 674 * for (int i = 0; i < engines->num_engines; i++) { 675 * printf("Engine %d: %s\n", i, 676 * engines->engines[i].instance.engine_class == 677 * DRM_XE_ENGINE_CLASS_RENDER ? "RENDER": 678 * engines->engines[i].instance.engine_class == 679 * DRM_XE_ENGINE_CLASS_COPY ? "COPY": 680 * engines->engines[i].instance.engine_class == 681 * DRM_XE_ENGINE_CLASS_VIDEO_DECODE ? "VIDEO_DECODE": 682 * engines->engines[i].instance.engine_class == 683 * DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE ? "VIDEO_ENHANCE": 684 * engines->engines[i].instance.engine_class == 685 * DRM_XE_ENGINE_CLASS_COMPUTE ? "COMPUTE": 686 * "UNKNOWN"); 687 * } 688 * free(engines); 689 */ 690 struct drm_xe_device_query { 691 /** @extensions: Pointer to the first extension struct, if any */ 692 __u64 extensions; 693 694 #define DRM_XE_DEVICE_QUERY_ENGINES 0 695 #define DRM_XE_DEVICE_QUERY_MEM_REGIONS 1 696 #define DRM_XE_DEVICE_QUERY_CONFIG 2 697 #define DRM_XE_DEVICE_QUERY_GT_LIST 3 698 #define DRM_XE_DEVICE_QUERY_HWCONFIG 4 699 #define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5 700 #define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 6 701 #define DRM_XE_DEVICE_QUERY_UC_FW_VERSION 7 702 #define DRM_XE_DEVICE_QUERY_OA_UNITS 8 703 /** @query: The type of data to query */ 704 __u32 query; 705 706 /** @size: Size of the queried data */ 707 __u32 size; 708 709 /** @data: Queried data is placed here */ 710 __u64 data; 711 712 /** @reserved: Reserved */ 713 __u64 reserved[2]; 714 }; 715 716 /** 717 * struct drm_xe_gem_create - Input of &DRM_IOCTL_XE_GEM_CREATE - A structure for 718 * gem creation 719 * 720 * The @flags can be: 721 * - %DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING 722 * - %DRM_XE_GEM_CREATE_FLAG_SCANOUT 723 * - %DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM - When using VRAM as a 724 * possible placement, ensure that the corresponding VRAM allocation 725 * will always use the CPU accessible part of VRAM. This is important 726 * for small-bar systems (on full-bar systems this gets turned into a 727 * noop). 728 * Note1: System memory can be used as an extra placement if the kernel 729 * should spill the allocation to system memory, if space can't be made 730 * available in the CPU accessible part of VRAM (giving the same 731 * behaviour as the i915 interface, see 732 * I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS). 733 * Note2: For clear-color CCS surfaces the kernel needs to read the 734 * clear-color value stored in the buffer, and on discrete platforms we 735 * need to use VRAM for display surfaces, therefore the kernel requires 736 * setting this flag for such objects, otherwise an error is thrown on 737 * small-bar systems. 738 * 739 * @cpu_caching supports the following values: 740 * - %DRM_XE_GEM_CPU_CACHING_WB - Allocate the pages with write-back 741 * caching. On iGPU this can't be used for scanout surfaces. Currently 742 * not allowed for objects placed in VRAM. 743 * - %DRM_XE_GEM_CPU_CACHING_WC - Allocate the pages as write-combined. This 744 * is uncached. Scanout surfaces should likely use this. All objects 745 * that can be placed in VRAM must use this. 746 */ 747 struct drm_xe_gem_create { 748 /** @extensions: Pointer to the first extension struct, if any */ 749 __u64 extensions; 750 751 /** 752 * @size: Size of the object to be created, must match region 753 * (system or vram) minimum alignment (&min_page_size). 754 */ 755 __u64 size; 756 757 /** 758 * @placement: A mask of memory instances of where BO can be placed. 759 * Each index in this mask refers directly to the struct 760 * drm_xe_query_mem_regions' instance, no assumptions should 761 * be made about order. The type of each region is described 762 * by struct drm_xe_query_mem_regions' mem_class. 763 */ 764 __u32 placement; 765 766 #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING (1 << 0) 767 #define DRM_XE_GEM_CREATE_FLAG_SCANOUT (1 << 1) 768 #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (1 << 2) 769 /** 770 * @flags: Flags, currently a mask of memory instances of where BO can 771 * be placed 772 */ 773 __u32 flags; 774 775 /** 776 * @vm_id: Attached VM, if any 777 * 778 * If a VM is specified, this BO must: 779 * 780 * 1. Only ever be bound to that VM. 781 * 2. Cannot be exported as a PRIME fd. 782 */ 783 __u32 vm_id; 784 785 /** 786 * @handle: Returned handle for the object. 787 * 788 * Object handles are nonzero. 789 */ 790 __u32 handle; 791 792 #define DRM_XE_GEM_CPU_CACHING_WB 1 793 #define DRM_XE_GEM_CPU_CACHING_WC 2 794 /** 795 * @cpu_caching: The CPU caching mode to select for this object. If 796 * mmaping the object the mode selected here will also be used. The 797 * exception is when mapping system memory (including data evicted 798 * to system) on discrete GPUs. The caching mode selected will 799 * then be overridden to DRM_XE_GEM_CPU_CACHING_WB, and coherency 800 * between GPU- and CPU is guaranteed. The caching mode of 801 * existing CPU-mappings will be updated transparently to 802 * user-space clients. 803 */ 804 __u16 cpu_caching; 805 /** @pad: MBZ */ 806 __u16 pad[3]; 807 808 /** @reserved: Reserved */ 809 __u64 reserved[2]; 810 }; 811 812 /** 813 * struct drm_xe_gem_mmap_offset - Input of &DRM_IOCTL_XE_GEM_MMAP_OFFSET 814 */ 815 struct drm_xe_gem_mmap_offset { 816 /** @extensions: Pointer to the first extension struct, if any */ 817 __u64 extensions; 818 819 /** @handle: Handle for the object being mapped. */ 820 __u32 handle; 821 822 /** @flags: Must be zero */ 823 __u32 flags; 824 825 /** @offset: The fake offset to use for subsequent mmap call */ 826 __u64 offset; 827 828 /** @reserved: Reserved */ 829 __u64 reserved[2]; 830 }; 831 832 /** 833 * struct drm_xe_vm_create - Input of &DRM_IOCTL_XE_VM_CREATE 834 * 835 * The @flags can be: 836 * - %DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE 837 * - %DRM_XE_VM_CREATE_FLAG_LR_MODE - An LR, or Long Running VM accepts 838 * exec submissions to its exec_queues that don't have an upper time 839 * limit on the job execution time. But exec submissions to these 840 * don't allow any of the flags DRM_XE_SYNC_FLAG_SYNCOBJ, 841 * DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ, DRM_XE_SYNC_FLAG_DMA_BUF, 842 * used as out-syncobjs, that is, together with DRM_XE_SYNC_FLAG_SIGNAL. 843 * LR VMs can be created in recoverable page-fault mode using 844 * DRM_XE_VM_CREATE_FLAG_FAULT_MODE, if the device supports it. 845 * If that flag is omitted, the UMD can not rely on the slightly 846 * different per-VM overcommit semantics that are enabled by 847 * DRM_XE_VM_CREATE_FLAG_FAULT_MODE (see below), but KMD may 848 * still enable recoverable pagefaults if supported by the device. 849 * - %DRM_XE_VM_CREATE_FLAG_FAULT_MODE - Requires also 850 * DRM_XE_VM_CREATE_FLAG_LR_MODE. It allows memory to be allocated on 851 * demand when accessed, and also allows per-VM overcommit of memory. 852 * The xe driver internally uses recoverable pagefaults to implement 853 * this. 854 */ 855 struct drm_xe_vm_create { 856 /** @extensions: Pointer to the first extension struct, if any */ 857 __u64 extensions; 858 859 #define DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE (1 << 0) 860 #define DRM_XE_VM_CREATE_FLAG_LR_MODE (1 << 1) 861 #define DRM_XE_VM_CREATE_FLAG_FAULT_MODE (1 << 2) 862 /** @flags: Flags */ 863 __u32 flags; 864 865 /** @vm_id: Returned VM ID */ 866 __u32 vm_id; 867 868 /** @reserved: Reserved */ 869 __u64 reserved[2]; 870 }; 871 872 /** 873 * struct drm_xe_vm_destroy - Input of &DRM_IOCTL_XE_VM_DESTROY 874 */ 875 struct drm_xe_vm_destroy { 876 /** @vm_id: VM ID */ 877 __u32 vm_id; 878 879 /** @pad: MBZ */ 880 __u32 pad; 881 882 /** @reserved: Reserved */ 883 __u64 reserved[2]; 884 }; 885 886 /** 887 * struct drm_xe_vm_bind_op - run bind operations 888 * 889 * The @op can be: 890 * - %DRM_XE_VM_BIND_OP_MAP 891 * - %DRM_XE_VM_BIND_OP_UNMAP 892 * - %DRM_XE_VM_BIND_OP_MAP_USERPTR 893 * - %DRM_XE_VM_BIND_OP_UNMAP_ALL 894 * - %DRM_XE_VM_BIND_OP_PREFETCH 895 * 896 * and the @flags can be: 897 * - %DRM_XE_VM_BIND_FLAG_READONLY - Setup the page tables as read-only 898 * to ensure write protection 899 * - %DRM_XE_VM_BIND_FLAG_IMMEDIATE - On a faulting VM, do the 900 * MAP operation immediately rather than deferring the MAP to the page 901 * fault handler. This is implied on a non-faulting VM as there is no 902 * fault handler to defer to. 903 * - %DRM_XE_VM_BIND_FLAG_NULL - When the NULL flag is set, the page 904 * tables are setup with a special bit which indicates writes are 905 * dropped and all reads return zero. In the future, the NULL flags 906 * will only be valid for DRM_XE_VM_BIND_OP_MAP operations, the BO 907 * handle MBZ, and the BO offset MBZ. This flag is intended to 908 * implement VK sparse bindings. 909 */ 910 struct drm_xe_vm_bind_op { 911 /** @extensions: Pointer to the first extension struct, if any */ 912 __u64 extensions; 913 914 /** 915 * @obj: GEM object to operate on, MBZ for MAP_USERPTR, MBZ for UNMAP 916 */ 917 __u32 obj; 918 919 /** 920 * @pat_index: The platform defined @pat_index to use for this mapping. 921 * The index basically maps to some predefined memory attributes, 922 * including things like caching, coherency, compression etc. The exact 923 * meaning of the pat_index is platform specific and defined in the 924 * Bspec and PRMs. When the KMD sets up the binding the index here is 925 * encoded into the ppGTT PTE. 926 * 927 * For coherency the @pat_index needs to be at least 1way coherent when 928 * drm_xe_gem_create.cpu_caching is DRM_XE_GEM_CPU_CACHING_WB. The KMD 929 * will extract the coherency mode from the @pat_index and reject if 930 * there is a mismatch (see note below for pre-MTL platforms). 931 * 932 * Note: On pre-MTL platforms there is only a caching mode and no 933 * explicit coherency mode, but on such hardware there is always a 934 * shared-LLC (or is dgpu) so all GT memory accesses are coherent with 935 * CPU caches even with the caching mode set as uncached. It's only the 936 * display engine that is incoherent (on dgpu it must be in VRAM which 937 * is always mapped as WC on the CPU). However to keep the uapi somewhat 938 * consistent with newer platforms the KMD groups the different cache 939 * levels into the following coherency buckets on all pre-MTL platforms: 940 * 941 * ppGTT UC -> COH_NONE 942 * ppGTT WC -> COH_NONE 943 * ppGTT WT -> COH_NONE 944 * ppGTT WB -> COH_AT_LEAST_1WAY 945 * 946 * In practice UC/WC/WT should only ever used for scanout surfaces on 947 * such platforms (or perhaps in general for dma-buf if shared with 948 * another device) since it is only the display engine that is actually 949 * incoherent. Everything else should typically use WB given that we 950 * have a shared-LLC. On MTL+ this completely changes and the HW 951 * defines the coherency mode as part of the @pat_index, where 952 * incoherent GT access is possible. 953 * 954 * Note: For userptr and externally imported dma-buf the kernel expects 955 * either 1WAY or 2WAY for the @pat_index. 956 * 957 * For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD restrictions 958 * on the @pat_index. For such mappings there is no actual memory being 959 * mapped (the address in the PTE is invalid), so the various PAT memory 960 * attributes likely do not apply. Simply leaving as zero is one 961 * option (still a valid pat_index). 962 */ 963 __u16 pat_index; 964 965 /** @pad: MBZ */ 966 __u16 pad; 967 968 union { 969 /** 970 * @obj_offset: Offset into the object, MBZ for CLEAR_RANGE, 971 * ignored for unbind 972 */ 973 __u64 obj_offset; 974 975 /** @userptr: user pointer to bind on */ 976 __u64 userptr; 977 }; 978 979 /** 980 * @range: Number of bytes from the object to bind to addr, MBZ for UNMAP_ALL 981 */ 982 __u64 range; 983 984 /** @addr: Address to operate on, MBZ for UNMAP_ALL */ 985 __u64 addr; 986 987 #define DRM_XE_VM_BIND_OP_MAP 0x0 988 #define DRM_XE_VM_BIND_OP_UNMAP 0x1 989 #define DRM_XE_VM_BIND_OP_MAP_USERPTR 0x2 990 #define DRM_XE_VM_BIND_OP_UNMAP_ALL 0x3 991 #define DRM_XE_VM_BIND_OP_PREFETCH 0x4 992 /** @op: Bind operation to perform */ 993 __u32 op; 994 995 #define DRM_XE_VM_BIND_FLAG_READONLY (1 << 0) 996 #define DRM_XE_VM_BIND_FLAG_IMMEDIATE (1 << 1) 997 #define DRM_XE_VM_BIND_FLAG_NULL (1 << 2) 998 #define DRM_XE_VM_BIND_FLAG_DUMPABLE (1 << 3) 999 /** @flags: Bind flags */ 1000 __u32 flags; 1001 1002 /** 1003 * @prefetch_mem_region_instance: Memory region to prefetch VMA to. 1004 * It is a region instance, not a mask. 1005 * To be used only with %DRM_XE_VM_BIND_OP_PREFETCH operation. 1006 */ 1007 __u32 prefetch_mem_region_instance; 1008 1009 /** @pad2: MBZ */ 1010 __u32 pad2; 1011 1012 /** @reserved: Reserved */ 1013 __u64 reserved[3]; 1014 }; 1015 1016 /** 1017 * struct drm_xe_vm_bind - Input of &DRM_IOCTL_XE_VM_BIND 1018 * 1019 * Below is an example of a minimal use of @drm_xe_vm_bind to 1020 * asynchronously bind the buffer `data` at address `BIND_ADDRESS` to 1021 * illustrate `userptr`. It can be synchronized by using the example 1022 * provided for @drm_xe_sync. 1023 * 1024 * .. code-block:: C 1025 * 1026 * data = aligned_alloc(ALIGNMENT, BO_SIZE); 1027 * struct drm_xe_vm_bind bind = { 1028 * .vm_id = vm, 1029 * .num_binds = 1, 1030 * .bind.obj = 0, 1031 * .bind.obj_offset = to_user_pointer(data), 1032 * .bind.range = BO_SIZE, 1033 * .bind.addr = BIND_ADDRESS, 1034 * .bind.op = DRM_XE_VM_BIND_OP_MAP_USERPTR, 1035 * .bind.flags = 0, 1036 * .num_syncs = 1, 1037 * .syncs = &sync, 1038 * .exec_queue_id = 0, 1039 * }; 1040 * ioctl(fd, DRM_IOCTL_XE_VM_BIND, &bind); 1041 * 1042 */ 1043 struct drm_xe_vm_bind { 1044 /** @extensions: Pointer to the first extension struct, if any */ 1045 __u64 extensions; 1046 1047 /** @vm_id: The ID of the VM to bind to */ 1048 __u32 vm_id; 1049 1050 /** 1051 * @exec_queue_id: exec_queue_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND 1052 * and exec queue must have same vm_id. If zero, the default VM bind engine 1053 * is used. 1054 */ 1055 __u32 exec_queue_id; 1056 1057 /** @pad: MBZ */ 1058 __u32 pad; 1059 1060 /** @num_binds: number of binds in this IOCTL */ 1061 __u32 num_binds; 1062 1063 union { 1064 /** @bind: used if num_binds == 1 */ 1065 struct drm_xe_vm_bind_op bind; 1066 1067 /** 1068 * @vector_of_binds: userptr to array of struct 1069 * drm_xe_vm_bind_op if num_binds > 1 1070 */ 1071 __u64 vector_of_binds; 1072 }; 1073 1074 /** @pad2: MBZ */ 1075 __u32 pad2; 1076 1077 /** @num_syncs: amount of syncs to wait on */ 1078 __u32 num_syncs; 1079 1080 /** @syncs: pointer to struct drm_xe_sync array */ 1081 __u64 syncs; 1082 1083 /** @reserved: Reserved */ 1084 __u64 reserved[2]; 1085 }; 1086 1087 /** 1088 * struct drm_xe_exec_queue_create - Input of &DRM_IOCTL_XE_EXEC_QUEUE_CREATE 1089 * 1090 * The example below shows how to use @drm_xe_exec_queue_create to create 1091 * a simple exec_queue (no parallel submission) of class 1092 * &DRM_XE_ENGINE_CLASS_RENDER. 1093 * 1094 * .. code-block:: C 1095 * 1096 * struct drm_xe_engine_class_instance instance = { 1097 * .engine_class = DRM_XE_ENGINE_CLASS_RENDER, 1098 * }; 1099 * struct drm_xe_exec_queue_create exec_queue_create = { 1100 * .extensions = 0, 1101 * .vm_id = vm, 1102 * .num_bb_per_exec = 1, 1103 * .num_eng_per_bb = 1, 1104 * .instances = to_user_pointer(&instance), 1105 * }; 1106 * ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create); 1107 * 1108 */ 1109 struct drm_xe_exec_queue_create { 1110 #define DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0 1111 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0 1112 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1 1113 1114 /** @extensions: Pointer to the first extension struct, if any */ 1115 __u64 extensions; 1116 1117 /** @width: submission width (number BB per exec) for this exec queue */ 1118 __u16 width; 1119 1120 /** @num_placements: number of valid placements for this exec queue */ 1121 __u16 num_placements; 1122 1123 /** @vm_id: VM to use for this exec queue */ 1124 __u32 vm_id; 1125 1126 /** @flags: MBZ */ 1127 __u32 flags; 1128 1129 /** @exec_queue_id: Returned exec queue ID */ 1130 __u32 exec_queue_id; 1131 1132 /** 1133 * @instances: user pointer to a 2-d array of struct 1134 * drm_xe_engine_class_instance 1135 * 1136 * length = width (i) * num_placements (j) 1137 * index = j + i * width 1138 */ 1139 __u64 instances; 1140 1141 /** @reserved: Reserved */ 1142 __u64 reserved[2]; 1143 }; 1144 1145 /** 1146 * struct drm_xe_exec_queue_destroy - Input of &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY 1147 */ 1148 struct drm_xe_exec_queue_destroy { 1149 /** @exec_queue_id: Exec queue ID */ 1150 __u32 exec_queue_id; 1151 1152 /** @pad: MBZ */ 1153 __u32 pad; 1154 1155 /** @reserved: Reserved */ 1156 __u64 reserved[2]; 1157 }; 1158 1159 /** 1160 * struct drm_xe_exec_queue_get_property - Input of &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY 1161 * 1162 * The @property can be: 1163 * - %DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 1164 */ 1165 struct drm_xe_exec_queue_get_property { 1166 /** @extensions: Pointer to the first extension struct, if any */ 1167 __u64 extensions; 1168 1169 /** @exec_queue_id: Exec queue ID */ 1170 __u32 exec_queue_id; 1171 1172 #define DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 0 1173 /** @property: property to get */ 1174 __u32 property; 1175 1176 /** @value: property value */ 1177 __u64 value; 1178 1179 /** @reserved: Reserved */ 1180 __u64 reserved[2]; 1181 }; 1182 1183 /** 1184 * struct drm_xe_sync - sync object 1185 * 1186 * The @type can be: 1187 * - %DRM_XE_SYNC_TYPE_SYNCOBJ 1188 * - %DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ 1189 * - %DRM_XE_SYNC_TYPE_USER_FENCE 1190 * 1191 * and the @flags can be: 1192 * - %DRM_XE_SYNC_FLAG_SIGNAL 1193 * 1194 * A minimal use of @drm_xe_sync looks like this: 1195 * 1196 * .. code-block:: C 1197 * 1198 * struct drm_xe_sync sync = { 1199 * .flags = DRM_XE_SYNC_FLAG_SIGNAL, 1200 * .type = DRM_XE_SYNC_TYPE_SYNCOBJ, 1201 * }; 1202 * struct drm_syncobj_create syncobj_create = { 0 }; 1203 * ioctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, &syncobj_create); 1204 * sync.handle = syncobj_create.handle; 1205 * ... 1206 * use of &sync in drm_xe_exec or drm_xe_vm_bind 1207 * ... 1208 * struct drm_syncobj_wait wait = { 1209 * .handles = &sync.handle, 1210 * .timeout_nsec = INT64_MAX, 1211 * .count_handles = 1, 1212 * .flags = 0, 1213 * .first_signaled = 0, 1214 * .pad = 0, 1215 * }; 1216 * ioctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &wait); 1217 */ 1218 struct drm_xe_sync { 1219 /** @extensions: Pointer to the first extension struct, if any */ 1220 __u64 extensions; 1221 1222 #define DRM_XE_SYNC_TYPE_SYNCOBJ 0x0 1223 #define DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ 0x1 1224 #define DRM_XE_SYNC_TYPE_USER_FENCE 0x2 1225 /** @type: Type of the this sync object */ 1226 __u32 type; 1227 1228 #define DRM_XE_SYNC_FLAG_SIGNAL (1 << 0) 1229 /** @flags: Sync Flags */ 1230 __u32 flags; 1231 1232 union { 1233 /** @handle: Handle for the object */ 1234 __u32 handle; 1235 1236 /** 1237 * @addr: Address of user fence. When sync is passed in via exec 1238 * IOCTL this is a GPU address in the VM. When sync passed in via 1239 * VM bind IOCTL this is a user pointer. In either case, it is 1240 * the users responsibility that this address is present and 1241 * mapped when the user fence is signalled. Must be qword 1242 * aligned. 1243 */ 1244 __u64 addr; 1245 }; 1246 1247 /** 1248 * @timeline_value: Input for the timeline sync object. Needs to be 1249 * different than 0 when used with %DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ. 1250 */ 1251 __u64 timeline_value; 1252 1253 /** @reserved: Reserved */ 1254 __u64 reserved[2]; 1255 }; 1256 1257 /** 1258 * struct drm_xe_exec - Input of &DRM_IOCTL_XE_EXEC 1259 * 1260 * This is an example to use @drm_xe_exec for execution of the object 1261 * at BIND_ADDRESS (see example in @drm_xe_vm_bind) by an exec_queue 1262 * (see example in @drm_xe_exec_queue_create). It can be synchronized 1263 * by using the example provided for @drm_xe_sync. 1264 * 1265 * .. code-block:: C 1266 * 1267 * struct drm_xe_exec exec = { 1268 * .exec_queue_id = exec_queue, 1269 * .syncs = &sync, 1270 * .num_syncs = 1, 1271 * .address = BIND_ADDRESS, 1272 * .num_batch_buffer = 1, 1273 * }; 1274 * ioctl(fd, DRM_IOCTL_XE_EXEC, &exec); 1275 * 1276 */ 1277 struct drm_xe_exec { 1278 /** @extensions: Pointer to the first extension struct, if any */ 1279 __u64 extensions; 1280 1281 /** @exec_queue_id: Exec queue ID for the batch buffer */ 1282 __u32 exec_queue_id; 1283 1284 /** @num_syncs: Amount of struct drm_xe_sync in array. */ 1285 __u32 num_syncs; 1286 1287 /** @syncs: Pointer to struct drm_xe_sync array. */ 1288 __u64 syncs; 1289 1290 /** 1291 * @address: address of batch buffer if num_batch_buffer == 1 or an 1292 * array of batch buffer addresses 1293 */ 1294 __u64 address; 1295 1296 /** 1297 * @num_batch_buffer: number of batch buffer in this exec, must match 1298 * the width of the engine 1299 */ 1300 __u16 num_batch_buffer; 1301 1302 /** @pad: MBZ */ 1303 __u16 pad[3]; 1304 1305 /** @reserved: Reserved */ 1306 __u64 reserved[2]; 1307 }; 1308 1309 /** 1310 * struct drm_xe_wait_user_fence - Input of &DRM_IOCTL_XE_WAIT_USER_FENCE 1311 * 1312 * Wait on user fence, XE will wake-up on every HW engine interrupt in the 1313 * instances list and check if user fence is complete:: 1314 * 1315 * (*addr & MASK) OP (VALUE & MASK) 1316 * 1317 * Returns to user on user fence completion or timeout. 1318 * 1319 * The @op can be: 1320 * - %DRM_XE_UFENCE_WAIT_OP_EQ 1321 * - %DRM_XE_UFENCE_WAIT_OP_NEQ 1322 * - %DRM_XE_UFENCE_WAIT_OP_GT 1323 * - %DRM_XE_UFENCE_WAIT_OP_GTE 1324 * - %DRM_XE_UFENCE_WAIT_OP_LT 1325 * - %DRM_XE_UFENCE_WAIT_OP_LTE 1326 * 1327 * and the @flags can be: 1328 * - %DRM_XE_UFENCE_WAIT_FLAG_ABSTIME 1329 * - %DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP 1330 * 1331 * The @mask values can be for example: 1332 * - 0xffu for u8 1333 * - 0xffffu for u16 1334 * - 0xffffffffu for u32 1335 * - 0xffffffffffffffffu for u64 1336 */ 1337 struct drm_xe_wait_user_fence { 1338 /** @extensions: Pointer to the first extension struct, if any */ 1339 __u64 extensions; 1340 1341 /** 1342 * @addr: user pointer address to wait on, must qword aligned 1343 */ 1344 __u64 addr; 1345 1346 #define DRM_XE_UFENCE_WAIT_OP_EQ 0x0 1347 #define DRM_XE_UFENCE_WAIT_OP_NEQ 0x1 1348 #define DRM_XE_UFENCE_WAIT_OP_GT 0x2 1349 #define DRM_XE_UFENCE_WAIT_OP_GTE 0x3 1350 #define DRM_XE_UFENCE_WAIT_OP_LT 0x4 1351 #define DRM_XE_UFENCE_WAIT_OP_LTE 0x5 1352 /** @op: wait operation (type of comparison) */ 1353 __u16 op; 1354 1355 #define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 0) 1356 /** @flags: wait flags */ 1357 __u16 flags; 1358 1359 /** @pad: MBZ */ 1360 __u32 pad; 1361 1362 /** @value: compare value */ 1363 __u64 value; 1364 1365 /** @mask: comparison mask */ 1366 __u64 mask; 1367 1368 /** 1369 * @timeout: how long to wait before bailing, value in nanoseconds. 1370 * Without DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag set (relative timeout) 1371 * it contains timeout expressed in nanoseconds to wait (fence will 1372 * expire at now() + timeout). 1373 * When DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flat is set (absolute timeout) wait 1374 * will end at timeout (uses system MONOTONIC_CLOCK). 1375 * Passing negative timeout leads to neverending wait. 1376 * 1377 * On relative timeout this value is updated with timeout left 1378 * (for restarting the call in case of signal delivery). 1379 * On absolute timeout this value stays intact (restarted call still 1380 * expire at the same point of time). 1381 */ 1382 __s64 timeout; 1383 1384 /** @exec_queue_id: exec_queue_id returned from xe_exec_queue_create_ioctl */ 1385 __u32 exec_queue_id; 1386 1387 /** @pad2: MBZ */ 1388 __u32 pad2; 1389 1390 /** @reserved: Reserved */ 1391 __u64 reserved[2]; 1392 }; 1393 1394 /** 1395 * enum drm_xe_observation_type - Observation stream types 1396 */ 1397 enum drm_xe_observation_type { 1398 /** @DRM_XE_OBSERVATION_TYPE_OA: OA observation stream type */ 1399 DRM_XE_OBSERVATION_TYPE_OA, 1400 }; 1401 1402 /** 1403 * enum drm_xe_observation_op - Observation stream ops 1404 */ 1405 enum drm_xe_observation_op { 1406 /** @DRM_XE_OBSERVATION_OP_STREAM_OPEN: Open an observation stream */ 1407 DRM_XE_OBSERVATION_OP_STREAM_OPEN, 1408 1409 /** @DRM_XE_OBSERVATION_OP_ADD_CONFIG: Add observation stream config */ 1410 DRM_XE_OBSERVATION_OP_ADD_CONFIG, 1411 1412 /** @DRM_XE_OBSERVATION_OP_REMOVE_CONFIG: Remove observation stream config */ 1413 DRM_XE_OBSERVATION_OP_REMOVE_CONFIG, 1414 }; 1415 1416 /** 1417 * struct drm_xe_observation_param - Input of &DRM_XE_OBSERVATION 1418 * 1419 * The observation layer enables multiplexing observation streams of 1420 * multiple types. The actual params for a particular stream operation are 1421 * supplied via the @param pointer (use __copy_from_user to get these 1422 * params). 1423 */ 1424 struct drm_xe_observation_param { 1425 /** @extensions: Pointer to the first extension struct, if any */ 1426 __u64 extensions; 1427 /** @observation_type: observation stream type, of enum @drm_xe_observation_type */ 1428 __u64 observation_type; 1429 /** @observation_op: observation stream op, of enum @drm_xe_observation_op */ 1430 __u64 observation_op; 1431 /** @param: Pointer to actual stream params */ 1432 __u64 param; 1433 }; 1434 1435 /** 1436 * enum drm_xe_observation_ioctls - Observation stream fd ioctl's 1437 * 1438 * Information exchanged between userspace and kernel for observation fd 1439 * ioctl's is stream type specific 1440 */ 1441 enum drm_xe_observation_ioctls { 1442 /** @DRM_XE_OBSERVATION_IOCTL_ENABLE: Enable data capture for an observation stream */ 1443 DRM_XE_OBSERVATION_IOCTL_ENABLE = _IO('i', 0x0), 1444 1445 /** @DRM_XE_OBSERVATION_IOCTL_DISABLE: Disable data capture for a observation stream */ 1446 DRM_XE_OBSERVATION_IOCTL_DISABLE = _IO('i', 0x1), 1447 1448 /** @DRM_XE_OBSERVATION_IOCTL_CONFIG: Change observation stream configuration */ 1449 DRM_XE_OBSERVATION_IOCTL_CONFIG = _IO('i', 0x2), 1450 1451 /** @DRM_XE_OBSERVATION_IOCTL_STATUS: Return observation stream status */ 1452 DRM_XE_OBSERVATION_IOCTL_STATUS = _IO('i', 0x3), 1453 1454 /** @DRM_XE_OBSERVATION_IOCTL_INFO: Return observation stream info */ 1455 DRM_XE_OBSERVATION_IOCTL_INFO = _IO('i', 0x4), 1456 }; 1457 1458 /** 1459 * enum drm_xe_oa_unit_type - OA unit types 1460 */ 1461 enum drm_xe_oa_unit_type { 1462 /** 1463 * @DRM_XE_OA_UNIT_TYPE_OAG: OAG OA unit. OAR/OAC are considered 1464 * sub-types of OAG. For OAR/OAC, use OAG. 1465 */ 1466 DRM_XE_OA_UNIT_TYPE_OAG, 1467 1468 /** @DRM_XE_OA_UNIT_TYPE_OAM: OAM OA unit */ 1469 DRM_XE_OA_UNIT_TYPE_OAM, 1470 }; 1471 1472 /** 1473 * struct drm_xe_oa_unit - describe OA unit 1474 */ 1475 struct drm_xe_oa_unit { 1476 /** @extensions: Pointer to the first extension struct, if any */ 1477 __u64 extensions; 1478 1479 /** @oa_unit_id: OA unit ID */ 1480 __u32 oa_unit_id; 1481 1482 /** @oa_unit_type: OA unit type of @drm_xe_oa_unit_type */ 1483 __u32 oa_unit_type; 1484 1485 /** @capabilities: OA capabilities bit-mask */ 1486 __u64 capabilities; 1487 #define DRM_XE_OA_CAPS_BASE (1 << 0) 1488 #define DRM_XE_OA_CAPS_SYNCS (1 << 1) 1489 #define DRM_XE_OA_CAPS_OA_BUFFER_SIZE (1 << 2) 1490 #define DRM_XE_OA_CAPS_WAIT_NUM_REPORTS (1 << 3) 1491 1492 /** @oa_timestamp_freq: OA timestamp freq */ 1493 __u64 oa_timestamp_freq; 1494 1495 /** @reserved: MBZ */ 1496 __u64 reserved[4]; 1497 1498 /** @num_engines: number of engines in @eci array */ 1499 __u64 num_engines; 1500 1501 /** @eci: engines attached to this OA unit */ 1502 struct drm_xe_engine_class_instance eci[]; 1503 }; 1504 1505 /** 1506 * struct drm_xe_query_oa_units - describe OA units 1507 * 1508 * If a query is made with a struct drm_xe_device_query where .query 1509 * is equal to DRM_XE_DEVICE_QUERY_OA_UNITS, then the reply uses struct 1510 * drm_xe_query_oa_units in .data. 1511 * 1512 * OA unit properties for all OA units can be accessed using a code block 1513 * such as the one below: 1514 * 1515 * .. code-block:: C 1516 * 1517 * struct drm_xe_query_oa_units *qoa; 1518 * struct drm_xe_oa_unit *oau; 1519 * u8 *poau; 1520 * 1521 * // malloc qoa and issue DRM_XE_DEVICE_QUERY_OA_UNITS. Then: 1522 * poau = (u8 *)&qoa->oa_units[0]; 1523 * for (int i = 0; i < qoa->num_oa_units; i++) { 1524 * oau = (struct drm_xe_oa_unit *)poau; 1525 * // Access 'struct drm_xe_oa_unit' fields here 1526 * poau += sizeof(*oau) + oau->num_engines * sizeof(oau->eci[0]); 1527 * } 1528 */ 1529 struct drm_xe_query_oa_units { 1530 /** @extensions: Pointer to the first extension struct, if any */ 1531 __u64 extensions; 1532 /** @num_oa_units: number of OA units returned in oau[] */ 1533 __u32 num_oa_units; 1534 /** @pad: MBZ */ 1535 __u32 pad; 1536 /** 1537 * @oa_units: struct @drm_xe_oa_unit array returned for this device. 1538 * Written below as a u64 array to avoid problems with nested flexible 1539 * arrays with some compilers 1540 */ 1541 __u64 oa_units[]; 1542 }; 1543 1544 /** 1545 * enum drm_xe_oa_format_type - OA format types as specified in PRM/Bspec 1546 * 52198/60942 1547 */ 1548 enum drm_xe_oa_format_type { 1549 /** @DRM_XE_OA_FMT_TYPE_OAG: OAG report format */ 1550 DRM_XE_OA_FMT_TYPE_OAG, 1551 /** @DRM_XE_OA_FMT_TYPE_OAR: OAR report format */ 1552 DRM_XE_OA_FMT_TYPE_OAR, 1553 /** @DRM_XE_OA_FMT_TYPE_OAM: OAM report format */ 1554 DRM_XE_OA_FMT_TYPE_OAM, 1555 /** @DRM_XE_OA_FMT_TYPE_OAC: OAC report format */ 1556 DRM_XE_OA_FMT_TYPE_OAC, 1557 /** @DRM_XE_OA_FMT_TYPE_OAM_MPEC: OAM SAMEDIA or OAM MPEC report format */ 1558 DRM_XE_OA_FMT_TYPE_OAM_MPEC, 1559 /** @DRM_XE_OA_FMT_TYPE_PEC: PEC report format */ 1560 DRM_XE_OA_FMT_TYPE_PEC, 1561 }; 1562 1563 /** 1564 * enum drm_xe_oa_property_id - OA stream property id's 1565 * 1566 * Stream params are specified as a chain of @drm_xe_ext_set_property 1567 * struct's, with @property values from enum @drm_xe_oa_property_id and 1568 * @drm_xe_user_extension base.name set to @DRM_XE_OA_EXTENSION_SET_PROPERTY. 1569 * @param field in struct @drm_xe_observation_param points to the first 1570 * @drm_xe_ext_set_property struct. 1571 * 1572 * Exactly the same mechanism is also used for stream reconfiguration using the 1573 * @DRM_XE_OBSERVATION_IOCTL_CONFIG observation stream fd ioctl, though only a 1574 * subset of properties below can be specified for stream reconfiguration. 1575 */ 1576 enum drm_xe_oa_property_id { 1577 #define DRM_XE_OA_EXTENSION_SET_PROPERTY 0 1578 /** 1579 * @DRM_XE_OA_PROPERTY_OA_UNIT_ID: ID of the OA unit on which to open 1580 * the OA stream, see @oa_unit_id in 'struct 1581 * drm_xe_query_oa_units'. Defaults to 0 if not provided. 1582 */ 1583 DRM_XE_OA_PROPERTY_OA_UNIT_ID = 1, 1584 1585 /** 1586 * @DRM_XE_OA_PROPERTY_SAMPLE_OA: A value of 1 requests inclusion of raw 1587 * OA unit reports or stream samples in a global buffer attached to an 1588 * OA unit. 1589 */ 1590 DRM_XE_OA_PROPERTY_SAMPLE_OA, 1591 1592 /** 1593 * @DRM_XE_OA_PROPERTY_OA_METRIC_SET: OA metrics defining contents of OA 1594 * reports, previously added via @DRM_XE_OBSERVATION_OP_ADD_CONFIG. 1595 */ 1596 DRM_XE_OA_PROPERTY_OA_METRIC_SET, 1597 1598 /** @DRM_XE_OA_PROPERTY_OA_FORMAT: OA counter report format */ 1599 DRM_XE_OA_PROPERTY_OA_FORMAT, 1600 /* 1601 * OA_FORMAT's are specified the same way as in PRM/Bspec 52198/60942, 1602 * in terms of the following quantities: a. enum @drm_xe_oa_format_type 1603 * b. Counter select c. Counter size and d. BC report. Also refer to the 1604 * oa_formats array in drivers/gpu/drm/xe/xe_oa.c. 1605 */ 1606 #define DRM_XE_OA_FORMAT_MASK_FMT_TYPE (0xffu << 0) 1607 #define DRM_XE_OA_FORMAT_MASK_COUNTER_SEL (0xffu << 8) 1608 #define DRM_XE_OA_FORMAT_MASK_COUNTER_SIZE (0xffu << 16) 1609 #define DRM_XE_OA_FORMAT_MASK_BC_REPORT (0xffu << 24) 1610 1611 /** 1612 * @DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT: Requests periodic OA unit 1613 * sampling with sampling frequency proportional to 2^(period_exponent + 1) 1614 */ 1615 DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, 1616 1617 /** 1618 * @DRM_XE_OA_PROPERTY_OA_DISABLED: A value of 1 will open the OA 1619 * stream in a DISABLED state (see @DRM_XE_OBSERVATION_IOCTL_ENABLE). 1620 */ 1621 DRM_XE_OA_PROPERTY_OA_DISABLED, 1622 1623 /** 1624 * @DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID: Open the stream for a specific 1625 * @exec_queue_id. OA queries can be executed on this exec queue. 1626 */ 1627 DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID, 1628 1629 /** 1630 * @DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE: Optional engine instance to 1631 * pass along with @DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID or will default to 0. 1632 */ 1633 DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, 1634 1635 /** 1636 * @DRM_XE_OA_PROPERTY_NO_PREEMPT: Allow preemption and timeslicing 1637 * to be disabled for the stream exec queue. 1638 */ 1639 DRM_XE_OA_PROPERTY_NO_PREEMPT, 1640 1641 /** 1642 * @DRM_XE_OA_PROPERTY_NUM_SYNCS: Number of syncs in the sync array 1643 * specified in @DRM_XE_OA_PROPERTY_SYNCS 1644 */ 1645 DRM_XE_OA_PROPERTY_NUM_SYNCS, 1646 1647 /** 1648 * @DRM_XE_OA_PROPERTY_SYNCS: Pointer to struct @drm_xe_sync array 1649 * with array size specified via @DRM_XE_OA_PROPERTY_NUM_SYNCS. OA 1650 * configuration will wait till input fences signal. Output fences 1651 * will signal after the new OA configuration takes effect. For 1652 * @DRM_XE_SYNC_TYPE_USER_FENCE, @addr is a user pointer, similar 1653 * to the VM bind case. 1654 */ 1655 DRM_XE_OA_PROPERTY_SYNCS, 1656 1657 /** 1658 * @DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE: Size of OA buffer to be 1659 * allocated by the driver in bytes. Supported sizes are powers of 1660 * 2 from 128 KiB to 128 MiB. When not specified, a 16 MiB OA 1661 * buffer is allocated by default. 1662 */ 1663 DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE, 1664 1665 /** 1666 * @DRM_XE_OA_PROPERTY_WAIT_NUM_REPORTS: Number of reports to wait 1667 * for before unblocking poll or read 1668 */ 1669 DRM_XE_OA_PROPERTY_WAIT_NUM_REPORTS, 1670 }; 1671 1672 /** 1673 * struct drm_xe_oa_config - OA metric configuration 1674 * 1675 * Multiple OA configs can be added using @DRM_XE_OBSERVATION_OP_ADD_CONFIG. A 1676 * particular config can be specified when opening an OA stream using 1677 * @DRM_XE_OA_PROPERTY_OA_METRIC_SET property. 1678 */ 1679 struct drm_xe_oa_config { 1680 /** @extensions: Pointer to the first extension struct, if any */ 1681 __u64 extensions; 1682 1683 /** @uuid: String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x" */ 1684 char uuid[36]; 1685 1686 /** @n_regs: Number of regs in @regs_ptr */ 1687 __u32 n_regs; 1688 1689 /** 1690 * @regs_ptr: Pointer to (register address, value) pairs for OA config 1691 * registers. Expected length of buffer is: (2 * sizeof(u32) * @n_regs). 1692 */ 1693 __u64 regs_ptr; 1694 }; 1695 1696 /** 1697 * struct drm_xe_oa_stream_status - OA stream status returned from 1698 * @DRM_XE_OBSERVATION_IOCTL_STATUS observation stream fd ioctl. Userspace can 1699 * call the ioctl to query stream status in response to EIO errno from 1700 * observation fd read(). 1701 */ 1702 struct drm_xe_oa_stream_status { 1703 /** @extensions: Pointer to the first extension struct, if any */ 1704 __u64 extensions; 1705 1706 /** @oa_status: OA stream status (see Bspec 46717/61226) */ 1707 __u64 oa_status; 1708 #define DRM_XE_OASTATUS_MMIO_TRG_Q_FULL (1 << 3) 1709 #define DRM_XE_OASTATUS_COUNTER_OVERFLOW (1 << 2) 1710 #define DRM_XE_OASTATUS_BUFFER_OVERFLOW (1 << 1) 1711 #define DRM_XE_OASTATUS_REPORT_LOST (1 << 0) 1712 1713 /** @reserved: reserved for future use */ 1714 __u64 reserved[3]; 1715 }; 1716 1717 /** 1718 * struct drm_xe_oa_stream_info - OA stream info returned from 1719 * @DRM_XE_OBSERVATION_IOCTL_INFO observation stream fd ioctl 1720 */ 1721 struct drm_xe_oa_stream_info { 1722 /** @extensions: Pointer to the first extension struct, if any */ 1723 __u64 extensions; 1724 1725 /** @oa_buf_size: OA buffer size */ 1726 __u64 oa_buf_size; 1727 1728 /** @reserved: reserved for future use */ 1729 __u64 reserved[3]; 1730 }; 1731 1732 #if defined(__cplusplus) 1733 } 1734 #endif 1735 1736 #endif /* _XE_DRM_H_ */