nvme.h (85637B) - Raw
1 /** 2 * This file has no copyright assigned and is placed in the Public Domain. 3 * This file is part of the mingw-w64 runtime package. 4 * No warranty is given; refer to the file DISCLAIMER.PD within this package. 5 */ 6 7 #ifndef NVME_INCLUDED 8 #define NVME_INCLUDED 9 10 #include <winapifamily.h> 11 12 #if WINAPI_FAMILY_PARTITION(WINAPI_PARTITION_DESKTOP) 13 14 typedef enum { 15 NVME_AMS_ROUND_ROBIN = 0, 16 NVME_AMS_WEIGHTED_ROUND_ROBIN_URGENT = 1 17 } NVME_AMS_OPTION; 18 19 typedef union { 20 __C89_NAMELESS struct { 21 ULONGLONG MQES : 16; 22 ULONGLONG CQR : 1; 23 ULONGLONG AMS_WeightedRoundRobinWithUrgent : 1; 24 ULONGLONG AMS_VendorSpecific : 1; 25 ULONGLONG Reserved0 : 5; 26 ULONGLONG TO : 8; 27 ULONGLONG DSTRD : 4; 28 ULONGLONG NSSRS : 1; 29 ULONGLONG CSS_NVM : 1; 30 ULONGLONG CSS_Reserved0 : 1; 31 ULONGLONG CSS_Reserved1 : 1; 32 ULONGLONG CSS_Reserved2 : 1; 33 ULONGLONG CSS_Reserved3 : 1; 34 ULONGLONG CSS_Reserved4 : 1; 35 ULONGLONG CSS_MultipleIo : 1; 36 ULONGLONG CSS_AdminOnly : 1; 37 ULONGLONG Reserved2 : 3; 38 ULONGLONG MPSMIN : 4; 39 ULONGLONG MPSMAX : 4; 40 ULONGLONG Reserved3 : 8; 41 }; 42 ULONGLONG AsUlonglong; 43 } NVME_CONTROLLER_CAPABILITIES, *PNVME_CONTROLLER_CAPABILITIES; 44 45 typedef union { 46 __C89_NAMELESS struct { 47 ULONG TER : 8; 48 ULONG MNR : 8; 49 ULONG MJR : 16; 50 }; 51 ULONG AsUlong; 52 } NVME_VERSION, *PNVME_VERSION; 53 54 typedef enum { 55 NVME_CC_SHN_NO_NOTIFICATION = 0, 56 NVME_CC_SHN_NORMAL_SHUTDOWN = 1, 57 NVME_CC_SHN_ABRUPT_SHUTDOWN = 2 58 } NVME_CC_SHN_SHUTDOWN_NOTIFICATIONS; 59 60 typedef enum { 61 NVME_CSS_NVM_COMMAND_SET = 0, 62 NVME_CSS_ALL_SUPPORTED_IO_COMMAND_SET = 6, 63 NVME_CSS_ADMIN_COMMAND_SET_ONLY = 7 64 } NVME_CSS_COMMAND_SETS; 65 66 typedef union { 67 __C89_NAMELESS struct { 68 ULONG EN : 1; 69 ULONG Reserved0 : 3; 70 ULONG CSS : 3; 71 ULONG MPS : 4; 72 ULONG AMS : 3; 73 ULONG SHN : 2; 74 ULONG IOSQES : 4; 75 ULONG IOCQES : 4; 76 ULONG Reserved1 : 8; 77 }; 78 ULONG AsUlong; 79 } NVME_CONTROLLER_CONFIGURATION, *PNVME_CONTROLLER_CONFIGURATION; 80 81 typedef enum { 82 NVME_CSTS_SHST_NO_SHUTDOWN = 0, 83 NVME_CSTS_SHST_SHUTDOWN_IN_PROCESS = 1, 84 NVME_CSTS_SHST_SHUTDOWN_COMPLETED = 2 85 } NVME_CSTS_SHST_SHUTDOWN_STATUS; 86 87 typedef union { 88 __C89_NAMELESS struct { 89 ULONG RDY : 1; 90 ULONG CFS : 1; 91 ULONG SHST : 2; 92 ULONG NSSRO : 1; 93 ULONG PP : 1; 94 ULONG Reserved0 : 26; 95 }; 96 ULONG AsUlong; 97 } NVME_CONTROLLER_STATUS, *PNVME_CONTROLLER_STATUS; 98 99 typedef struct _NVME_NVM_SUBSYSTEM_RESET { 100 ULONG NSSRC; 101 } NVME_NVM_SUBSYSTEM_RESET, *PNVME_NVM_SUBSYSTEM_RESET; 102 103 typedef union { 104 __C89_NAMELESS struct { 105 ULONG ASQS : 12; 106 ULONG Reserved0 : 4; 107 ULONG ACQS : 12; 108 ULONG Reserved1 : 4; 109 }; 110 ULONG AsUlong; 111 } NVME_ADMIN_QUEUE_ATTRIBUTES, *PNVME_ADMIN_QUEUE_ATTRIBUTES; 112 113 typedef union { 114 __C89_NAMELESS struct { 115 ULONGLONG Reserved0 : 12; 116 ULONGLONG ASQB : 52; 117 }; 118 ULONGLONG AsUlonglong; 119 } NVME_ADMIN_SUBMISSION_QUEUE_BASE_ADDRESS, *PNVME_ADMIN_SUBMISSION_QUEUE_BASE_ADDRESS; 120 121 typedef union { 122 __C89_NAMELESS struct { 123 ULONGLONG Reserved0 : 12; 124 ULONGLONG ACQB : 52; 125 }; 126 ULONGLONG AsUlonglong; 127 } NVME_ADMIN_COMPLETION_QUEUE_BASE_ADDRESS, *PNVME_ADMIN_COMPLETION_QUEUE_BASE_ADDRESS; 128 129 typedef union { 130 __C89_NAMELESS struct { 131 ULONG BIR : 3; 132 ULONG Reserved : 9; 133 ULONG OFST : 20; 134 }; 135 ULONG AsUlong; 136 } NVME_CONTROLLER_MEMORY_BUFFER_LOCATION, *PNVME_CONTROLLER_MEMORY_BUFFER_LOCATION; 137 138 typedef enum { 139 NVME_CMBSZ_SIZE_UNITS_4KB = 0, 140 NVME_CMBSZ_SIZE_UNITS_64KB = 1, 141 NVME_CMBSZ_SIZE_UNITS_1MB = 2, 142 NVME_CMBSZ_SIZE_UNITS_16MB = 3, 143 NVME_CMBSZ_SIZE_UNITS_256MB = 4, 144 NVME_CMBSZ_SIZE_UNITS_4GB = 5, 145 NVME_CMBSZ_SIZE_UNITS_64GB = 6 146 } NVME_CMBSZ_SIZE_UNITS; 147 148 typedef union { 149 __C89_NAMELESS struct { 150 ULONG SQS : 1; 151 ULONG CQS : 1; 152 ULONG LISTS : 1; 153 ULONG RDS : 1; 154 ULONG WDS : 1; 155 ULONG Reserved : 3; 156 ULONG SZU : 4; 157 ULONG SZ : 20; 158 }; 159 ULONG AsUlong; 160 } NVME_CONTROLLER_MEMORY_BUFFER_SIZE, *PNVME_CONTROLLER_MEMORY_BUFFER_SIZE; 161 162 typedef union { 163 __C89_NAMELESS struct { 164 ULONG SQT : 16; 165 ULONG Reserved0 : 16; 166 }; 167 ULONG AsUlong; 168 } NVME_SUBMISSION_QUEUE_TAIL_DOORBELL, *PNVME_SUBMISSION_QUEUE_TAIL_DOORBELL; 169 170 typedef union { 171 __C89_NAMELESS struct { 172 ULONG CQH : 16; 173 ULONG Reserved0 : 16; 174 }; 175 ULONG AsUlong; 176 } NVME_COMPLETION_QUEUE_HEAD_DOORBELL, *PNVME_COMPLETION_QUEUE_HEAD_DOORBELL; 177 178 typedef struct { 179 NVME_CONTROLLER_CAPABILITIES CAP; 180 NVME_VERSION VS; 181 ULONG INTMS; 182 ULONG INTMC; 183 NVME_CONTROLLER_CONFIGURATION CC; 184 ULONG Reserved0; 185 NVME_CONTROLLER_STATUS CSTS; 186 NVME_NVM_SUBSYSTEM_RESET NSSR; 187 NVME_ADMIN_QUEUE_ATTRIBUTES AQA; 188 NVME_ADMIN_SUBMISSION_QUEUE_BASE_ADDRESS ASQ; 189 NVME_ADMIN_COMPLETION_QUEUE_BASE_ADDRESS ACQ; 190 NVME_CONTROLLER_MEMORY_BUFFER_LOCATION CMBLOC; 191 NVME_CONTROLLER_MEMORY_BUFFER_SIZE CMBSZ; 192 ULONG Reserved2[944]; 193 ULONG Reserved3[64]; 194 ULONG Doorbells[0]; 195 } NVME_CONTROLLER_REGISTERS, *PNVME_CONTROLLER_REGISTERS; 196 197 typedef union { 198 __C89_NAMELESS struct { 199 USHORT P : 1; 200 USHORT SC : 8; 201 USHORT SCT : 3; 202 USHORT Reserved : 2; 203 USHORT M : 1; 204 USHORT DNR : 1; 205 }; 206 USHORT AsUshort; 207 } NVME_COMMAND_STATUS, *PNVME_COMMAND_STATUS; 208 209 typedef struct { 210 ULONG DW0; 211 ULONG DW1; 212 union { 213 __C89_NAMELESS struct { 214 USHORT SQHD; 215 USHORT SQID; 216 }; 217 ULONG AsUlong; 218 } DW2; 219 union { 220 __C89_NAMELESS struct { 221 USHORT CID; 222 NVME_COMMAND_STATUS Status; 223 }; 224 ULONG AsUlong; 225 } DW3; 226 } NVME_COMPLETION_ENTRY, *PNVME_COMPLETION_ENTRY; 227 228 typedef enum { 229 NVME_ASYNC_EVENT_TYPE_ERROR_STATUS = 0, 230 NVME_ASYNC_EVENT_TYPE_HEALTH_STATUS = 1, 231 NVME_ASYNC_EVENT_TYPE_NOTICE = 2, 232 NVME_ASYNC_EVENT_TYPE_IO_COMMAND_SET_STATUS = 6, 233 NVME_ASYNC_EVENT_TYPE_VENDOR_SPECIFIC = 7 234 } NVME_ASYNC_EVENT_TYPES; 235 236 typedef enum { 237 NVME_ASYNC_ERROR_INVALID_SUBMISSION_QUEUE = 0, 238 NVME_ASYNC_ERROR_INVALID_DOORBELL_WRITE_VALUE = 1, 239 NVME_ASYNC_ERROR_DIAG_FAILURE = 2, 240 NVME_ASYNC_ERROR_PERSISTENT_INTERNAL_DEVICE_ERROR = 3, 241 NVME_ASYNC_ERROR_TRANSIENT_INTERNAL_DEVICE_ERROR = 4, 242 NVME_ASYNC_ERROR_FIRMWARE_IMAGE_LOAD_ERROR = 5 243 } NVME_ASYNC_EVENT_ERROR_STATUS_CODES; 244 245 typedef enum { 246 NVME_ASYNC_HEALTH_NVM_SUBSYSTEM_RELIABILITY = 0, 247 NVME_ASYNC_HEALTH_TEMPERATURE_THRESHOLD = 1, 248 NVME_ASYNC_HEALTH_SPARE_BELOW_THRESHOLD = 2 249 } NVME_ASYNC_EVENT_HEALTH_STATUS_CODES; 250 251 typedef enum { 252 NVME_ASYNC_NOTICE_NAMESPACE_ATTRIBUTE_CHANGED = 0, 253 NVME_ASYNC_NOTICE_FIRMWARE_ACTIVATION_STARTING = 1, 254 NVME_ASYNC_NOTICE_TELEMETRY_LOG_CHANGED = 2, 255 NVME_ASYNC_NOTICE_ASYMMETRIC_ACCESS_CHANGE = 3, 256 NVME_ASYNC_NOTICE_PREDICTABLE_LATENCY_EVENT_AGGREGATE_LOG_CHANGE = 4, 257 NVME_ASYNC_NOTICE_LBA_STATUS_INFORMATION_ALERT = 5, 258 NVME_ASYNC_NOTICE_ENDURANCE_GROUP_EVENT_AGGREGATE_LOG_CHANGE = 6, 259 NVME_ASYNC_NOTICE_ZONE_DESCRIPTOR_CHANGED = 0xEF 260 } NVME_ASYNC_EVENT_NOTICE_CODES; 261 262 typedef enum { 263 NVME_ASYNC_IO_CMD_SET_RESERVATION_LOG_PAGE_AVAILABLE = 0, 264 NVME_ASYNC_IO_CMD_SANITIZE_OPERATION_COMPLETED = 1, 265 NVME_ASYNC_IO_CMD_SANITIZE_OPERATION_COMPLETED_WITH_UNEXPECTED_DEALLOCATION = 2 266 } NVME_ASYNC_EVENT_IO_COMMAND_SET_STATUS_CODES; 267 268 typedef struct { 269 ULONG AsyncEventType : 3; 270 ULONG Reserved0 : 5; 271 ULONG AsyncEventInfo : 8; 272 ULONG LogPage : 8; 273 ULONG Reserved1 : 8; 274 } NVME_COMPLETION_DW0_ASYNC_EVENT_REQUEST, *PNVME_COMPLETION_DW0_ASYNC_EVENT_REQUEST; 275 276 typedef enum { 277 NVME_STATUS_TYPE_GENERIC_COMMAND = 0, 278 NVME_STATUS_TYPE_COMMAND_SPECIFIC = 1, 279 NVME_STATUS_TYPE_MEDIA_ERROR = 2, 280 NVME_STATUS_TYPE_VENDOR_SPECIFIC = 7 281 } NVME_STATUS_TYPES; 282 283 typedef enum { 284 NVME_STATUS_SUCCESS_COMPLETION = 0x00, 285 NVME_STATUS_INVALID_COMMAND_OPCODE = 0x01, 286 NVME_STATUS_INVALID_FIELD_IN_COMMAND = 0x02, 287 NVME_STATUS_COMMAND_ID_CONFLICT = 0x03, 288 NVME_STATUS_DATA_TRANSFER_ERROR = 0x04, 289 NVME_STATUS_COMMAND_ABORTED_DUE_TO_POWER_LOSS_NOTIFICATION = 0x05, 290 NVME_STATUS_INTERNAL_DEVICE_ERROR = 0x06, 291 NVME_STATUS_COMMAND_ABORT_REQUESTED = 0x07, 292 NVME_STATUS_COMMAND_ABORTED_DUE_TO_SQ_DELETION = 0x08, 293 NVME_STATUS_COMMAND_ABORTED_DUE_TO_FAILED_FUSED_COMMAND = 0x09, 294 NVME_STATUS_COMMAND_ABORTED_DUE_TO_FAILED_MISSING_COMMAND = 0x0A, 295 NVME_STATUS_INVALID_NAMESPACE_OR_FORMAT = 0x0B, 296 NVME_STATUS_COMMAND_SEQUENCE_ERROR = 0x0C, 297 NVME_STATUS_INVALID_SGL_LAST_SEGMENT_DESCR = 0x0D, 298 NVME_STATUS_INVALID_NUMBER_OF_SGL_DESCR = 0x0E, 299 NVME_STATUS_DATA_SGL_LENGTH_INVALID = 0x0F, 300 NVME_STATUS_METADATA_SGL_LENGTH_INVALID = 0x10, 301 NVME_STATUS_SGL_DESCR_TYPE_INVALID = 0x11, 302 NVME_STATUS_INVALID_USE_OF_CONTROLLER_MEMORY_BUFFER = 0x12, 303 NVME_STATUS_PRP_OFFSET_INVALID = 0x13, 304 NVME_STATUS_ATOMIC_WRITE_UNIT_EXCEEDED = 0x14, 305 NVME_STATUS_OPERATION_DENIED = 0x15, 306 NVME_STATUS_SGL_OFFSET_INVALID = 0x16, 307 NVME_STATUS_RESERVED = 0x17, 308 NVME_STATUS_HOST_IDENTIFIER_INCONSISTENT_FORMAT = 0x18, 309 NVME_STATUS_KEEP_ALIVE_TIMEOUT_EXPIRED = 0x19, 310 NVME_STATUS_KEEP_ALIVE_TIMEOUT_INVALID = 0x1A, 311 NVME_STATUS_COMMAND_ABORTED_DUE_TO_PREEMPT_ABORT = 0x1B, 312 NVME_STATUS_SANITIZE_FAILED = 0x1C, 313 NVME_STATUS_SANITIZE_IN_PROGRESS = 0x1D, 314 NVME_STATUS_SGL_DATA_BLOCK_GRANULARITY_INVALID = 0x1E, 315 NVME_STATUS_DIRECTIVE_TYPE_INVALID = 0x70, 316 NVME_STATUS_DIRECTIVE_ID_INVALID = 0x71, 317 NVME_STATUS_NVM_LBA_OUT_OF_RANGE = 0x80, 318 NVME_STATUS_NVM_CAPACITY_EXCEEDED = 0x81, 319 NVME_STATUS_NVM_NAMESPACE_NOT_READY = 0x82, 320 NVME_STATUS_NVM_RESERVATION_CONFLICT = 0x83, 321 NVME_STATUS_FORMAT_IN_PROGRESS = 0x84 322 } NVME_STATUS_GENERIC_COMMAND_CODES; 323 324 typedef enum { 325 NVME_STATUS_COMPLETION_QUEUE_INVALID = 0x00, 326 NVME_STATUS_INVALID_QUEUE_IDENTIFIER = 0x01, 327 NVME_STATUS_MAX_QUEUE_SIZE_EXCEEDED = 0x02, 328 NVME_STATUS_ABORT_COMMAND_LIMIT_EXCEEDED = 0x03, 329 NVME_STATUS_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05, 330 NVME_STATUS_INVALID_FIRMWARE_SLOT = 0x06, 331 NVME_STATUS_INVALID_FIRMWARE_IMAGE = 0x07, 332 NVME_STATUS_INVALID_INTERRUPT_VECTOR = 0x08, 333 NVME_STATUS_INVALID_LOG_PAGE = 0x09, 334 NVME_STATUS_INVALID_FORMAT = 0x0A, 335 NVME_STATUS_FIRMWARE_ACTIVATION_REQUIRES_CONVENTIONAL_RESET = 0x0B, 336 NVME_STATUS_INVALID_QUEUE_DELETION = 0x0C, 337 NVME_STATUS_FEATURE_ID_NOT_SAVEABLE = 0x0D, 338 NVME_STATUS_FEATURE_NOT_CHANGEABLE = 0x0E, 339 NVME_STATUS_FEATURE_NOT_NAMESPACE_SPECIFIC = 0x0F, 340 NVME_STATUS_FIRMWARE_ACTIVATION_REQUIRES_NVM_SUBSYSTEM_RESET = 0x10, 341 NVME_STATUS_FIRMWARE_ACTIVATION_REQUIRES_RESET = 0x11, 342 NVME_STATUS_FIRMWARE_ACTIVATION_REQUIRES_MAX_TIME_VIOLATION = 0x12, 343 NVME_STATUS_FIRMWARE_ACTIVATION_PROHIBITED = 0x13, 344 NVME_STATUS_OVERLAPPING_RANGE = 0x14, 345 NVME_STATUS_NAMESPACE_INSUFFICIENT_CAPACITY = 0x15, 346 NVME_STATUS_NAMESPACE_IDENTIFIER_UNAVAILABLE = 0x16, 347 NVME_STATUS_NAMESPACE_ALREADY_ATTACHED = 0x18, 348 NVME_STATUS_NAMESPACE_IS_PRIVATE = 0x19, 349 NVME_STATUS_NAMESPACE_NOT_ATTACHED = 0x1A, 350 NVME_STATUS_NAMESPACE_THIN_PROVISIONING_NOT_SUPPORTED = 0x1B, 351 NVME_STATUS_CONTROLLER_LIST_INVALID = 0x1C, 352 NVME_STATUS_DEVICE_SELF_TEST_IN_PROGRESS = 0x1D, 353 NVME_STATUS_BOOT_PARTITION_WRITE_PROHIBITED = 0x1E, 354 NVME_STATUS_INVALID_CONTROLLER_IDENTIFIER = 0x1F, 355 NVME_STATUS_INVALID_SECONDARY_CONTROLLER_STATE = 0x20, 356 NVME_STATUS_INVALID_NUMBER_OF_CONTROLLER_RESOURCES = 0x21, 357 NVME_STATUS_INVALID_RESOURCE_IDENTIFIER = 0x22, 358 NVME_STATUS_SANITIZE_PROHIBITED_ON_PERSISTENT_MEMORY = 0x23, 359 NVME_STATUS_INVALID_ANA_GROUP_IDENTIFIER = 0x24, 360 NVME_STATUS_ANA_ATTACH_FAILED = 0x25, 361 NVME_IO_COMMAND_SET_NOT_SUPPORTED = 0x29, 362 NVME_IO_COMMAND_SET_NOT_ENABLED = 0x2A, 363 NVME_IO_COMMAND_SET_COMBINATION_REJECTED = 0x2B, 364 NVME_IO_COMMAND_SET_INVALID = 0x2C, 365 NVME_STATUS_STREAM_RESOURCE_ALLOCATION_FAILED = 0x7F, 366 NVME_STATUS_ZONE_INVALID_FORMAT = 0x7F, 367 NVME_STATUS_NVM_CONFLICTING_ATTRIBUTES = 0x80, 368 NVME_STATUS_NVM_INVALID_PROTECTION_INFORMATION = 0x81, 369 NVME_STATUS_NVM_ATTEMPTED_WRITE_TO_READ_ONLY_RANGE = 0x82, 370 NVME_STATUS_NVM_COMMAND_SIZE_LIMIT_EXCEEDED = 0x83, 371 NVME_STATUS_ZONE_BOUNDARY_ERROR = 0xB8, 372 NVME_STATUS_ZONE_FULL = 0xB9, 373 NVME_STATUS_ZONE_READ_ONLY = 0xBA, 374 NVME_STATUS_ZONE_OFFLINE = 0xBB, 375 NVME_STATUS_ZONE_INVALID_WRITE = 0xBC, 376 NVME_STATUS_ZONE_TOO_MANY_ACTIVE = 0xBD, 377 NVME_STATUS_ZONE_TOO_MANY_OPEN = 0xBE, 378 NVME_STATUS_ZONE_INVALID_STATE_TRANSITION = 0xBF 379 } NVME_STATUS_COMMAND_SPECIFIC_CODES; 380 381 typedef enum { 382 NVME_STATUS_NVM_WRITE_FAULT = 0x80, 383 NVME_STATUS_NVM_UNRECOVERED_READ_ERROR = 0x81, 384 NVME_STATUS_NVM_END_TO_END_GUARD_CHECK_ERROR = 0x82, 385 NVME_STATUS_NVM_END_TO_END_APPLICATION_TAG_CHECK_ERROR = 0x83, 386 NVME_STATUS_NVM_END_TO_END_REFERENCE_TAG_CHECK_ERROR = 0x84, 387 NVME_STATUS_NVM_COMPARE_FAILURE = 0x85, 388 NVME_STATUS_NVM_ACCESS_DENIED = 0x86, 389 NVME_STATUS_NVM_DEALLOCATED_OR_UNWRITTEN_LOGICAL_BLOCK = 0x87 390 } NVME_STATUS_MEDIA_ERROR_CODES; 391 392 typedef enum { 393 NVME_ADMIN_COMMAND_DELETE_IO_SQ = 0x00, 394 NVME_ADMIN_COMMAND_CREATE_IO_SQ = 0x01, 395 NVME_ADMIN_COMMAND_GET_LOG_PAGE = 0x02, 396 NVME_ADMIN_COMMAND_DELETE_IO_CQ = 0x04, 397 NVME_ADMIN_COMMAND_CREATE_IO_CQ = 0x05, 398 NVME_ADMIN_COMMAND_IDENTIFY = 0x06, 399 NVME_ADMIN_COMMAND_ABORT = 0x08, 400 NVME_ADMIN_COMMAND_SET_FEATURES = 0x09, 401 NVME_ADMIN_COMMAND_GET_FEATURES = 0x0A, 402 NVME_ADMIN_COMMAND_ASYNC_EVENT_REQUEST = 0x0C, 403 NVME_ADMIN_COMMAND_NAMESPACE_MANAGEMENT = 0x0D, 404 NVME_ADMIN_COMMAND_FIRMWARE_ACTIVATE = 0x10, 405 NVME_ADMIN_COMMAND_FIRMWARE_COMMIT = 0x10, 406 NVME_ADMIN_COMMAND_FIRMWARE_IMAGE_DOWNLOAD = 0x11, 407 NVME_ADMIN_COMMAND_DEVICE_SELF_TEST = 0x14, 408 NVME_ADMIN_COMMAND_NAMESPACE_ATTACHMENT = 0x15, 409 NVME_ADMIN_COMMAND_DIRECTIVE_SEND = 0x19, 410 NVME_ADMIN_COMMAND_DIRECTIVE_RECEIVE = 0x1A, 411 NVME_ADMIN_COMMAND_VIRTUALIZATION_MANAGEMENT = 0x1C, 412 NVME_ADMIN_COMMAND_NVME_MI_SEND = 0x1D, 413 NVME_ADMIN_COMMAND_NVME_MI_RECEIVE = 0x1E, 414 NVME_ADMIN_COMMAND_DOORBELL_BUFFER_CONFIG = 0x7C, 415 NVME_ADMIN_COMMAND_FORMAT_NVM = 0x80, 416 NVME_ADMIN_COMMAND_SECURITY_SEND = 0x81, 417 NVME_ADMIN_COMMAND_SECURITY_RECEIVE = 0x82, 418 NVME_ADMIN_COMMAND_SANITIZE = 0x84, 419 NVME_ADMIN_COMMAND_GET_LBA_STATUS = 0x86 420 } NVME_ADMIN_COMMANDS; 421 422 typedef enum { 423 NVME_FEATURE_ARBITRATION = 0x01, 424 NVME_FEATURE_POWER_MANAGEMENT = 0x02, 425 NVME_FEATURE_LBA_RANGE_TYPE = 0x03, 426 NVME_FEATURE_TEMPERATURE_THRESHOLD = 0x04, 427 NVME_FEATURE_ERROR_RECOVERY = 0x05, 428 NVME_FEATURE_VOLATILE_WRITE_CACHE = 0x06, 429 NVME_FEATURE_NUMBER_OF_QUEUES = 0x07, 430 NVME_FEATURE_INTERRUPT_COALESCING = 0x08, 431 NVME_FEATURE_INTERRUPT_VECTOR_CONFIG = 0x09, 432 NVME_FEATURE_WRITE_ATOMICITY = 0x0A, 433 NVME_FEATURE_ASYNC_EVENT_CONFIG = 0x0B, 434 NVME_FEATURE_AUTONOMOUS_POWER_STATE_TRANSITION = 0x0C, 435 NVME_FEATURE_HOST_MEMORY_BUFFER = 0x0D, 436 NVME_FEATURE_TIMESTAMP = 0x0E, 437 NVME_FEATURE_KEEP_ALIVE = 0x0F, 438 NVME_FEATURE_HOST_CONTROLLED_THERMAL_MANAGEMENT = 0x10, 439 NVME_FEATURE_NONOPERATIONAL_POWER_STATE = 0x11, 440 NVME_FEATURE_READ_RECOVERY_LEVEL_CONFIG = 0x12, 441 NVME_FEATURE_PREDICTABLE_LATENCY_MODE_CONFIG = 0x13, 442 NVME_FEATURE_PREDICTABLE_LATENCY_MODE_WINDOW = 0x14, 443 NVME_FEATURE_LBA_STATUS_INFORMATION_REPORT_INTERVAL = 0x15, 444 NVME_FEATURE_HOST_BEHAVIOR_SUPPORT = 0x16, 445 NVME_FEATURE_SANITIZE_CONFIG = 0x17, 446 NVME_FEATURE_ENDURANCE_GROUP_EVENT_CONFIG = 0x18, 447 NVME_FEATURE_IO_COMMAND_SET_PROFILE = 0x19, 448 NVME_FEATURE_ENHANCED_CONTROLLER_METADATA = 0x7D, 449 NVME_FEATURE_CONTROLLER_METADATA = 0x7E, 450 NVME_FEATURE_NAMESPACE_METADATA = 0x7F, 451 NVME_FEATURE_NVM_SOFTWARE_PROGRESS_MARKER = 0x80, 452 NVME_FEATURE_NVM_HOST_IDENTIFIER = 0x81, 453 NVME_FEATURE_NVM_RESERVATION_NOTIFICATION_MASK = 0x82, 454 NVME_FEATURE_NVM_RESERVATION_PERSISTANCE = 0x83, 455 NVME_FEATURE_NVM_NAMESPACE_WRITE_PROTECTION_CONFIG = 0x84, 456 NVME_FEATURE_ERROR_INJECTION = 0xC0, 457 NVME_FEATURE_CLEAR_FW_UPDATE_HISTORY = 0xC1, 458 NVME_FEATURE_READONLY_WRITETHROUGH_MODE = 0xC2, 459 NVME_FEATURE_CLEAR_PCIE_CORRECTABLE_ERROR_COUNTERS = 0xC3, 460 NVME_FEATURE_ENABLE_IEEE1667_SILO = 0xC4, 461 NVME_FEATURE_PLP_HEALTH_MONITOR = 0xC5 462 } NVME_FEATURES; 463 464 typedef union { 465 __C89_NAMELESS struct { 466 ULONG SQID : 8; 467 ULONG CID : 16; 468 }; 469 ULONG AsUlong; 470 } NVME_CDW10_ABORT, *PNVME_CDW10_ABORT; 471 472 typedef enum { 473 NVME_IDENTIFY_CNS_SPECIFIC_NAMESPACE = 0x0, 474 NVME_IDENTIFY_CNS_CONTROLLER = 0x1, 475 NVME_IDENTIFY_CNS_ACTIVE_NAMESPACES = 0x2, 476 NVME_IDENTIFY_CNS_DESCRIPTOR_NAMESPACE = 0x3, 477 NVME_IDENTIFY_CNS_NVM_SET = 0x4, 478 NVME_IDENTIFY_CNS_SPECIFIC_NAMESPACE_IO_COMMAND_SET = 0x5, 479 NVME_IDENTIFY_CNS_SPECIFIC_CONTROLLER_IO_COMMAND_SET = 0x6, 480 NVME_IDENTIFY_CNS_ACTIVE_NAMESPACE_LIST_IO_COMMAND_SET = 0x7, 481 NVME_IDENTIFY_CNS_ALLOCATED_NAMESPACE_LIST = 0x10, 482 NVME_IDENTIFY_CNS_ALLOCATED_NAMESPACE = 0x11, 483 NVME_IDENTIFY_CNS_CONTROLLER_LIST_OF_NSID = 0x12, 484 NVME_IDENTIFY_CNS_CONTROLLER_LIST_OF_NVM_SUBSYSTEM = 0x13, 485 NVME_IDENTIFY_CNS_PRIMARY_CONTROLLER_CAPABILITIES = 0x14, 486 NVME_IDENTIFY_CNS_SECONDARY_CONTROLLER_LIST = 0x15, 487 NVME_IDENTIFY_CNS_NAMESPACE_GRANULARITY_LIST = 0x16, 488 NVME_IDENTIFY_CNS_UUID_LIST = 0x17, 489 NVME_IDENTIFY_CNS_DOMAIN_LIST = 0x18, 490 NVME_IDENTIFY_CNS_ENDURANCE_GROUP_LIST = 0x19, 491 NVME_IDENTIFY_CNS_ALLOCATED_NAMSPACE_LIST_IO_COMMAND_SET = 0x1A, 492 NVME_IDENTIFY_CNS_ALLOCATED_NAMESPACE_IO_COMMAND_SET = 0x1B, 493 NVME_IDENTIFY_CNS_IO_COMMAND_SET = 0x1C 494 } NVME_IDENTIFY_CNS_CODES; 495 496 typedef enum { 497 NVME_COMMAND_SET_NVM = 0x0, 498 NVME_COMMAND_SET_KEY_VALUE = 0x1, 499 NVME_COMMAND_SET_ZONED_NAMESPACE = 0x2 500 } NVME_COMMAND_SET_IDENTIFIERS; 501 502 typedef union { 503 __C89_NAMELESS struct { 504 ULONG CNS : 8; 505 ULONG Reserved : 8; 506 ULONG CNTID : 16; 507 }; 508 ULONG AsUlong; 509 } NVME_CDW10_IDENTIFY, *PNVME_CDW10_IDENTIFY; 510 511 typedef union { 512 __C89_NAMELESS struct { 513 USHORT NVMSETID; 514 USHORT Reserved; 515 }; 516 __C89_NAMELESS struct { 517 ULONG CNSID : 16; 518 ULONG Reserved2 : 8; 519 ULONG CSI : 8; 520 }; 521 ULONG AsUlong; 522 } NVME_CDW11_IDENTIFY, *PNVME_CDW11_IDENTIFY; 523 524 typedef union { 525 __C89_NAMELESS struct { 526 USHORT MS; 527 UCHAR LBADS; 528 UCHAR RP : 2; 529 UCHAR Reserved0 : 6; 530 }; 531 ULONG AsUlong; 532 } NVME_LBA_FORMAT, *PNVME_LBA_FORMAT; 533 534 typedef union { 535 __C89_NAMELESS struct { 536 UCHAR PersistThroughPowerLoss : 1; 537 UCHAR WriteExclusiveReservation : 1; 538 UCHAR ExclusiveAccessReservation : 1; 539 UCHAR WriteExclusiveRegistrantsOnlyReservation : 1; 540 UCHAR ExclusiveAccessRegistrantsOnlyReservation : 1; 541 UCHAR WriteExclusiveAllRegistrantsReservation : 1; 542 UCHAR ExclusiveAccessAllRegistrantsReservation : 1; 543 UCHAR Reserved : 1; 544 }; 545 UCHAR AsUchar; 546 } NVM_RESERVATION_CAPABILITIES, *PNVME_RESERVATION_CAPABILITIES; 547 548 typedef struct { 549 ULONGLONG NSZE; 550 ULONGLONG NCAP; 551 ULONGLONG NUSE; 552 struct { 553 UCHAR ThinProvisioning : 1; 554 UCHAR NameSpaceAtomicWriteUnit : 1; 555 UCHAR DeallocatedOrUnwrittenError : 1; 556 UCHAR SkipReuseUI : 1; 557 UCHAR NameSpaceIoOptimization : 1; 558 UCHAR Reserved : 3; 559 } NSFEAT; 560 UCHAR NLBAF; 561 struct { 562 UCHAR LbaFormatIndex : 4; 563 UCHAR MetadataInExtendedDataLBA : 1; 564 UCHAR Reserved : 3; 565 } FLBAS; 566 struct { 567 UCHAR MetadataInExtendedDataLBA : 1; 568 UCHAR MetadataInSeparateBuffer : 1; 569 UCHAR Reserved : 6; 570 } MC; 571 struct { 572 UCHAR ProtectionInfoType1 : 1; 573 UCHAR ProtectionInfoType2 : 1; 574 UCHAR ProtectionInfoType3 : 1; 575 UCHAR InfoAtBeginningOfMetadata : 1; 576 UCHAR InfoAtEndOfMetadata : 1; 577 UCHAR Reserved : 3; 578 } DPC; 579 struct { 580 UCHAR ProtectionInfoTypeEnabled : 3; 581 UCHAR InfoAtBeginningOfMetadata : 1; 582 UCHAR Reserved : 4; 583 } DPS; 584 struct { 585 UCHAR SharedNameSpace : 1; 586 UCHAR Reserved : 7; 587 } NMIC; 588 NVM_RESERVATION_CAPABILITIES RESCAP; 589 struct { 590 UCHAR PercentageRemained : 7; 591 UCHAR Supported : 1; 592 } FPI; 593 struct { 594 UCHAR ReadBehavior : 3; 595 UCHAR WriteZeroes : 1; 596 UCHAR GuardFieldWithCRC : 1; 597 UCHAR Reserved : 3; 598 } DLFEAT; 599 USHORT NAWUN; 600 USHORT NAWUPF; 601 USHORT NACWU; 602 USHORT NABSN; 603 USHORT NABO; 604 USHORT NABSPF; 605 USHORT NOIOB; 606 UCHAR NVMCAP[16]; 607 USHORT NPWG; 608 USHORT NPWA; 609 USHORT NPDG; 610 USHORT NPDA; 611 USHORT NOWS; 612 USHORT MSSRL; 613 ULONG MCL; 614 UCHAR MSRC; 615 UCHAR Reserved2[11]; 616 ULONG ANAGRPID; 617 UCHAR Reserved3[3]; 618 struct { 619 UCHAR WriteProtected : 1; 620 UCHAR Reserved : 7; 621 } NSATTR; 622 USHORT NVMSETID; 623 USHORT ENDGID; 624 UCHAR NGUID[16]; 625 UCHAR EUI64[8]; 626 NVME_LBA_FORMAT LBAF[16]; 627 UCHAR Reserved4[192]; 628 UCHAR VS[3712]; 629 } NVME_IDENTIFY_NAMESPACE_DATA, *PNVME_IDENTIFY_NAMESPACE_DATA; 630 631 typedef struct { 632 USHORT MP; 633 UCHAR Reserved0; 634 UCHAR MPS : 1; 635 UCHAR NOPS : 1; 636 UCHAR Reserved1 : 6; 637 ULONG ENLAT; 638 ULONG EXLAT; 639 UCHAR RRT : 5; 640 UCHAR Reserved2 : 3; 641 UCHAR RRL : 5; 642 UCHAR Reserved3 : 3; 643 UCHAR RWT : 5; 644 UCHAR Reserved4 : 3; 645 UCHAR RWL : 5; 646 UCHAR Reserved5 : 3; 647 USHORT IDLP; 648 UCHAR Reserved6 : 6; 649 UCHAR IPS : 2; 650 UCHAR Reserved7; 651 USHORT ACTP; 652 UCHAR APW : 3; 653 UCHAR Reserved8 : 3; 654 UCHAR APS : 2; 655 UCHAR Reserved9[9]; 656 } NVME_POWER_STATE_DESC, *PNVME_POWER_STATE_DESC; 657 658 typedef struct { 659 USHORT VID; 660 USHORT SSVID; 661 UCHAR SN[20]; 662 UCHAR MN[40]; 663 UCHAR FR[8]; 664 UCHAR RAB; 665 UCHAR IEEE[3]; 666 struct { 667 UCHAR MultiPCIePorts : 1; 668 UCHAR MultiControllers : 1; 669 UCHAR SRIOV : 1; 670 UCHAR Reserved : 5; 671 } CMIC; 672 UCHAR MDTS; 673 USHORT CNTLID; 674 ULONG VER; 675 ULONG RTD3R; 676 ULONG RTD3E; 677 struct { 678 ULONG Reserved0 : 8; 679 ULONG NamespaceAttributeChanged : 1; 680 ULONG FirmwareActivation : 1; 681 ULONG Reserved1 : 1; 682 ULONG AsymmetricAccessChanged : 1; 683 ULONG PredictableLatencyAggregateLogChanged : 1; 684 ULONG LbaStatusChanged : 1; 685 ULONG EnduranceGroupAggregateLogChanged : 1; 686 ULONG Reserved2 : 12; 687 ULONG ZoneInformation : 1; 688 ULONG Reserved3 : 4; 689 } OAES; 690 struct { 691 ULONG HostIdentifier128Bit : 1; 692 ULONG NOPSPMode : 1; 693 ULONG NVMSets : 1; 694 ULONG ReadRecoveryLevels : 1; 695 ULONG EnduranceGroups : 1; 696 ULONG PredictableLatencyMode : 1; 697 ULONG TBKAS : 1; 698 ULONG NamespaceGranularity : 1; 699 ULONG SQAssociations : 1; 700 ULONG UUIDList : 1; 701 ULONG Reserved0 : 22; 702 } CTRATT; 703 struct { 704 USHORT ReadRecoveryLevel0 : 1; 705 USHORT ReadRecoveryLevel1 : 1; 706 USHORT ReadRecoveryLevel2 : 1; 707 USHORT ReadRecoveryLevel3 : 1; 708 USHORT ReadRecoveryLevel4 : 1; 709 USHORT ReadRecoveryLevel5 : 1; 710 USHORT ReadRecoveryLevel6 : 1; 711 USHORT ReadRecoveryLevel7 : 1; 712 USHORT ReadRecoveryLevel8 : 1; 713 USHORT ReadRecoveryLevel9 : 1; 714 USHORT ReadRecoveryLevel10 : 1; 715 USHORT ReadRecoveryLevel11 : 1; 716 USHORT ReadRecoveryLevel12 : 1; 717 USHORT ReadRecoveryLevel13 : 1; 718 USHORT ReadRecoveryLevel14 : 1; 719 USHORT ReadRecoveryLevel15 : 1; 720 } RRLS; 721 UCHAR Reserved0[9]; 722 UCHAR CNTRLTYPE; 723 UCHAR FGUID[16]; 724 USHORT CRDT1; 725 USHORT CRDT2; 726 USHORT CRDT3; 727 UCHAR Reserved0_1[106]; 728 UCHAR ReservedForManagement[16]; 729 struct { 730 USHORT SecurityCommands : 1; 731 USHORT FormatNVM : 1; 732 USHORT FirmwareCommands : 1; 733 USHORT NamespaceCommands : 1; 734 USHORT DeviceSelfTest : 1; 735 USHORT Directives : 1; 736 USHORT NVMeMICommands : 1; 737 USHORT VirtualizationMgmt : 1; 738 USHORT DoorBellBufferConfig: 1; 739 USHORT GetLBAStatus : 1; 740 USHORT Reserved : 6; 741 } OACS; 742 UCHAR ACL; 743 UCHAR AERL; 744 struct { 745 UCHAR Slot1ReadOnly : 1; 746 UCHAR SlotCount : 3; 747 UCHAR ActivationWithoutReset : 1; 748 UCHAR Reserved : 3; 749 } FRMW; 750 struct { 751 UCHAR SmartPagePerNamespace : 1; 752 UCHAR CommandEffectsLog : 1; 753 UCHAR LogPageExtendedData : 1; 754 UCHAR TelemetrySupport : 1; 755 UCHAR PersistentEventLog : 1; 756 UCHAR Reserved0 : 1; 757 UCHAR TelemetryDataArea4 : 1; 758 UCHAR Reserved1 : 1; 759 } LPA; 760 UCHAR ELPE; 761 UCHAR NPSS; 762 struct { 763 UCHAR CommandFormatInSpec : 1; 764 UCHAR Reserved : 7; 765 } AVSCC; 766 struct { 767 UCHAR Supported : 1; 768 UCHAR Reserved : 7; 769 } APSTA; 770 USHORT WCTEMP; 771 USHORT CCTEMP; 772 USHORT MTFA; 773 ULONG HMPRE; 774 ULONG HMMIN; 775 UCHAR TNVMCAP[16]; 776 UCHAR UNVMCAP[16]; 777 struct { 778 ULONG RPMBUnitCount : 3; 779 ULONG AuthenticationMethod : 3; 780 ULONG Reserved0 : 10; 781 ULONG TotalSize : 8; 782 ULONG AccessSize : 8; 783 } RPMBS; 784 USHORT EDSTT; 785 UCHAR DSTO; 786 UCHAR FWUG; 787 USHORT KAS; 788 struct { 789 USHORT Supported : 1; 790 USHORT Reserved : 15; 791 } HCTMA; 792 USHORT MNTMT; 793 USHORT MXTMT; 794 struct { 795 ULONG CryptoErase : 1; 796 ULONG BlockErase : 1; 797 ULONG Overwrite : 1; 798 ULONG Reserved : 26; 799 ULONG NDI : 1; 800 ULONG NODMMAS : 2; 801 } SANICAP; 802 ULONG HMMINDS; 803 USHORT HMMAXD; 804 USHORT NSETIDMAX; 805 USHORT ENDGIDMAX; 806 UCHAR ANATT; 807 struct { 808 UCHAR OptimizedState : 1; 809 UCHAR NonOptimizedState : 1; 810 UCHAR InaccessibleState : 1; 811 UCHAR PersistentLossState : 1; 812 UCHAR ChangeState : 1; 813 UCHAR Reserved : 1; 814 UCHAR StaticANAGRPID : 1; 815 UCHAR SupportNonZeroANAGRPID : 1; 816 } ANACAP; 817 ULONG ANAGRPMAX; 818 ULONG NANAGRPID; 819 ULONG PELS; 820 UCHAR Reserved1[156]; 821 struct { 822 UCHAR RequiredEntrySize : 4; 823 UCHAR MaxEntrySize : 4; 824 } SQES; 825 struct { 826 UCHAR RequiredEntrySize : 4; 827 UCHAR MaxEntrySize : 4; 828 } CQES; 829 USHORT MAXCMD; 830 ULONG NN; 831 struct { 832 USHORT Compare : 1; 833 USHORT WriteUncorrectable : 1; 834 USHORT DatasetManagement : 1; 835 USHORT WriteZeroes : 1; 836 USHORT FeatureField : 1; 837 USHORT Reservations : 1; 838 USHORT Timestamp : 1; 839 USHORT Verify : 1; 840 USHORT Reserved : 8; 841 } ONCS; 842 struct { 843 USHORT CompareAndWrite : 1; 844 USHORT Reserved : 15; 845 } FUSES; 846 struct { 847 UCHAR FormatApplyToAll : 1; 848 UCHAR SecureEraseApplyToAll : 1; 849 UCHAR CryptographicEraseSupported : 1; 850 UCHAR FormatSupportNSIDAllF : 1; 851 UCHAR Reserved : 4; 852 } FNA; 853 struct { 854 UCHAR Present : 1; 855 UCHAR FlushBehavior : 2; 856 UCHAR Reserved : 5; 857 } VWC; 858 USHORT AWUN; 859 USHORT AWUPF; 860 struct { 861 UCHAR CommandFormatInSpec : 1; 862 UCHAR Reserved : 7; 863 } NVSCC; 864 struct { 865 UCHAR WriteProtect : 1; 866 UCHAR UntilPowerCycle : 1; 867 UCHAR Permanent : 1; 868 UCHAR Reserved : 5; 869 } NWPC; 870 USHORT ACWU; 871 UCHAR Reserved4[2]; 872 struct { 873 ULONG SGLSupported : 2; 874 ULONG KeyedSGLData : 1; 875 ULONG Reserved0 : 13; 876 ULONG BitBucketDescrSupported : 1; 877 ULONG ByteAlignedContiguousPhysicalBuffer : 1; 878 ULONG SGLLengthLargerThanDataLength : 1; 879 ULONG MPTRSGLDescriptor : 1; 880 ULONG AddressFieldSGLDataBlock: 1; 881 ULONG TransportSGLData : 1; 882 ULONG Reserved1 : 10; 883 } SGLS; 884 ULONG MNAN; 885 UCHAR Reserved6[224]; 886 UCHAR SUBNQN[256]; 887 UCHAR Reserved7[768]; 888 UCHAR Reserved8[256]; 889 NVME_POWER_STATE_DESC PDS[32]; 890 UCHAR VS[1024]; 891 } NVME_IDENTIFY_CONTROLLER_DATA, *PNVME_IDENTIFY_CONTROLLER_DATA; 892 893 typedef enum { 894 NVME_IDENTIFIER_TYPE_EUI64 = 0x1, 895 NVME_IDENTIFIER_TYPE_NGUID = 0x2, 896 NVME_IDENTIFIER_TYPE_UUID = 0x3, 897 NVME_IDENTIFIER_TYPE_CSI = 0x4 898 } NVME_IDENTIFIER_TYPE; 899 900 typedef enum { 901 NVME_IDENTIFIER_TYPE_EUI64_LENGTH = 0x8, 902 NVME_IDENTIFIER_TYPE_NGUID_LENGTH = 0x10, 903 NVME_IDENTIFIER_TYPE_UUID_LENGTH = 0x10, 904 NVME_IDENTIFIER_TYPE_CSI_LENGTH = 0x1 905 } NVME_IDENTIFIER_TYPE_LENGTH; 906 907 #define NVME_IDENTIFY_CNS_DESCRIPTOR_NAMESPACE_SIZE 0x1000 908 909 typedef struct { 910 UCHAR NIDT; 911 UCHAR NIDL; 912 UCHAR Reserved[2]; 913 UCHAR NID[ANYSIZE_ARRAY]; 914 } NVME_IDENTIFY_NAMESPACE_DESCRIPTOR, *PNVME_IDENTIFY_NAMESPACE_DESCRIPTOR; 915 916 typedef struct { 917 USHORT Identifier; 918 USHORT ENDGID; 919 ULONG Reserved1; 920 ULONG Random4KBReadTypical; 921 ULONG OptimalWriteSize; 922 UCHAR TotalCapacity[16]; 923 UCHAR UnallocatedCapacity[16]; 924 UCHAR Reserved2[80]; 925 } NVME_SET_ATTRIBUTES_ENTRY, *PNVME_SET_ATTRIBUTES_ENTRY; 926 927 typedef struct { 928 UCHAR IdentifierCount; 929 UCHAR Reserved[127]; 930 NVME_SET_ATTRIBUTES_ENTRY Entry[ANYSIZE_ARRAY]; 931 } NVM_SET_LIST, *PNVM_SET_LIST; 932 933 typedef struct { 934 ULONGLONG ZoneSize; 935 UCHAR ZDES; 936 UCHAR Reserved[7]; 937 } NVME_LBA_ZONE_FORMAT, *PNVME_LBA_ZONE_FORMAT; 938 939 typedef struct { 940 struct { 941 USHORT VariableZoneCapacity : 1; 942 USHORT ZoneExcursions : 1; 943 USHORT Reserved : 14; 944 } ZOC; 945 struct { 946 USHORT ReadAcrossZoneBoundaries : 1; 947 USHORT Reserved : 15; 948 } OZCS; 949 ULONG MAR; 950 ULONG MOR; 951 ULONG RRL; 952 ULONG FRL; 953 UCHAR Reserved0[2796]; 954 NVME_LBA_ZONE_FORMAT LBAEF[16]; 955 UCHAR Reserved1[768]; 956 UCHAR VS[256]; 957 } NVME_IDENTIFY_SPECIFIC_NAMESPACE_IO_COMMAND_SET, *PNVME_IDENTIFY_SPECIFIC_NAMESPACE_IO_COMMAND_SET; 958 959 typedef struct { 960 UCHAR VSL; 961 UCHAR WZSL; 962 UCHAR WUSL; 963 UCHAR DMRL; 964 ULONG DMRSL; 965 ULONGLONG DMSL; 966 UCHAR Reserved[4080]; 967 } NVME_IDENTIFY_NVM_SPECIFIC_CONTROLLER_IO_COMMAND_SET, *PNVME_IDENTIFY_NVM_SPECIFIC_CONTROLLER_IO_COMMAND_SET; 968 969 typedef struct { 970 UCHAR ZASL; 971 UCHAR Reserved[4095]; 972 } NVME_IDENTIFY_ZNS_SPECIFIC_CONTROLLER_IO_COMMAND_SET, *PNVME_IDENTIFY_ZNS_SPECIFIC_CONTROLLER_IO_COMMAND_SET; 973 974 typedef struct { 975 USHORT NumberOfIdentifiers; 976 USHORT ControllerID[2047]; 977 } NVME_CONTROLLER_LIST, *PNVME_CONTROLLER_LIST; 978 979 typedef struct { 980 ULONGLONG IOCommandSetVector[512]; 981 } NVME_IDENTIFY_IO_COMMAND_SET, *PNVME_IDENTIFY_IO_COMMAND_SET; 982 983 typedef enum { 984 NVME_LBA_RANGE_TYPE_RESERVED = 0, 985 NVME_LBA_RANGE_TYPE_FILESYSTEM = 1, 986 NVME_LBA_RANGE_TYPE_RAID = 2, 987 NVME_LBA_RANGE_TYPE_CACHE = 3, 988 NVME_LBA_RANGE_TYPE_PAGE_SWAP_FILE = 4 989 } NVME_LBA_RANGE_TYPES; 990 991 typedef struct { 992 UCHAR Type; 993 struct { 994 UCHAR MayOverwritten : 1; 995 UCHAR Hidden : 1; 996 UCHAR Reserved : 6; 997 } Attributes; 998 UCHAR Reserved0[14]; 999 ULONGLONG SLBA; 1000 ULONGLONG NLB; 1001 UCHAR GUID[16]; 1002 UCHAR Reserved1[16]; 1003 } NVME_LBA_RANGET_TYPE_ENTRY, *PNVME_LBA_RANGET_TYPE_ENTRY; 1004 1005 typedef enum { 1006 NVME_LOG_PAGE_WCS_DEVICE_SMART_ATTRIBUTES = 0xC0, 1007 NVME_LOG_PAGE_WCS_DEVICE_ERROR_RECOVERY = 0xC1 1008 } NVME_VENDOR_LOG_PAGES; 1009 1010 #define GUID_WCS_DEVICE_SMART_ATTRIBUTESGuid { 0x2810AFC5, 0xBFEA, 0xA4F2, { 0x9C, 0x4F, 0x6F, 0x7C, 0xC9, 0x14, 0xD5, 0xAF} } 1011 DEFINE_GUID(GUID_WCS_DEVICE_SMART_ATTRIBUTES, 0x2810AFC5, 0xBFEA, 0xA4F2, 0x9C, 0x4F, 0x6F, 0x7C, 0xC9, 0x14, 0xD5, 0xAF); 1012 1013 #define GUID_WCS_DEVICE_ERROR_RECOVERYGuid { 0x2131D944, 0x30FE, 0xAE34, {0xAB, 0x4D, 0xFD, 0x3D, 0xBA, 0x83, 0x19, 0x5A} } 1014 DEFINE_GUID(GUID_WCS_DEVICE_ERROR_RECOVERY, 0x2131D944, 0x30FE, 0xAE34, 0xAB, 0x4D, 0xFD, 0x3D, 0xBA, 0x83, 0x19, 0x5A); 1015 1016 typedef enum { 1017 NVME_ASYNC_EVENT_TYPE_VENDOR_SPECIFIC_RESERVED = 0, 1018 NVME_ASYNC_EVENT_TYPE_VENDOR_SPECIFIC_DEVICE_PANIC = 1 1019 } NVME_ASYNC_EVENT_TYPE_VENDOR_SPECIFIC_CODES; 1020 1021 typedef struct _NVME_WCS_DEVICE_RESET_ACTION { 1022 union { 1023 __C89_NAMELESS struct { 1024 UCHAR ControllerReset : 1; 1025 UCHAR NVMeSubsystemReset : 1; 1026 UCHAR PCIeFLR : 1; 1027 UCHAR PERST : 1; 1028 UCHAR PowerCycle : 1; 1029 UCHAR PCIeConventionalHotReset : 1; 1030 UCHAR Reserved : 2; 1031 }; 1032 UCHAR AsUCHAR; 1033 }; 1034 } NVME_WCS_DEVICE_RESET_ACTION, *PNVME_WCS_DEVICE_RESET_ACTION; 1035 1036 typedef struct _NVME_WCS_DEVICE_CAPABILITIES { 1037 union { 1038 __C89_NAMELESS struct { 1039 ULONG PanicAEN : 1; 1040 ULONG PanicCFS : 1; 1041 ULONG Reserved : 30; 1042 }; 1043 ULONG AsULONG; 1044 }; 1045 } NVME_WCS_DEVICE_CAPABILITIES, *PNVME_WCS_DEVICE_CAPABILITIES; 1046 1047 typedef enum _NVME_WCS_DEVICE_RECOVERY_ACTION { 1048 NVMeDeviceRecoveryNoAction = 0, 1049 NVMeDeviceRecoveryFormatNVM, 1050 NVMeDeviceRecoveryVendorSpecificCommand, 1051 NVMeDeviceRecoveryVendorAnalysis, 1052 NVMeDeviceRecoveryDeviceReplacement, 1053 NVMeDeviceRecoverySanitize, 1054 NVMeDeviceRecoveryMax = 15 1055 } NVME_WCS_DEVICE_RECOVERY_ACTION, *PNVME_WCS_DEVICE_RECOVERY_ACTION; 1056 1057 #pragma pack(push, 1) 1058 1059 typedef struct _NVME_WCS_DEVICE_SMART_ATTRIBUTES_LOG { 1060 UCHAR VersionSpecificData[494]; 1061 USHORT LogPageVersionNumber; 1062 GUID LogPageGUID; 1063 } NVME_WCS_DEVICE_SMART_ATTRIBUTES_LOG, *PNVME_WCS_DEVICE_SMART_ATTRIBUTES_LOG; 1064 1065 C_ASSERT(sizeof(NVME_WCS_DEVICE_SMART_ATTRIBUTES_LOG) == 512); 1066 1067 #define NVME_WCS_DEVICE_SMART_ATTRIBUTES_LOG_VERSION_2 0x0002 1068 1069 typedef struct _NVME_WCS_DEVICE_SMART_ATTRIBUTES_LOG_V2 { 1070 UCHAR MediaUnitsWritten[16]; 1071 UCHAR MediaUnitsRead[16]; 1072 struct { 1073 UCHAR RawCount[6]; 1074 UCHAR Normalized[2]; 1075 } BadUserNANDBlockCount; 1076 struct { 1077 UCHAR RawCount[6]; 1078 UCHAR Normalized[2]; 1079 } BadSystemNANDBlockCount; 1080 ULONGLONG XORRecoveryCount; 1081 ULONGLONG UnrecoverableReadErrorCount; 1082 ULONGLONG SoftECCErrorCount; 1083 struct { 1084 ULONG DetectedCounts; 1085 ULONG CorrectedCounts; 1086 } EndToEndCorrectionCounts; 1087 UCHAR PercentageSystemDataUsed; 1088 UCHAR RefreshCount[7]; 1089 struct { 1090 ULONG MaximumCount; 1091 ULONG MinimumCount; 1092 } UserDataEraseCounts; 1093 struct { 1094 UCHAR EventCount; 1095 UCHAR Status; 1096 } ThermalThrottling; 1097 UCHAR Reserved0[6]; 1098 ULONGLONG PCIeCorrectableErrorCount; 1099 ULONG IncompleteShutdownCount; 1100 ULONG Reserved1; 1101 UCHAR PercentageFreeBlocks; 1102 UCHAR Reserved2[7]; 1103 USHORT CapacitorHealth; 1104 UCHAR Reserved3[6]; 1105 ULONGLONG UnalignedIOCount; 1106 ULONGLONG SecurityVersionNumber; 1107 ULONGLONG NUSE; 1108 UCHAR PLPStartCount[16]; 1109 UCHAR EnduranceEstimate[16]; 1110 UCHAR Reserved4[302]; 1111 USHORT LogPageVersionNumber; 1112 GUID LogPageGUID; 1113 } NVME_WCS_DEVICE_SMART_ATTRIBUTES_LOG_V2, *PNVME_WCS_DEVICE_SMART_ATTRIBUTES_LOG_V2; 1114 1115 C_ASSERT(sizeof(NVME_WCS_DEVICE_SMART_ATTRIBUTES_LOG_V2) == sizeof(NVME_WCS_DEVICE_SMART_ATTRIBUTES_LOG)); 1116 1117 typedef struct _NVME_WCS_DEVICE_ERROR_RECOVERY_LOG { 1118 USHORT PanicResetWaitTime; 1119 NVME_WCS_DEVICE_RESET_ACTION PanicResetAction; 1120 UCHAR DriveRecoveryAction; 1121 ULONGLONG PanicId; 1122 NVME_WCS_DEVICE_CAPABILITIES DeviceCapabilities; 1123 UCHAR VendorSpecificRecoveryCode; 1124 UCHAR Reserved0[3]; 1125 ULONG VendorSpecificCommandCDW12; 1126 ULONG VendorSpecificCommandCDW13; 1127 UCHAR Reserved1[466]; 1128 USHORT LogPageVersionNumber; 1129 GUID LogPageGUID; 1130 } NVME_WCS_DEVICE_ERROR_RECOVERY_LOG, *PNVME_WCS_DEVICE_ERROR_RECOVERY_LOG; 1131 1132 C_ASSERT(sizeof(NVME_WCS_DEVICE_ERROR_RECOVERY_LOG) == 512); 1133 1134 #pragma pack(pop) 1135 1136 typedef union { 1137 __C89_NAMELESS struct { 1138 ULONG QID : 16; 1139 ULONG QSIZE : 16; 1140 }; 1141 ULONG AsUlong; 1142 } NVME_CDW10_CREATE_IO_QUEUE, *PNVME_CDW10_CREATE_IO_QUEUE; 1143 1144 typedef union { 1145 __C89_NAMELESS struct { 1146 ULONG PC : 1; 1147 ULONG IEN : 1; 1148 ULONG Reserved0 : 14; 1149 ULONG IV : 16; 1150 }; 1151 ULONG AsUlong; 1152 } NVME_CDW11_CREATE_IO_CQ, *PNVME_CDW11_CREATE_IO_CQ; 1153 1154 typedef enum { 1155 NVME_NVM_QUEUE_PRIORITY_URGENT = 0, 1156 NVME_NVM_QUEUE_PRIORITY_HIGH = 1, 1157 NVME_NVM_QUEUE_PRIORITY_MEDIUM = 2, 1158 NVME_NVM_QUEUE_PRIORITY_LOW = 3 1159 } NVME_NVM_QUEUE_PRIORITIES; 1160 1161 typedef union { 1162 __C89_NAMELESS struct { 1163 ULONG PC : 1; 1164 ULONG QPRIO : 2; 1165 ULONG Reserved0 : 13; 1166 ULONG CQID : 16; 1167 }; 1168 ULONG AsUlong; 1169 } NVME_CDW11_CREATE_IO_SQ, *PNVME_CDW11_CREATE_IO_SQ; 1170 1171 typedef enum { 1172 NVME_FEATURE_VALUE_CURRENT = 0, 1173 NVME_FEATURE_VALUE_DEFAULT = 1, 1174 NVME_FEATURE_VALUE_SAVED = 2, 1175 NVME_FEATURE_VALUE_SUPPORTED_CAPABILITIES = 3 1176 } NVME_FEATURE_VALUE_CODES; 1177 1178 typedef union { 1179 __C89_NAMELESS struct { 1180 ULONG FID : 8; 1181 ULONG SEL : 3; 1182 ULONG Reserved0 : 21; 1183 }; 1184 ULONG AsUlong; 1185 } NVME_CDW10_GET_FEATURES, *PNVME_CDW10_GET_FEATURES; 1186 1187 typedef union { 1188 __C89_NAMELESS struct { 1189 ULONG FID : 8; 1190 ULONG Reserved0 : 23; 1191 ULONG SV : 1; 1192 }; 1193 ULONG AsUlong; 1194 } NVME_CDW10_SET_FEATURES, *PNVME_CDW10_SET_FEATURES; 1195 1196 typedef union { 1197 __C89_NAMELESS struct { 1198 ULONG NSQ : 16; 1199 ULONG NCQ : 16; 1200 }; 1201 ULONG AsUlong; 1202 } NVME_CDW11_FEATURE_NUMBER_OF_QUEUES, *PNVME_CDW11_FEATURE_NUMBER_OF_QUEUES; 1203 1204 typedef union { 1205 __C89_NAMELESS struct { 1206 ULONG THR : 8; 1207 ULONG TIME : 8; 1208 ULONG Reserved0 : 16; 1209 }; 1210 ULONG AsUlong; 1211 } NVME_CDW11_FEATURE_INTERRUPT_COALESCING, *PNVME_CDW11_FEATURE_INTERRUPT_COALESCING; 1212 1213 typedef union { 1214 __C89_NAMELESS struct { 1215 ULONG IV : 16; 1216 ULONG CD : 1; 1217 ULONG Reserved0 : 15; 1218 }; 1219 ULONG AsUlong; 1220 } NVME_CDW11_FEATURE_INTERRUPT_VECTOR_CONFIG, *PNVME_CDW11_FEATURE_INTERRUPT_VECTOR_CONFIG; 1221 1222 typedef union { 1223 __C89_NAMELESS struct { 1224 ULONG DN : 1; 1225 ULONG Reserved0 : 31; 1226 }; 1227 ULONG AsUlong; 1228 } NVME_CDW11_FEATURE_WRITE_ATOMICITY_NORMAL, *PNVME_CDW11_FEATURE_WRITE_ATOMICITY_NORMAL; 1229 1230 typedef union { 1231 __C89_NAMELESS struct { 1232 ULONG NOPPME : 1; 1233 ULONG Reserved0 : 31; 1234 }; 1235 ULONG AsUlong; 1236 } NVME_CDW11_FEATURE_NON_OPERATIONAL_POWER_STATE, *PNVME_CDW11_FEATURE_NON_OPERATIONAL_POWER_STATE; 1237 1238 typedef union { 1239 __C89_NAMELESS struct { 1240 ULONG NUM : 6; 1241 ULONG Reserved0 : 26; 1242 }; 1243 ULONG AsUlong; 1244 } NVME_CDW11_FEATURE_LBA_RANGE_TYPE, *PNVME_CDW11_FEATURE_LBA_RANGE_TYPE; 1245 1246 typedef union { 1247 __C89_NAMELESS struct { 1248 ULONG AB : 3; 1249 ULONG Reserved0 : 5; 1250 ULONG LPW : 8; 1251 ULONG MPW : 8; 1252 ULONG HPW : 8; 1253 }; 1254 ULONG AsUlong; 1255 } NVME_CDW11_FEATURE_ARBITRATION, *PNVME_CDW11_FEATURE_ARBITRATION; 1256 1257 typedef union { 1258 __C89_NAMELESS struct { 1259 ULONG WCE : 1; 1260 ULONG Reserved0 : 31; 1261 }; 1262 ULONG AsUlong; 1263 } NVME_CDW11_FEATURE_VOLATILE_WRITE_CACHE, *PNVME_CDW11_FEATURE_VOLATILE_WRITE_CACHE; 1264 1265 typedef union { 1266 __C89_NAMELESS struct { 1267 ULONG SAVE : 1; 1268 ULONG NSS : 1; 1269 ULONG MOD : 1; 1270 ULONG Reserved0 : 29; 1271 }; 1272 ULONG AsUlong; 1273 } NVME_CDW11_FEATURE_SUPPORTED_CAPABILITY, *PNVME_CDW11_FEATURE_SUPPORTED_CAPABILITY; 1274 1275 typedef union { 1276 __C89_NAMELESS struct { 1277 ULONG CriticalWarnings : 8; 1278 ULONG NsAttributeNotices : 1; 1279 ULONG FwActivationNotices : 1; 1280 ULONG TelemetryLogNotices : 1; 1281 ULONG ANAChangeNotices : 1; 1282 ULONG PredictableLogChangeNotices : 1; 1283 ULONG LBAStatusNotices : 1; 1284 ULONG EnduranceEventNotices : 1; 1285 ULONG Reserved0 : 12; 1286 ULONG ZoneDescriptorNotices : 1; 1287 ULONG Reserved1 : 4; 1288 }; 1289 ULONG AsUlong; 1290 } NVME_CDW11_FEATURE_ASYNC_EVENT_CONFIG, *PNVME_CDW11_FEATURE_ASYNC_EVENT_CONFIG; 1291 1292 typedef union { 1293 __C89_NAMELESS struct { 1294 ULONG PS : 5; 1295 ULONG Reserved0 : 27; 1296 }; 1297 ULONG AsUlong; 1298 } NVME_CDW11_FEATURE_POWER_MANAGEMENT, *PNVME_CDW11_FEATURE_POWER_MANAGEMENT; 1299 1300 typedef union { 1301 __C89_NAMELESS struct { 1302 ULONG APSTE : 1; 1303 ULONG Reserved0 : 31; 1304 }; 1305 ULONG AsUlong; 1306 } NVME_CDW11_FEATURE_AUTO_POWER_STATE_TRANSITION, *PNVME_CDW11_FEATURE_AUTO_POWER_STATE_TRANSITION; 1307 1308 typedef struct { 1309 ULONG Reserved0 : 3; 1310 ULONG IdleTransitionPowerState : 5; 1311 ULONG IdleTimePriorToTransition : 24; 1312 ULONG Reserved1; 1313 } NVME_AUTO_POWER_STATE_TRANSITION_ENTRY, *PNVME_AUTO_POWER_STATE_TRANSITION_ENTRY; 1314 1315 typedef enum { 1316 NVME_TEMPERATURE_OVER_THRESHOLD = 0, 1317 NVME_TEMPERATURE_UNDER_THRESHOLD = 1 1318 } NVME_TEMPERATURE_THRESHOLD_TYPES; 1319 1320 typedef union { 1321 __C89_NAMELESS struct { 1322 ULONG TMPTH : 16; 1323 ULONG TMPSEL : 4; 1324 ULONG THSEL : 2; 1325 ULONG Reserved0 : 10; 1326 }; 1327 ULONG AsUlong; 1328 } NVME_CDW11_FEATURE_TEMPERATURE_THRESHOLD, *PNVME_CDW11_FEATURE_TEMPERATURE_THRESHOLD; 1329 1330 typedef union { 1331 __C89_NAMELESS struct { 1332 ULONG TLER : 16; 1333 ULONG DULBE : 1; 1334 ULONG Reserved0 : 15; 1335 }; 1336 ULONG AsUlong; 1337 } NVME_CDW11_FEATURE_ERROR_RECOVERY, *PNVME_CDW11_FEATURE_ERROR_RECOVERY; 1338 1339 typedef union { 1340 __C89_NAMELESS struct { 1341 ULONG EHM : 1; 1342 ULONG MR : 1; 1343 ULONG Reserved : 30; 1344 }; 1345 ULONG AsUlong; 1346 } NVME_CDW11_FEATURE_HOST_MEMORY_BUFFER, *PNVME_CDW11_FEATURE_HOST_MEMORY_BUFFER; 1347 1348 typedef union { 1349 __C89_NAMELESS struct { 1350 ULONG HSIZE; 1351 }; 1352 ULONG AsUlong; 1353 } NVME_CDW12_FEATURE_HOST_MEMORY_BUFFER, *PNVME_CDW12_FEATURE_HOST_MEMORY_BUFFER; 1354 1355 typedef union { 1356 __C89_NAMELESS struct { 1357 ULONG Reserved : 4; 1358 ULONG HMDLLA : 28; 1359 }; 1360 ULONG AsUlong; 1361 } NVME_CDW13_FEATURE_HOST_MEMORY_BUFFER, *PNVME_CDW13_FEATURE_HOST_MEMORY_BUFFER; 1362 1363 typedef union { 1364 __C89_NAMELESS struct { 1365 ULONG HMDLUA; 1366 }; 1367 ULONG AsUlong; 1368 } NVME_CDW14_FEATURE_HOST_MEMORY_BUFFER, *PNVME_CDW14_FEATURE_HOST_MEMORY_BUFFER; 1369 1370 typedef union { 1371 __C89_NAMELESS struct { 1372 ULONG HMDLEC; 1373 }; 1374 ULONG AsUlong; 1375 } NVME_CDW15_FEATURE_HOST_MEMORY_BUFFER, *PNVME_CDW15_FEATURE_HOST_MEMORY_BUFFER; 1376 1377 typedef struct { 1378 ULONGLONG BADD; 1379 ULONG BSIZE; 1380 ULONG Reserved; 1381 } NVME_HOST_MEMORY_BUFFER_DESCRIPTOR_ENTRY, *PNVME_HOST_MEMORY_BUFFER_DESCRIPTOR_ENTRY; 1382 1383 typedef union { 1384 __C89_NAMELESS struct { 1385 ULONG IOCSCI : 8; 1386 ULONG Reserved : 24; 1387 }; 1388 ULONG AsUlong; 1389 } NVME_CDW11_FEATURE_IO_COMMAND_SET_PROFILE, *PNVME_CDW11_FEATURE_IO_COMMAND_SET_PROFILE; 1390 1391 typedef union { 1392 __C89_NAMELESS struct { 1393 ULONG GDHM : 1; 1394 ULONG Reserved : 31; 1395 }; 1396 ULONG AsUlong; 1397 } NVME_CDW11_FEATURE_GET_HOST_METADATA, *PNVME_CDW11_FEATURE_GET_HOST_METADATA; 1398 1399 typedef enum { 1400 NVME_HOST_METADATA_ADD_REPLACE_ENTRY = 0, 1401 NVME_HOST_METADATA_DELETE_ENTRY_MULTIPLE = 1, 1402 NVME_HOST_METADATA_ADD_ENTRY_MULTIPLE = 2 1403 } NVME_HOST_METADATA_ELEMENT_ACTIONS; 1404 1405 typedef union { 1406 __C89_NAMELESS struct { 1407 ULONG Reserved0 : 13; 1408 ULONG EA : 2; 1409 ULONG Reserved1 : 17; 1410 }; 1411 ULONG AsUlong; 1412 } NVME_CDW11_FEATURE_SET_HOST_METADATA, *PNVME_CDW11_FEATURE_SET_HOST_METADATA; 1413 1414 typedef enum { 1415 NVME_CONTROLLER_METADATA_OPERATING_SYSTEM_CONTROLLER_NAME = 0x1, 1416 NVME_CONTROLLER_METADATA_OPERATING_SYSTEM_DRIVER_NAME = 0x2, 1417 NVME_CONTROLLER_METADATA_OPERATING_SYSTEM_DRIVER_VERSION = 0x3, 1418 NVME_CONTROLLER_METADATA_PREBOOT_CONTROLLER_NAME = 0x4, 1419 NVME_CONTROLLER_METADATA_PREBOOT_DRIVER_NAME = 0x5, 1420 NVME_CONTROLLER_METADATA_PREBOOT_DRIVER_VERSION = 0x6, 1421 NVME_CONTROLLER_METADATA_SYSTEM_PROCESSOR_MODEL = 0x7, 1422 NVME_CONTROLLER_METADATA_CHIPSET_DRIVER_NAME = 0x8, 1423 NVME_CONTROLLER_METADATA_CHIPSET_DRIVER_VERSION = 0x9, 1424 NVME_CONTROLLER_METADATA_OPERATING_SYSTEM_NAME_AND_BUILD = 0xA, 1425 NVME_CONTROLLER_METADATA_SYSTEM_PRODUCT_NAME = 0xB, 1426 NVME_CONTROLLER_METADATA_FIRMWARE_VERSION = 0xC, 1427 NVME_CONTROLLER_METADATA_OPERATING_SYSTEM_DRIVER_FILENAME = 0xD, 1428 NVME_CONTROLLER_METADATA_DISPLAY_DRIVER_NAME = 0xE, 1429 NVME_CONTROLLER_METADATA_DISPLAY_DRIVER_VERSION = 0xF, 1430 NVME_CONTROLLER_METADATA_HOST_DETERMINED_FAILURE_RECORD = 0x10 1431 } NVME_CONTROLLER_METADATA_ELEMENT_TYPES; 1432 1433 typedef enum { 1434 NVME_NAMESPACE_METADATA_OPERATING_SYSTEM_NAMESPACE_NAME = 0x1, 1435 NVME_NAMESPACE_METADATA_PREBOOT_NAMESPACE_NAME = 0x2, 1436 NVME_NAMESPACE_METADATA_OPERATING_SYSTEM_NAMESPACE_NAME_QUALIFIER_1 = 0x3, 1437 NVME_NAMESPACE_METADATA_OPERATING_SYSTEM_NAMESPACE_NAME_QUALIFIER_2 = 0x4 1438 } NVME_NAMESPACE_METADATA_ELEMENT_TYPES; 1439 1440 typedef struct { 1441 ULONG ET : 6; 1442 ULONG Reserved0 : 2; 1443 ULONG ER : 4; 1444 ULONG Reserved1 : 4; 1445 ULONG ELEN : 16; 1446 UCHAR EVAL[ANYSIZE_ARRAY]; 1447 } NVME_HOST_METADATA_ELEMENT_DESCRIPTOR, *PNVME_HOST_METADATA_ELEMENT_DESCRIPTOR; 1448 1449 typedef struct { 1450 UCHAR NumberOfMetadataElementDescriptors; 1451 UCHAR Reserved0; 1452 UCHAR MetadataElementDescriptors[4094]; 1453 } NVME_FEATURE_HOST_METADATA_DATA, *PNVME_FEATURE_HOST_METADATA_DATA; 1454 1455 typedef union { 1456 __C89_NAMELESS struct { 1457 ULONG NUM : 7; 1458 ULONG Reserved0 : 25; 1459 }; 1460 ULONG AsUlong; 1461 } NVME_CDW11_FEATURE_ERROR_INJECTION, *PNVME_CDW11_FEATURE_ERROR_INJECTION; 1462 1463 typedef NVME_CDW11_FEATURE_ERROR_INJECTION NVME_CDW0_FEATURE_ERROR_INJECTION, *PNVME_CDW0_FEATURE_ERROR_INJECTION; 1464 1465 typedef struct { 1466 union { 1467 __C89_NAMELESS struct { 1468 UCHAR Enable : 1; 1469 UCHAR SingleInstance : 1; 1470 UCHAR Reserved0 : 6; 1471 }; 1472 UCHAR AsUchar; 1473 } Flags; 1474 UCHAR Reserved1; 1475 USHORT ErrorInjectionType; 1476 UCHAR ErrorInjectionTypeSpecific[28]; 1477 } NVME_ERROR_INJECTION_ENTRY, *PNVME_ERROR_INJECTION_ENTRY; 1478 1479 typedef enum { 1480 NVME_ERROR_INJECTION_TYPE_RESERVED0 = 0, 1481 NVME_ERROR_INJECTION_TYPE_DEVICE_PANIC_CPU_CONTROLLER_HANG, 1482 NVME_ERROR_INJECTION_TYPE_DEVICE_PANIC_NAND_HANG, 1483 NVME_ERROR_INJECTION_TYPE_DEVICE_PANIC_PLP_DEFECT, 1484 NVME_ERROR_INJECTION_TYPE_DEVICE_PANIC_LOGICAL_FW_ERROR, 1485 NVME_ERROR_INJECTION_TYPE_DEVICE_PANIC_DRAM_CORRUPTION_CRITICAL, 1486 NVME_ERROR_INJECTION_TYPE_DEVICE_PANIC_DRAM_CORRUPTION_NONCRITICAL, 1487 NVME_ERROR_INJECTION_TYPE_DEVICE_PANIC_NAND_CORRUPTION, 1488 NVME_ERROR_INJECTION_TYPE_DEVICE_PANIC_SRAM_CORRUPTION, 1489 NVME_ERROR_INJECTION_TYPE_DEVICE_PANIC_HW_MALFUNCTION, 1490 NVME_ERROR_INJECTION_TYPE_RESERVED1, 1491 NVME_ERROR_INJECTION_TYPE_MAX = 0xFFFF 1492 } NVME_ERROR_INJECTION_TYPES; 1493 1494 typedef union { 1495 __C89_NAMELESS struct { 1496 ULONG Reserved0 : 31; 1497 ULONG Clear : 1; 1498 }; 1499 ULONG AsUlong; 1500 } NVME_CDW11_FEATURE_CLEAR_FW_UPDATE_HISTORY, *PNVME_CDW11_FEATURE_CLEAR_FW_UPDATE_HISTORY; 1501 1502 typedef union { 1503 __C89_NAMELESS struct { 1504 ULONG Reserved0 : 30; 1505 ULONG EOLBehavior : 2; 1506 }; 1507 ULONG AsUlong; 1508 } NVME_CDW11_FEATURE_READONLY_WRITETHROUGH_MODE, *PNVME_CDW11_FEATURE_READONLY_WRITETHROUGH_MODE; 1509 1510 typedef union { 1511 __C89_NAMELESS struct { 1512 ULONG EOLBehavior : 3; 1513 ULONG Reserved0 : 29; 1514 }; 1515 ULONG AsUlong; 1516 } NVME_CDW0_FEATURE_READONLY_WRITETHROUGH_MODE, *PNVME_CDW0_FEATURE_READONLY_WRITETHROUGH_MODE; 1517 1518 typedef union { 1519 __C89_NAMELESS struct { 1520 ULONG Reserved0 : 31; 1521 ULONG Clear : 1; 1522 }; 1523 ULONG AsUlong; 1524 } NVME_CDW11_FEATURE_CLEAR_PCIE_CORRECTABLE_ERROR_COUNTERS, *PNVME_CDW11_FEATURE_CLEAR_PCIE_CORRECTABLE_ERROR_COUNTERS; 1525 1526 typedef union { 1527 __C89_NAMELESS struct { 1528 ULONG Reserved0 : 31; 1529 ULONG Enable : 1; 1530 }; 1531 ULONG AsUlong; 1532 } NVME_CDW11_FEATURE_ENABLE_IEEE1667_SILO, *PNVME_CDW11_FEATURE_ENABLE_IEEE1667_SILO; 1533 1534 typedef union { 1535 __C89_NAMELESS struct { 1536 ULONG Enabled : 3; 1537 ULONG Reserved0 : 29; 1538 }; 1539 ULONG AsUlong; 1540 } NVME_CDW0_FEATURE_ENABLE_IEEE1667_SILO, *PNVME_CDW0_FEATURE_ENABLE_IEEE1667_SILO; 1541 1542 #define NVME_MAX_HOST_IDENTIFIER_SIZE 16 1543 #define NVME_HOST_IDENTIFIER_SIZE 8 1544 #define NVME_EXTENDED_HOST_IDENTIFIER_SIZE 16 1545 1546 typedef struct { 1547 ULONG EXHID : 1; 1548 ULONG Reserved : 31; 1549 } NVME_CDW11_FEATURE_HOST_IDENTIFIER, *PNVME_CDW11_FEATURE_HOST_IDENTIFIER; 1550 1551 typedef struct { 1552 UCHAR HOSTID[NVME_MAX_HOST_IDENTIFIER_SIZE]; 1553 } NVME_FEATURE_HOST_IDENTIFIER_DATA, *PNVME_FEATURE_HOST_IDENTIFIER_DATA; 1554 1555 typedef struct { 1556 ULONG PTPL : 1; 1557 ULONG Reserved : 31; 1558 } NVME_CDW11_FEATURE_RESERVATION_PERSISTENCE, *PNVME_CDW11_FEATURE_RESERVATION_PERSISTENCE; 1559 1560 typedef struct { 1561 ULONG Reserved : 1; 1562 ULONG REGPRE : 1; 1563 ULONG RESREL : 1; 1564 ULONG RESPRE : 1; 1565 ULONG Reserved1 : 28; 1566 } NVME_CDW11_FEATURE_RESERVATION_NOTIFICATION_MASK, *PNVME_CDW11_FEATURE_RESERVATION_NOTIFICATION_MASK; 1567 1568 typedef union { 1569 NVME_CDW11_FEATURE_NUMBER_OF_QUEUES NumberOfQueues; 1570 NVME_CDW11_FEATURE_INTERRUPT_COALESCING InterruptCoalescing; 1571 NVME_CDW11_FEATURE_INTERRUPT_VECTOR_CONFIG InterruptVectorConfig; 1572 NVME_CDW11_FEATURE_LBA_RANGE_TYPE LbaRangeType; 1573 NVME_CDW11_FEATURE_ARBITRATION Arbitration; 1574 NVME_CDW11_FEATURE_VOLATILE_WRITE_CACHE VolatileWriteCache; 1575 NVME_CDW11_FEATURE_ASYNC_EVENT_CONFIG AsyncEventConfig; 1576 NVME_CDW11_FEATURE_POWER_MANAGEMENT PowerManagement; 1577 NVME_CDW11_FEATURE_AUTO_POWER_STATE_TRANSITION AutoPowerStateTransition; 1578 NVME_CDW11_FEATURE_TEMPERATURE_THRESHOLD TemperatureThreshold; 1579 NVME_CDW11_FEATURE_ERROR_RECOVERY ErrorRecovery; 1580 NVME_CDW11_FEATURE_HOST_MEMORY_BUFFER HostMemoryBuffer; 1581 NVME_CDW11_FEATURE_WRITE_ATOMICITY_NORMAL WriteAtomicityNormal; 1582 NVME_CDW11_FEATURE_NON_OPERATIONAL_POWER_STATE NonOperationalPowerState; 1583 NVME_CDW11_FEATURE_IO_COMMAND_SET_PROFILE IoCommandSetProfile; 1584 NVME_CDW11_FEATURE_ERROR_INJECTION ErrorInjection; 1585 NVME_CDW11_FEATURE_HOST_IDENTIFIER HostIdentifier; 1586 NVME_CDW11_FEATURE_RESERVATION_PERSISTENCE ReservationPersistence; 1587 NVME_CDW11_FEATURE_RESERVATION_NOTIFICATION_MASK ReservationNotificationMask; 1588 NVME_CDW11_FEATURE_GET_HOST_METADATA GetHostMetadata; 1589 NVME_CDW11_FEATURE_SET_HOST_METADATA SetHostMetadata; 1590 ULONG AsUlong; 1591 } NVME_CDW11_FEATURES, *PNVME_CDW11_FEATURES; 1592 1593 typedef union { 1594 NVME_CDW12_FEATURE_HOST_MEMORY_BUFFER HostMemoryBuffer; 1595 ULONG AsUlong; 1596 } NVME_CDW12_FEATURES, *PNVME_CDW12_FEATURES; 1597 1598 typedef union { 1599 NVME_CDW13_FEATURE_HOST_MEMORY_BUFFER HostMemoryBuffer; 1600 ULONG AsUlong; 1601 } NVME_CDW13_FEATURES, *PNVME_CDW13_FEATURES; 1602 1603 typedef union { 1604 NVME_CDW14_FEATURE_HOST_MEMORY_BUFFER HostMemoryBuffer; 1605 ULONG AsUlong; 1606 } NVME_CDW14_FEATURES, *PNVME_CDW14_FEATURES; 1607 1608 typedef union { 1609 NVME_CDW15_FEATURE_HOST_MEMORY_BUFFER HostMemoryBuffer; 1610 ULONG AsUlong; 1611 } NVME_CDW15_FEATURES, *PNVME_CDW15_FEATURES; 1612 1613 #define NVME_MAX_LOG_SIZE 0x1000 1614 1615 typedef enum { 1616 NVME_LOG_PAGE_ERROR_INFO = 0x01, 1617 NVME_LOG_PAGE_HEALTH_INFO = 0x02, 1618 NVME_LOG_PAGE_FIRMWARE_SLOT_INFO = 0x03, 1619 NVME_LOG_PAGE_CHANGED_NAMESPACE_LIST = 0x04, 1620 NVME_LOG_PAGE_COMMAND_EFFECTS = 0x05, 1621 NVME_LOG_PAGE_DEVICE_SELF_TEST = 0x06, 1622 NVME_LOG_PAGE_TELEMETRY_HOST_INITIATED = 0x07, 1623 NVME_LOG_PAGE_TELEMETRY_CTLR_INITIATED = 0x08, 1624 NVME_LOG_PAGE_ENDURANCE_GROUP_INFORMATION = 0x09, 1625 NVME_LOG_PAGE_PREDICTABLE_LATENCY_NVM_SET = 0x0A, 1626 NVME_LOG_PAGE_PREDICTABLE_LATENCY_EVENT_AGGREGATE = 0x0B, 1627 NVME_LOG_PAGE_ASYMMETRIC_NAMESPACE_ACCESS = 0x0C, 1628 NVME_LOG_PAGE_PERSISTENT_EVENT_LOG = 0x0D, 1629 NVME_LOG_PAGE_LBA_STATUS_INFORMATION = 0x0E, 1630 NVME_LOG_PAGE_ENDURANCE_GROUP_EVENT_AGGREGATE = 0x0F, 1631 NVME_LOG_PAGE_RESERVATION_NOTIFICATION = 0x80, 1632 NVME_LOG_PAGE_SANITIZE_STATUS = 0x81, 1633 NVME_LOG_PAGE_CHANGED_ZONE_LIST = 0xBF 1634 } NVME_LOG_PAGES; 1635 1636 typedef union { 1637 __C89_NAMELESS struct { 1638 ULONG LID : 8; 1639 ULONG Reserved0 : 8; 1640 ULONG NUMD : 12; 1641 ULONG Reserved1 : 4; 1642 }; 1643 ULONG AsUlong; 1644 } NVME_CDW10_GET_LOG_PAGE, *PNVME_CDW10_GET_LOG_PAGE; 1645 1646 typedef union { 1647 __C89_NAMELESS struct { 1648 ULONG LID : 8; 1649 ULONG LSP : 4; 1650 ULONG Reserved0 : 3; 1651 ULONG RAE : 1; 1652 ULONG NUMDL : 16; 1653 }; 1654 ULONG AsUlong; 1655 } NVME_CDW10_GET_LOG_PAGE_V13, *PNVME_CDW10_GET_LOG_PAGE_V13; 1656 1657 typedef union { 1658 __C89_NAMELESS struct { 1659 ULONG NUMDU : 16; 1660 ULONG LogSpecificIdentifier : 16; 1661 }; 1662 ULONG AsUlong; 1663 } NVME_CDW11_GET_LOG_PAGE, *PNVME_CDW11_GET_LOG_PAGE; 1664 1665 typedef struct { 1666 ULONG LPOL; 1667 } NVME_CDW12_GET_LOG_PAGE, *PNVME_CDW12_GET_LOG_PAGE; 1668 1669 typedef struct { 1670 ULONG LPOU; 1671 } NVME_CDW13_GET_LOG_PAGE, *PNVME_CDW13_GET_LOG_PAGE; 1672 1673 typedef union { 1674 __C89_NAMELESS struct { 1675 ULONG UUIDIndex : 7; 1676 ULONG Reserved : 17; 1677 ULONG CommandSetIdentifier : 8; 1678 }; 1679 ULONG AsUlong; 1680 } NVME_CDW14_GET_LOG_PAGE, *PNVME_CDW14_GET_LOG_PAGE; 1681 1682 typedef struct { 1683 ULONGLONG ErrorCount; 1684 USHORT SQID; 1685 USHORT CMDID; 1686 NVME_COMMAND_STATUS Status; 1687 struct { 1688 USHORT Byte : 8; 1689 USHORT Bit : 3; 1690 USHORT Reserved : 5; 1691 } ParameterErrorLocation; 1692 ULONGLONG Lba; 1693 ULONG NameSpace; 1694 UCHAR VendorInfoAvailable; 1695 UCHAR Reserved0[3]; 1696 ULONGLONG CommandSpecificInfo; 1697 UCHAR Reserved1[24]; 1698 } NVME_ERROR_INFO_LOG, *PNVME_ERROR_INFO_LOG; 1699 1700 typedef struct { 1701 union { 1702 __C89_NAMELESS struct { 1703 UCHAR AvailableSpaceLow : 1; 1704 UCHAR TemperatureThreshold : 1; 1705 UCHAR ReliabilityDegraded : 1; 1706 UCHAR ReadOnly : 1; 1707 UCHAR VolatileMemoryBackupDeviceFailed : 1; 1708 UCHAR Reserved : 3; 1709 }; 1710 UCHAR AsUchar; 1711 } CriticalWarning; 1712 UCHAR Temperature[2]; 1713 UCHAR AvailableSpare; 1714 UCHAR AvailableSpareThreshold; 1715 UCHAR PercentageUsed; 1716 UCHAR Reserved0[26]; 1717 UCHAR DataUnitRead[16]; 1718 UCHAR DataUnitWritten[16]; 1719 UCHAR HostReadCommands[16]; 1720 UCHAR HostWrittenCommands[16]; 1721 UCHAR ControllerBusyTime[16]; 1722 UCHAR PowerCycle[16]; 1723 UCHAR PowerOnHours[16]; 1724 UCHAR UnsafeShutdowns[16]; 1725 UCHAR MediaErrors[16]; 1726 UCHAR ErrorInfoLogEntryCount[16]; 1727 ULONG WarningCompositeTemperatureTime; 1728 ULONG CriticalCompositeTemperatureTime; 1729 USHORT TemperatureSensor1; 1730 USHORT TemperatureSensor2; 1731 USHORT TemperatureSensor3; 1732 USHORT TemperatureSensor4; 1733 USHORT TemperatureSensor5; 1734 USHORT TemperatureSensor6; 1735 USHORT TemperatureSensor7; 1736 USHORT TemperatureSensor8; 1737 UCHAR Reserved1[296]; 1738 } NVME_HEALTH_INFO_LOG, *PNVME_HEALTH_INFO_LOG; 1739 1740 #define NVME_TELEMETRY_DATA_BLOCK_SIZE 0x200 1741 1742 typedef struct _NVME_TELEMETRY_HOST_INITIATED_LOG { 1743 UCHAR LogIdentifier; 1744 UCHAR Reserved0[4]; 1745 UCHAR OrganizationID[3]; 1746 USHORT Area1LastBlock; 1747 USHORT Area2LastBlock; 1748 USHORT Area3LastBlock; 1749 UCHAR Reserved1[2]; 1750 ULONG Area4LastBlock; 1751 UCHAR Reserved2[361]; 1752 UCHAR HostInitiatedDataGenerationNumber; 1753 UCHAR ControllerInitiatedDataAvailable; 1754 UCHAR ControllerInitiatedDataGenerationNumber; 1755 UCHAR ReasonIdentifier[128]; 1756 } NVME_TELEMETRY_HOST_INITIATED_LOG, *PNVME_TELEMETRY_HOST_INITIATED_LOG; 1757 1758 typedef struct _NVME_TELEMETRY_CONTROLLER_INITIATED_LOG { 1759 UCHAR LogIdentifier; 1760 UCHAR Reserved0[4]; 1761 UCHAR OrganizationID[3]; 1762 USHORT Area1LastBlock; 1763 USHORT Area2LastBlock; 1764 USHORT Area3LastBlock; 1765 UCHAR Reserved1[2]; 1766 ULONG Area4LastBlock; 1767 UCHAR Reserved2[362]; 1768 UCHAR ControllerInitiatedDataAvailable; 1769 UCHAR ControllerInitiatedDataGenerationNumber; 1770 UCHAR ReasonIdentifier[128]; 1771 } NVME_TELEMETRY_CONTROLLER_INITIATED_LOG, *PNVME_TELEMETRY_CONTROLLER_INITIATED_LOG; 1772 1773 typedef struct { 1774 struct { 1775 UCHAR ActiveSlot : 3; 1776 UCHAR Reserved0 : 1; 1777 UCHAR PendingActivateSlot : 3; 1778 UCHAR Reserved1 : 1; 1779 } AFI; 1780 UCHAR Reserved0[7]; 1781 ULONGLONG FRS[7]; 1782 UCHAR Reserved1[448]; 1783 } NVME_FIRMWARE_SLOT_INFO_LOG, *PNVME_FIRMWARE_SLOT_INFO_LOG; 1784 1785 typedef struct { 1786 ULONG NSID[1024]; 1787 } NVME_CHANGED_NAMESPACE_LIST_LOG, *PNVME_CHANGED_NAMESPACE_LIST_LOG; 1788 1789 typedef struct { 1790 USHORT ZoneIdentifiersCount; 1791 UCHAR Reserved[6]; 1792 ULONGLONG ZoneIdentifier[511]; 1793 } NVME_CHANGED_ZONE_LIST_LOG, *PNVME_CHANGED_ZONE_LIST_LOG; 1794 1795 typedef enum { 1796 NVME_COMMAND_EFFECT_SBUMISSION_EXECUTION_LIMIT_NONE = 0, 1797 NVME_COMMAND_EFFECT_SBUMISSION_EXECUTION_LIMIT_SINGLE_PER_NAMESPACE = 1, 1798 NVME_COMMAND_EFFECT_SBUMISSION_EXECUTION_LIMIT_SINGLE_PER_CONTROLLER = 2 1799 } NVME_COMMAND_EFFECT_SBUMISSION_EXECUTION_LIMITS; 1800 1801 typedef union { 1802 __C89_NAMELESS struct { 1803 ULONG CSUPP : 1; 1804 ULONG LBCC : 1; 1805 ULONG NCC : 1; 1806 ULONG NIC : 1; 1807 ULONG CCC : 1; 1808 ULONG Reserved0 : 11; 1809 ULONG CSE : 3; 1810 ULONG Reserved1 : 13; 1811 }; 1812 ULONG AsUlong; 1813 } NVME_COMMAND_EFFECTS_DATA, *PNVME_COMMAND_EFFECTS_DATA; 1814 1815 typedef struct { 1816 NVME_COMMAND_EFFECTS_DATA ACS[256]; 1817 NVME_COMMAND_EFFECTS_DATA IOCS[256]; 1818 UCHAR Reserved[2048]; 1819 } NVME_COMMAND_EFFECTS_LOG, *PNVME_COMMAND_EFFECTS_LOG; 1820 1821 #pragma pack(push, 1) 1822 typedef struct { 1823 struct { 1824 UCHAR Result : 4; 1825 UCHAR CodeValue : 4; 1826 } Status; 1827 UCHAR SegmentNumber; 1828 struct { 1829 UCHAR NSIDValid : 1; 1830 UCHAR FLBAValid : 1; 1831 UCHAR SCTValid : 1; 1832 UCHAR SCValid : 1; 1833 UCHAR Reserved : 4; 1834 } ValidDiagnostics; 1835 UCHAR Reserved; 1836 ULONGLONG POH; 1837 ULONG NSID; 1838 ULONGLONG FailingLBA; 1839 struct { 1840 UCHAR AdditionalInfo : 3; 1841 UCHAR Reserved : 5; 1842 } StatusCodeType; 1843 UCHAR StatusCode; 1844 USHORT VendorSpecific; 1845 } NVME_DEVICE_SELF_TEST_RESULT_DATA, *PNVME_DEVICE_SELF_TEST_RESULT_DATA; 1846 1847 typedef struct { 1848 struct { 1849 UCHAR Status : 4; 1850 UCHAR Reserved : 4; 1851 } CurrentOperation; 1852 struct { 1853 UCHAR CompletePercent : 7; 1854 UCHAR Reserved : 1; 1855 } CurrentCompletion; 1856 UCHAR Reserved[2]; 1857 NVME_DEVICE_SELF_TEST_RESULT_DATA ResultData[20]; 1858 } NVME_DEVICE_SELF_TEST_LOG, *PNVME_DEVICE_SELF_TEST_LOG; 1859 1860 typedef struct { 1861 ULONG Reserved0; 1862 UCHAR AvailableSpareThreshold; 1863 UCHAR PercentageUsed; 1864 UCHAR Reserved1[26]; 1865 UCHAR EnduranceEstimate[16]; 1866 UCHAR DataUnitsRead[16]; 1867 UCHAR DataUnitsWritten[16]; 1868 UCHAR MediaUnitsWritten[16]; 1869 UCHAR Reserved2[416]; 1870 } NVME_ENDURANCE_GROUP_LOG, *PNVME_ENDURANCE_GROUP_LOG; 1871 1872 typedef struct { 1873 UCHAR LogIdentifier; 1874 UCHAR Reserved0[3]; 1875 ULONG TotalNumberOfEvents; 1876 ULONGLONG TotalLogLength; 1877 UCHAR LogRevision; 1878 UCHAR Reserved1; 1879 USHORT LogHeaderLength; 1880 ULONGLONG Timestamp; 1881 UCHAR PowerOnHours[16]; 1882 ULONGLONG PowerCycleCount; 1883 USHORT PciVendorId; 1884 USHORT PciSubsystemVendorId; 1885 UCHAR SerialNumber[20]; 1886 UCHAR ModelNumber[40]; 1887 UCHAR NVMSubsystemNVMeQualifiedName[256]; 1888 UCHAR Reserved[108]; 1889 UCHAR SupportedEventsBitmap[32]; 1890 } NVME_PERSISTENT_EVENT_LOG_HEADER, *PNVME_PERSISTENT_EVENT_LOG_HEADER; 1891 1892 typedef struct { 1893 UCHAR EventType; 1894 UCHAR EventTypeRevision; 1895 UCHAR EventHeaderLength; 1896 UCHAR Reserved0; 1897 USHORT ControllerIdentifier; 1898 ULONGLONG EventTimestamp; 1899 UCHAR Reserved1[6]; 1900 USHORT VendorSpecificInformationLength; 1901 USHORT EventLength; 1902 } NVME_PERSISTENT_EVENT_LOG_EVENT_HEADER, *PNVME_PERSISTENT_EVENT_LOG_EVENT_HEADER; 1903 1904 typedef enum { 1905 NVME_PERSISTENT_EVENT_TYPE_RESERVED0 = 0x00, 1906 NVME_PERSISTENT_EVENT_TYPE_SMART_HEALTH_LOG_SNAPSHOT = 0x01, 1907 NVME_PERSISTENT_EVENT_TYPE_FIRMWARE_COMMIT = 0x02, 1908 NVME_PERSISTENT_EVENT_TYPE_TIMESTAMP_CHANGE = 0x03, 1909 NVME_PERSISTENT_EVENT_TYPE_POWER_ON_OR_RESET = 0x04, 1910 NVME_PERSISTENT_EVENT_TYPE_NVM_SUBSYSTEM_HARDWARE_ERROR = 0x05, 1911 NVME_PERSISTENT_EVENT_TYPE_CHANGE_NAMESPACE = 0x06, 1912 NVME_PERSISTENT_EVENT_TYPE_FORMAT_NVM_START = 0x07, 1913 NVME_PERSISTENT_EVENT_TYPE_FORMAT_NVM_COMPLETION = 0x08, 1914 NVME_PERSISTENT_EVENT_TYPE_SANITIZE_START = 0x09, 1915 NVME_PERSISTENT_EVENT_TYPE_SANITIZE_COMPLETION = 0x0A, 1916 NVME_PERSISTENT_EVENT_TYPE_SET_FEATURE = 0x0B, 1917 NVME_PERSISTENT_EVENT_TYPE_TELEMETRY_LOG_CREATED = 0x0C, 1918 NVME_PERSISTENT_EVENT_TYPE_THERMAL_EXCURSION = 0x0D, 1919 NVME_PERSISTENT_EVENT_TYPE_RESERVED1_BEGIN = 0x0E, 1920 NVME_PERSISTENT_EVENT_TYPE_RESERVED1_END = 0xDD, 1921 NVME_PERSISTENT_EVENT_TYPE_VENDOR_SPECIFIC_EVENT = 0xDE, 1922 NVME_PERSISTENT_EVENT_TYPE_TCG_DEFINED = 0xDF, 1923 NVME_PERSISTENT_EVENT_TYPE_RESERVED2_BEGIN = 0xE0, 1924 NVME_PERSISTENT_EVENT_TYPE_RESERVED2_END = 0xFF, 1925 NVME_PERSISTENT_EVENT_TYPE_MAX = 0xFF 1926 } NVME_PERSISTENT_EVENT_LOG_EVENT_TYPES; 1927 1928 #pragma pack(pop) 1929 1930 typedef enum { 1931 NVME_RESERVATION_NOTIFICATION_TYPE_EMPTY_LOG_PAGE = 0, 1932 NVME_RESERVATION_NOTIFICATION_TYPE_REGISTRATION_PREEMPTED = 1, 1933 NVME_RESERVATION_NOTIFICATION_TYPE_REGISTRATION_RELEASED = 2, 1934 NVME_RESERVATION_NOTIFICATION_TYPE_RESERVATION_PREEPMPTED = 3 1935 } NVME_RESERVATION_NOTIFICATION_TYPES; 1936 1937 typedef struct { 1938 ULONGLONG LogPageCount; 1939 UCHAR LogPageType; 1940 UCHAR AvailableLogPageCount; 1941 UCHAR Reserved0[2]; 1942 ULONG NameSpaceId; 1943 UCHAR Reserved1[48]; 1944 } NVME_RESERVATION_NOTIFICATION_LOG, *PNVME_RESERVATION_NOTIFICATION_LOG; 1945 1946 typedef enum { 1947 NVME_SANITIZE_OPERATION_NONE = 0, 1948 NVME_SANITIZE_OPERATION_SUCCEEDED = 1, 1949 NVME_SANITIZE_OPERATION_IN_PROGRESS = 2, 1950 NVME_SANITIZE_OPERATION_FAILED = 3, 1951 NVME_SANITIZE_OPERATION_SUCCEEDED_WITH_FORCED_DEALLOCATION = 4 1952 } NVME_SANITIZE_OPERATION_STATUS, *PNVME_SANITIZE_OPERATION_STATUS; 1953 1954 typedef struct { 1955 USHORT MostRecentSanitizeOperationStatus : 3; 1956 USHORT NumberCompletedPassesOfOverwrite : 4; 1957 USHORT GlobalDataErased : 1; 1958 USHORT Reserved : 8; 1959 } NVME_SANITIZE_STATUS, *PNVME_SANITIZE_STATUS; 1960 1961 typedef struct { 1962 USHORT SPROG; 1963 NVME_SANITIZE_STATUS SSTAT; 1964 ULONG SCDW10; 1965 ULONG EstimatedTimeForOverwrite; 1966 ULONG EstimatedTimeForBlockErase; 1967 ULONG EstimatedTimeForCryptoErase; 1968 ULONG EstimatedTimeForOverwriteWithNoDeallocateMediaModification; 1969 ULONG EstimatedTimeForBlockEraseWithNoDeallocateMediaModification; 1970 ULONG EstimatedTimeForCryptoEraseWithNoDeallocateMediaModification; 1971 UCHAR Reserved[480]; 1972 } NVME_SANITIZE_STATUS_LOG, *PNVME_SANITIZE_STATUS_LOG; 1973 1974 typedef struct { 1975 ULONG NUMD; 1976 } NVME_CDW10_FIRMWARE_DOWNLOAD, *PNVME_CDW10_FIRMWARE_DOWNLOAD; 1977 1978 typedef struct { 1979 ULONG OFST; 1980 } NVME_CDW11_FIRMWARE_DOWNLOAD, *PNVME_CDW11_FIRMWARE_DOWNLOAD; 1981 1982 typedef enum { 1983 NVME_FIRMWARE_ACTIVATE_ACTION_DOWNLOAD_TO_SLOT = 0, 1984 NVME_FIRMWARE_ACTIVATE_ACTION_DOWNLOAD_TO_SLOT_AND_ACTIVATE = 1, 1985 NVME_FIRMWARE_ACTIVATE_ACTION_ACTIVATE = 2, 1986 NVME_FIRMWARE_ACTIVATE_ACTION_DOWNLOAD_TO_SLOT_AND_ACTIVATE_IMMEDIATE = 3 1987 } NVME_FIRMWARE_ACTIVATE_ACTIONS; 1988 1989 typedef union { 1990 __C89_NAMELESS struct { 1991 ULONG FS : 3; 1992 ULONG AA : 2; 1993 ULONG Reserved : 27; 1994 }; 1995 ULONG AsUlong; 1996 } NVME_CDW10_FIRMWARE_ACTIVATE, *PNVME_CDW10_FIRMWARE_ACTIVATE; 1997 1998 typedef enum { 1999 NVME_PROTECTION_INFORMATION_NOT_ENABLED = 0, 2000 NVME_PROTECTION_INFORMATION_TYPE1 = 1, 2001 NVME_PROTECTION_INFORMATION_TYPE2 = 2, 2002 NVME_PROTECTION_INFORMATION_TYPE3 = 3 2003 } NVME_PROTECTION_INFORMATION_TYPES; 2004 2005 typedef enum { 2006 NVME_SECURE_ERASE_NONE = 0, 2007 NVME_SECURE_ERASE_USER_DATA = 1, 2008 NVME_SECURE_ERASE_CRYPTOGRAPHIC = 2 2009 } NVME_SECURE_ERASE_SETTINGS; 2010 2011 typedef union { 2012 __C89_NAMELESS struct { 2013 ULONG LBAF : 4; 2014 ULONG MS : 1; 2015 ULONG PI : 3; 2016 ULONG PIL : 1; 2017 ULONG SES : 3; 2018 ULONG ZF : 2; 2019 ULONG Reserved : 18; 2020 }; 2021 ULONG AsUlong; 2022 } NVME_CDW10_FORMAT_NVM, *PNVME_CDW10_FORMAT_NVM; 2023 2024 typedef enum { 2025 NVME_MEDIA_ADDITIONALLY_MODIFIED_AFTER_SANITIZE_NOT_DEFINED = 0, 2026 NVME_MEDIA_NOT_ADDITIONALLY_MODIFIED_AFTER_SANITIZE = 1, 2027 NVME_MEDIA_ADDITIONALLY_MOFIDIED_AFTER_SANITIZE = 2 2028 } NVME_NO_DEALLOCATE_MODIFIES_MEDIA_AFTER_SANITIZE, *PNVME_NO_DEALLOCATE_MODIFIES_MEDIA_AFTER_SANITIZE; 2029 2030 typedef enum { 2031 NVME_SANITIZE_ACTION_RESERVED = 0, 2032 NVME_SANITIZE_ACTION_EXIT_FAILURE_MODE = 1, 2033 NVME_SANITIZE_ACTION_START_BLOCK_ERASE_SANITIZE = 2, 2034 NVME_SANITIZE_ACTION_START_OVERWRITE_SANITIZE = 3, 2035 NVME_SANITIZE_ACTION_START_CRYPTO_ERASE_SANITIZE = 4 2036 } NVME_SANITIZE_ACTION, *PNVME_SANITIZE_ACTION; 2037 2038 typedef union { 2039 __C89_NAMELESS struct { 2040 ULONG SANACT : 3; 2041 ULONG AUSE : 1; 2042 ULONG OWPASS : 4; 2043 ULONG OIPBP : 1; 2044 ULONG NDAS : 1; 2045 ULONG Reserved : 22; 2046 }; 2047 ULONG AsUlong; 2048 } NVME_CDW10_SANITIZE, *PNVME_CDW10_SANITIZE; 2049 2050 typedef union { 2051 __C89_NAMELESS struct { 2052 ULONG OVRPAT; 2053 }; 2054 ULONG AsUlong; 2055 } NVME_CDW11_SANITIZE; 2056 2057 typedef enum { 2058 NVME_RESERVATION_TYPE_RESERVED = 0, 2059 NVME_RESERVATION_TYPE_WRITE_EXCLUSIVE = 1, 2060 NVME_RESERVATION_TYPE_EXCLUSIVE_ACCESS = 2, 2061 NVME_RESERVATION_TYPE_WRITE_EXCLUSIVE_REGISTRANTS_ONLY = 3, 2062 NVME_RESERVATION_TYPE_EXCLUSIVE_ACCESS_REGISTRANTS_ONLY = 4, 2063 NVME_RESERVATION_TYPE_WRITE_EXCLUSIVE_ALL_REGISTRANTS = 5, 2064 NVME_RESERVATION_TYPE_EXCLUSIVE_ACCESS_ALL_REGISTRANTS = 6 2065 } NVME_RESERVATION_TYPES; 2066 2067 typedef enum { 2068 NVME_RESERVATION_ACQUIRE_ACTION_ACQUIRE = 0, 2069 NVME_RESERVATION_ACQUIRE_ACTION_PREEMPT = 1, 2070 NVME_RESERVATION_ACQUIRE_ACTION_PREEMPT_AND_ABORT = 2 2071 } NVME_RESERVATION_ACQUIRE_ACTIONS; 2072 2073 typedef struct { 2074 ULONG PTPL : 1; 2075 ULONG Reserved : 31; 2076 } NVME_CDW0_RESERVATION_PERSISTENCE, *PNVME_CDW0_RESERVATION_PERSISTENCE; 2077 2078 typedef union { 2079 __C89_NAMELESS struct { 2080 ULONG RACQA : 3; 2081 ULONG IEKEY : 1; 2082 ULONG Reserved : 4; 2083 ULONG RTYPE : 8; 2084 ULONG Reserved1 : 16; 2085 }; 2086 ULONG AsUlong; 2087 } NVME_CDW10_RESERVATION_ACQUIRE, *PNVME_CDW10_RESERVATION_ACQUIRE; 2088 2089 typedef struct { 2090 ULONGLONG CRKEY; 2091 ULONGLONG PRKEY; 2092 } NVME_RESERVATION_ACQUIRE_DATA_STRUCTURE, *PNVME_RESERVATION_ACQUIRE_DATA_STRUCTURE; 2093 2094 typedef enum { 2095 NVME_RESERVATION_REGISTER_ACTION_REGISTER = 0, 2096 NVME_RESERVATION_REGISTER_ACTION_UNREGISTER = 1, 2097 NVME_RESERVATION_REGISTER_ACTION_REPLACE = 2 2098 } NVME_RESERVATION_REGISTER_ACTIONS; 2099 2100 typedef enum { 2101 NVME_RESERVATION_REGISTER_PTPL_STATE_NO_CHANGE = 0, 2102 NVME_RESERVATION_REGISTER_PTPL_STATE_RESERVED = 1, 2103 NVME_RESERVATION_REGISTER_PTPL_STATE_SET_TO_0 = 2, 2104 NVME_RESERVATION_REGISTER_PTPL_STATE_SET_TO_1 = 3 2105 } NVME_RESERVATION_REGISTER_PTPL_STATE_CHANGES; 2106 2107 typedef union { 2108 __C89_NAMELESS struct { 2109 ULONG RREGA : 3; 2110 ULONG IEKEY : 1; 2111 ULONG Reserved : 26; 2112 ULONG CPTPL : 2; 2113 }; 2114 ULONG AsUlong; 2115 } NVME_CDW10_RESERVATION_REGISTER, *PNVME_CDW10_RESERVATION_REGISTER; 2116 2117 typedef struct { 2118 ULONGLONG CRKEY; 2119 ULONGLONG NRKEY; 2120 } NVME_RESERVATION_REGISTER_DATA_STRUCTURE, *PNVME_RESERVATION_REGISTER_DATA_STRUCTURE; 2121 2122 typedef enum { 2123 NVME_RESERVATION_RELEASE_ACTION_RELEASE = 0, 2124 NVME_RESERVATION_RELEASE_ACTION_CLEAR = 1 2125 } NVME_RESERVATION_RELEASE_ACTIONS; 2126 2127 typedef union { 2128 struct { 2129 ULONG RRELA : 3; 2130 ULONG IEKEY : 1; 2131 ULONG Reserved : 4; 2132 ULONG RTYPE : 8; 2133 ULONG Reserved1 : 16; 2134 }; 2135 ULONG AsUlong; 2136 } NVME_CDW10_RESERVATION_RELEASE, *PNVME_CDW10_RESERVATION_RELEASE; 2137 2138 typedef struct { 2139 ULONGLONG CRKEY; 2140 } NVME_RESERVATION_RELEASE_DATA_STRUCTURE, *PNVME_RESERVATION_RELEASE_DATA_STRUCTURE; 2141 2142 typedef union { 2143 __C89_NAMELESS struct { 2144 ULONG NUMD; 2145 }; 2146 ULONG AsUlong; 2147 } NVME_CDW10_RESERVATION_REPORT, *PNVME_CDW10_RESERVATION_REPORT; 2148 2149 typedef union { 2150 __C89_NAMELESS struct { 2151 ULONG EDS : 1; 2152 ULONG Reserved : 31; 2153 }; 2154 ULONG AsUlong; 2155 } NVME_CDW11_RESERVATION_REPORT, *PNVME_CDW11_RESERVATION_REPORT; 2156 2157 #pragma pack(push, 1) 2158 typedef struct { 2159 ULONG GEN; 2160 UCHAR RTYPE; 2161 USHORT REGCTL; 2162 UCHAR Reserved[2]; 2163 UCHAR PTPLS; 2164 UCHAR Reserved1[14]; 2165 } NVME_RESERVATION_REPORT_STATUS_HEADER, *PNVME_RESERVATION_REPORT_STATUS_HEADER; 2166 #pragma pack(pop) 2167 2168 C_ASSERT(sizeof(NVME_RESERVATION_REPORT_STATUS_HEADER) == 24); 2169 2170 typedef struct { 2171 USHORT CNTLID; 2172 struct { 2173 UCHAR HoldReservation : 1; 2174 UCHAR Reserved : 7; 2175 } RCSTS; 2176 UCHAR Reserved[5]; 2177 UCHAR HOSTID[8]; 2178 ULONGLONG RKEY; 2179 } NVME_REGISTERED_CONTROLLER_DATA, *PNVME_REGISTERED_CONTROLLER_DATA; 2180 2181 C_ASSERT(sizeof(NVME_REGISTERED_CONTROLLER_DATA) == 24); 2182 2183 typedef struct { 2184 NVME_RESERVATION_REPORT_STATUS_HEADER Header; 2185 NVME_REGISTERED_CONTROLLER_DATA RegisteredControllersData[ANYSIZE_ARRAY]; 2186 } NVME_RESERVATION_REPORT_STATUS_DATA_STRUCTURE, *PNVME_RESERVATION_REPORT_STATUS_DATA_STRUCTURE; 2187 2188 typedef struct { 2189 USHORT CNTLID; 2190 struct { 2191 UCHAR HoldReservation : 1; 2192 UCHAR Reserved : 7; 2193 } RCSTS; 2194 UCHAR Reserved[5]; 2195 ULONGLONG RKEY; 2196 UCHAR HOSTID[16]; 2197 UCHAR Reserved1[32]; 2198 } NVME_REGISTERED_CONTROLLER_EXTENDED_DATA, *PNVME_REGISTERED_CONTROLLER_EXTENDED_DATA; 2199 2200 C_ASSERT(sizeof(NVME_REGISTERED_CONTROLLER_EXTENDED_DATA) == 64); 2201 2202 typedef struct { 2203 NVME_RESERVATION_REPORT_STATUS_HEADER Header; 2204 UCHAR Reserved1[40]; 2205 NVME_REGISTERED_CONTROLLER_EXTENDED_DATA RegisteredControllersExtendedData[ANYSIZE_ARRAY]; 2206 } NVME_RESERVATION_REPORT_STATUS_EXTENDED_DATA_STRUCTURE, *PNVME_RESERVATION_REPORT_STATUS_EXTENDED_DATA_STRUCTURE; 2207 2208 typedef enum { 2209 NVME_DIRECTIVE_TYPE_IDENTIFY = 0x00, 2210 NVME_DIRECTIVE_TYPE_STREAMS = 0x01 2211 } NVME_DIRECTIVE_TYPES; 2212 2213 #define NVME_STREAMS_ID_MIN 1 2214 #define NVME_STREAMS_ID_MAX 0xFFFF 2215 2216 typedef struct { 2217 ULONG NUMD; 2218 } NVME_CDW10_DIRECTIVE_RECEIVE, *PNVME_CDW10_DIRECTIVE_RECEIVE; 2219 2220 typedef union { 2221 __C89_NAMELESS struct { 2222 ULONG DOPER : 8; 2223 ULONG DTYPE : 8; 2224 ULONG DSPEC : 16; 2225 }; 2226 ULONG AsUlong; 2227 } NVME_CDW11_DIRECTIVE_RECEIVE, *PNVME_CDW11_DIRECTIVE_RECEIVE; 2228 2229 typedef struct { 2230 ULONG NUMD; 2231 } NVME_CDW10_DIRECTIVE_SEND, *PNVME_CDW10_DIRECTIVE_SEND; 2232 2233 typedef union { 2234 __C89_NAMELESS struct { 2235 ULONG DOPER : 8; 2236 ULONG DTYPE : 8; 2237 ULONG DSPEC : 16; 2238 }; 2239 ULONG AsUlong; 2240 } NVME_CDW11_DIRECTIVE_SEND, *PNVME_CDW11_DIRECTIVE_SEND; 2241 2242 typedef enum { 2243 NVME_DIRECTIVE_RECEIVE_IDENTIFY_OPERATION_RETURN_PARAMETERS = 1 2244 } NVME_DIRECTIVE_RECEIVE_IDENTIFY_OPERATIONS; 2245 2246 typedef enum { 2247 NVME_DIRECTIVE_SEND_IDENTIFY_OPERATION_ENABLE_DIRECTIVE = 1 2248 } NVME_DIRECTIVE_SEND_IDENTIFY_OPERATIONS; 2249 2250 typedef struct { 2251 UCHAR Identify : 1; 2252 UCHAR Streams : 1; 2253 UCHAR Reserved0 : 6; 2254 UCHAR Reserved1[31]; 2255 } NVME_DIRECTIVE_IDENTIFY_RETURN_PARAMETERS_DESCRIPTOR, *PNVME_DIRECTIVE_IDENTIFY_RETURN_PARAMETERS_DESCRIPTOR; 2256 2257 typedef struct { 2258 NVME_DIRECTIVE_IDENTIFY_RETURN_PARAMETERS_DESCRIPTOR DirectivesSupported; 2259 NVME_DIRECTIVE_IDENTIFY_RETURN_PARAMETERS_DESCRIPTOR DirectivesEnabled; 2260 } NVME_DIRECTIVE_IDENTIFY_RETURN_PARAMETERS, *PNVME_DIRECTIVE_IDENTIFY_RETURN_PARAMETERS; 2261 2262 typedef union { 2263 __C89_NAMELESS struct { 2264 ULONG ENDIR : 1; 2265 ULONG Reserved0 : 7; 2266 ULONG DTYPE : 8; 2267 ULONG Reserved1 : 16; 2268 }; 2269 ULONG AsUlong; 2270 } NVME_CDW12_DIRECTIVE_SEND_IDENTIFY_ENABLE_DIRECTIVE, *PNVME_CDW12_DIRECTIVE_SEND_IDENTIFY_ENABLE_DIRECTIVE; 2271 2272 typedef enum { 2273 NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_RETURN_PARAMETERS = 1, 2274 NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_GET_STATUS = 2, 2275 NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_ALLOCATE_RESOURCES = 3 2276 } NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATIONS; 2277 2278 typedef enum { 2279 NVME_DIRECTIVE_SEND_STREAMS_OPERATION_RELEASE_IDENTIFIER = 1, 2280 NVME_DIRECTIVE_SEND_STREAMS_OPERATION_RELEASE_RESOURCES = 2 2281 } NVME_DIRECTIVE_SEND_STREAMS_OPERATIONS; 2282 2283 typedef struct { 2284 USHORT MSL; 2285 USHORT NSSA; 2286 USHORT NSSO; 2287 UCHAR Reserved0[10]; 2288 ULONG SWS; 2289 USHORT SGS; 2290 USHORT NSA; 2291 USHORT NSO; 2292 UCHAR Reserved1[6]; 2293 } NVME_DIRECTIVE_STREAMS_RETURN_PARAMETERS, *PNVME_DIRECTIVE_STREAMS_RETURN_PARAMETERS; 2294 2295 #define NVME_STREAMS_GET_STATUS_MAX_IDS 65535 2296 2297 typedef struct { 2298 USHORT OpenStreamCount; 2299 USHORT StreamIdentifiers[NVME_STREAMS_GET_STATUS_MAX_IDS]; 2300 } NVME_DIRECTIVE_STREAMS_GET_STATUS_DATA, *PNVME_DIRECTIVE_STREAMS_GET_STATUS_DATA; 2301 2302 typedef union { 2303 __C89_NAMELESS struct { 2304 ULONG NSR : 16; 2305 ULONG Reserved : 16; 2306 }; 2307 ULONG AsUlong; 2308 } NVME_CDW12_DIRECTIVE_RECEIVE_STREAMS_ALLOCATE_RESOURCES, *PNVME_CDW12_DIRECTIVE_RECEIVE_STREAMS_ALLOCATE_RESOURCES; 2309 2310 typedef struct { 2311 __C89_NAMELESS struct { 2312 ULONG NSA : 16; 2313 ULONG Reserved : 16; 2314 }; 2315 ULONG AsUlong; 2316 } NVME_COMPLETION_DW0_DIRECTIVE_RECEIVE_STREAMS_ALLOCATE_RESOURCES, *PNVME_COMPLETION_DW0_DIRECTIVE_RECEIVE_STREAMS_ALLOCATE_RESOURCES; 2317 2318 typedef union { 2319 NVME_CDW12_DIRECTIVE_SEND_IDENTIFY_ENABLE_DIRECTIVE EnableDirective; 2320 ULONG AsUlong; 2321 } NVME_CDW12_DIRECTIVE_SEND; 2322 2323 typedef union { 2324 NVME_CDW12_DIRECTIVE_RECEIVE_STREAMS_ALLOCATE_RESOURCES AllocateResources; 2325 ULONG AsUlong; 2326 } NVME_CDW12_DIRECTIVE_RECEIVE; 2327 2328 typedef union { 2329 __C89_NAMELESS struct { 2330 ULONG Reserved0 : 8; 2331 ULONG SPSP : 16; 2332 ULONG SECP : 8; 2333 }; 2334 ULONG AsUlong; 2335 } NVME_CDW10_SECURITY_SEND_RECEIVE, *PNVME_CDW10_SECURITY_SEND_RECEIVE; 2336 2337 typedef struct { 2338 ULONG TL; 2339 } NVME_CDW11_SECURITY_SEND, *PNVME_CDW11_SECURITY_SEND; 2340 2341 typedef struct { 2342 ULONG AL; 2343 } NVME_CDW11_SECURITY_RECEIVE, *PNVME_CDW11_SECURITY_RECEIVE; 2344 2345 typedef enum { 2346 NVME_NVM_COMMAND_FLUSH = 0x00, 2347 NVME_NVM_COMMAND_WRITE = 0x01, 2348 NVME_NVM_COMMAND_READ = 0x02, 2349 NVME_NVM_COMMAND_WRITE_UNCORRECTABLE = 0x04, 2350 NVME_NVM_COMMAND_COMPARE = 0x05, 2351 NVME_NVM_COMMAND_WRITE_ZEROES = 0x08, 2352 NVME_NVM_COMMAND_DATASET_MANAGEMENT = 0x09, 2353 NVME_NVM_COMMAND_VERIFY = 0x0C, 2354 NVME_NVM_COMMAND_RESERVATION_REGISTER = 0x0D, 2355 NVME_NVM_COMMAND_RESERVATION_REPORT = 0x0E, 2356 NVME_NVM_COMMAND_RESERVATION_ACQUIRE = 0x11, 2357 NVME_NVM_COMMAND_RESERVATION_RELEASE = 0x15, 2358 NVME_NVM_COMMAND_COPY = 0x19, 2359 NVME_NVM_COMMAND_ZONE_MANAGEMENT_SEND = 0x79, 2360 NVME_NVM_COMMAND_ZONE_MANAGEMENT_RECEIVE = 0x7A, 2361 NVME_NVM_COMMAND_ZONE_APPEND = 0x7D 2362 } NVME_NVM_COMMANDS; 2363 2364 typedef union { 2365 __C89_NAMELESS struct { 2366 ULONG NLB : 16; 2367 ULONG Reserved0 : 4; 2368 ULONG DTYPE : 4; 2369 ULONG Reserved1 : 2; 2370 ULONG PRINFO : 4; 2371 ULONG FUA : 1; 2372 ULONG LR : 1; 2373 }; 2374 ULONG AsUlong; 2375 } NVME_CDW12_READ_WRITE, *PNVME_CDW12_READ_WRITE; 2376 2377 typedef enum { 2378 NVME_ACCESS_FREQUENCY_NONE = 0, 2379 NVME_ACCESS_FREQUENCY_TYPICAL = 1, 2380 NVME_ACCESS_FREQUENCY_INFR_WRITE_INFR_READ = 2, 2381 NVME_ACCESS_FREQUENCY_INFR_WRITE_FR_READ = 3, 2382 NVME_ACCESS_FREQUENCY_FR_WRITE_INFR_READ = 4, 2383 NVME_ACCESS_FREQUENCY_FR_WRITE_FR_READ = 5, 2384 NVME_ACCESS_FREQUENCY_ONE_TIME_READ = 6, 2385 NVME_ACCESS_FREQUENCY_SPECULATIVE_READ = 7, 2386 NVME_ACCESS_FREQUENCY_WILL_BE_OVERWRITTEN = 8 2387 } NVME_ACCESS_FREQUENCIES; 2388 2389 typedef enum { 2390 NVME_ACCESS_LATENCY_NONE = 0, 2391 NVME_ACCESS_LATENCY_IDLE = 1, 2392 NVME_ACCESS_LATENCY_NORMAL = 2, 2393 NVME_ACCESS_LATENCY_LOW = 3 2394 } NVME_ACCESS_LATENCIES; 2395 2396 typedef union { 2397 __C89_NAMELESS struct { 2398 struct { 2399 UCHAR AccessFrequency : 4; 2400 UCHAR AccessLatency : 2; 2401 UCHAR SequentialRequest : 1; 2402 UCHAR Incompressible : 1; 2403 } DSM; 2404 UCHAR Reserved; 2405 USHORT DSPEC; 2406 }; 2407 ULONG AsUlong; 2408 } NVME_CDW13_READ_WRITE, *PNVME_CDW13_READ_WRITE; 2409 2410 typedef union { 2411 __C89_NAMELESS struct { 2412 ULONG ELBAT : 16; 2413 ULONG ELBATM : 16; 2414 }; 2415 ULONG AsUlong; 2416 } NVME_CDW15_READ_WRITE, *PNVME_CDW15_READ_WRITE; 2417 2418 typedef union { 2419 __C89_NAMELESS struct { 2420 ULONG AccessFrequency : 4; 2421 ULONG AccessLatency : 2; 2422 ULONG Reserved0 : 2; 2423 ULONG SequentialReadRange : 1; 2424 ULONG SequentialWriteRange : 1; 2425 ULONG WritePrepare : 1; 2426 ULONG Reserved1 : 13; 2427 ULONG CommandAccessSize : 8; 2428 }; 2429 ULONG AsUlong; 2430 } NVME_CONTEXT_ATTRIBUTES, *PNVME_CONTEXT_ATTRIBUTES; 2431 2432 typedef struct { 2433 NVME_CONTEXT_ATTRIBUTES Attributes; 2434 ULONG LogicalBlockCount; 2435 ULONGLONG StartingLBA; 2436 } NVME_LBA_RANGE, *PNVME_LBA_RANGE; 2437 2438 typedef union { 2439 __C89_NAMELESS struct { 2440 ULONG NR : 8; 2441 ULONG Reserved : 24; 2442 }; 2443 ULONG AsUlong; 2444 } NVME_CDW10_DATASET_MANAGEMENT, *PNVME_CDW10_DATASET_MANAGEMENT; 2445 2446 typedef union { 2447 __C89_NAMELESS struct { 2448 ULONG IDR : 1; 2449 ULONG IDW : 1; 2450 ULONG AD : 1; 2451 ULONG Reserved : 29; 2452 }; 2453 ULONG AsUlong; 2454 } NVME_CDW11_DATASET_MANAGEMENT, *PNVME_CDW11_DATASET_MANAGEMENT; 2455 2456 typedef struct { 2457 __C89_NAMELESS struct { 2458 UCHAR ZT : 4; 2459 UCHAR Reserved1 : 4; 2460 }; 2461 __C89_NAMELESS struct { 2462 UCHAR Reserved2 : 4; 2463 UCHAR ZS : 4; 2464 }; 2465 struct { 2466 UCHAR ZFC : 1; 2467 UCHAR FZR : 1; 2468 UCHAR RZR : 1; 2469 UCHAR Reserved : 4; 2470 UCHAR ZDEV : 1; 2471 } ZA; 2472 UCHAR Reserved3[5]; 2473 ULONGLONG ZCAP; 2474 ULONGLONG ZSLBA; 2475 ULONGLONG WritePointer; 2476 UCHAR Reserved4[32]; 2477 } NVME_ZONE_DESCRIPTOR, *PNVME_ZONE_DESCRIPTOR; 2478 2479 typedef enum { 2480 NVME_STATE_ZSE = 0x1, 2481 NVME_STATE_ZSIO = 0x2, 2482 NVME_STATE_ZSEO = 0x3, 2483 NVME_STATE_ZSC = 0x4, 2484 NVME_STATE_ZSRO = 0xD, 2485 NVME_STATE_ZSF = 0xE, 2486 NVME_STATE_ZSO = 0xF 2487 } ZONE_STATE; 2488 2489 typedef enum { 2490 NVME_ZONE_SEND_CLOSE = 1, 2491 NVME_ZONE_SEND_FINISH = 2, 2492 NVME_ZONE_SEND_OPEN = 3, 2493 NVME_ZONE_SEND_RESET = 4, 2494 NVME_ZONE_SEND_OFFLINE = 5, 2495 NVME_ZONE_SEND_SET_ZONE_DESCRIPTOR = 0x10 2496 } NVME_ZONE_SEND_ACTION; 2497 2498 typedef struct { 2499 ULONGLONG SLBA; 2500 } NVME_CDW10_ZONE_MANAGEMENT_SEND, *PNVME_CDW10_ZONE_MANAGEMENT_SEND; 2501 2502 typedef union { 2503 __C89_NAMELESS struct { 2504 ULONG ZSA : 8; 2505 ULONG SelectAll : 1; 2506 ULONG Reserved : 23; 2507 }; 2508 ULONG AsUlong; 2509 } NVME_CDW13_ZONE_MANAGEMENT_SEND, *PNVME_CDW13_ZONE_MANAGEMENT_SEND; 2510 2511 typedef struct { 2512 ULONGLONG ZoneCount; 2513 ULONGLONG Reserved[7]; 2514 NVME_ZONE_DESCRIPTOR ZoneDescriptor[ANYSIZE_ARRAY]; 2515 } NVME_REPORT_ZONE_INFO, *PNVME_REPORT_ZONE_INFO; 2516 2517 typedef struct{ 2518 UCHAR ZoneDescriptorExtensionInfo[64]; 2519 } NVME_ZONE_DESCRIPTOR_EXTENSION, *PNVME_ZONE_DESCRIPTOR_EXTENSION; 2520 2521 typedef struct { 2522 NVME_ZONE_DESCRIPTOR ZoneDescriptor; 2523 NVME_ZONE_DESCRIPTOR_EXTENSION ZoneDescriptorExtension[ANYSIZE_ARRAY]; 2524 } NVME_ZONE_EXTENDED_REPORT_ZONE_DESC, *PNVME_ZONE_EXTENDED_REPORT_ZONE_DESC; 2525 2526 typedef struct { 2527 ULONGLONG ZoneCount; 2528 ULONGLONG Reserved[7]; 2529 NVME_ZONE_EXTENDED_REPORT_ZONE_DESC Desc[ANYSIZE_ARRAY]; 2530 } NVME_EXTENDED_REPORT_ZONE_INFO, *PNVME_EXTENDED_REPORT_ZONE_INFO; 2531 2532 typedef enum { 2533 NVME_ZONE_RECEIVE_REPORT_ZONES = 0, 2534 NVME_ZONE_RECEIVE_EXTENDED_REPORT_ZONES = 1 2535 } NVME_ZONE_RECEIVE_ACTION; 2536 2537 typedef enum { 2538 NVME_ZRA_ALL_ZONES = 0, 2539 NVME_ZRA_EMPTY_STATE_ZONES = 1, 2540 NVME_ZRA_IO_STATE_ZONES = 2, 2541 NVME_ZRA_EO_STATE_ZONES = 3, 2542 NVME_ZRA_CLOSED_STATE_ZONES = 4, 2543 NVME_ZRA_FULL_STATE_ZONES = 5, 2544 NVME_ZRA_RO_STATE_ZONES = 6, 2545 NVME_ZRA_OFFLINE_STATE_ZONES = 7 2546 } NVME_ZONE_RECEIVE_ACTION_SPECIFIC; 2547 2548 typedef struct { 2549 ULONGLONG SLBA; 2550 } NVME_CDW10_ZONE_MANAGEMENT_RECEIVE, *PNVME_CDW10_ZONE_MANAGEMENT_RECEIVE; 2551 2552 typedef union { 2553 __C89_NAMELESS struct { 2554 ULONG ZRA : 8; 2555 ULONG ZRASpecific : 8; 2556 ULONG Partial : 1; 2557 ULONG Reserved : 15; 2558 }; 2559 ULONG AsUlong; 2560 } NVME_CDW13_ZONE_MANAGEMENT_RECEIVE, *PNVME_CDW13_ZONE_MANAGEMENT_RECEIVE; 2561 2562 typedef struct { 2563 ULONGLONG SLBA; 2564 } NVME_CDW10_ZONE_APPEND, *PNVME_CDW10_ZONE_APPEND; 2565 2566 typedef union { 2567 __C89_NAMELESS struct { 2568 ULONG NLB : 16; 2569 ULONG Reserved : 9; 2570 ULONG PIREMAP : 1; 2571 ULONG PRINFO : 4; 2572 ULONG FUA : 1; 2573 ULONG LR : 1; 2574 }; 2575 ULONG AsUlong; 2576 } NVME_CDW12_ZONE_APPEND, *PNVME_CDW12_ZONE_APPEND; 2577 2578 typedef union { 2579 __C89_NAMELESS struct { 2580 ULONG LBAT : 16; 2581 ULONG LBATM : 16; 2582 }; 2583 ULONG AsUlong; 2584 } NVME_CDW15_ZONE_APPEND, *PNVME_CDW15_ZONE_APPEND; 2585 2586 typedef union { 2587 __C89_NAMELESS struct { 2588 ULONG OPC : 8; 2589 ULONG FUSE : 2; 2590 ULONG Reserved0 : 5; 2591 ULONG PSDT : 1; 2592 ULONG CID : 16; 2593 }; 2594 ULONG AsUlong; 2595 } NVME_COMMAND_DWORD0, *PNVME_COMMAND_DWORD0; 2596 2597 typedef enum { 2598 NVME_FUSED_OPERATION_NORMAL = 0, 2599 NVME_FUSED_OPERATION_FIRST_CMD = 1, 2600 NVME_FUSED_OPERATION_SECOND_CMD = 2 2601 } NVME_FUSED_OPERATION_CODES; 2602 2603 typedef union { 2604 __C89_NAMELESS struct { 2605 ULONGLONG Reserved0 : 2; 2606 ULONGLONG PBAO : 62; 2607 }; 2608 ULONGLONG AsUlonglong; 2609 } NVME_PRP_ENTRY, *PNVME_PRP_ENTRY; 2610 2611 #define NVME_NAMESPACE_ALL 0xFFFFFFFF 2612 2613 typedef struct { 2614 NVME_COMMAND_DWORD0 CDW0; 2615 ULONG NSID; 2616 ULONG Reserved0[2]; 2617 ULONGLONG MPTR; 2618 ULONGLONG PRP1; 2619 ULONGLONG PRP2; 2620 union { 2621 struct { 2622 ULONG CDW10; 2623 ULONG CDW11; 2624 ULONG CDW12; 2625 ULONG CDW13; 2626 ULONG CDW14; 2627 ULONG CDW15; 2628 } GENERAL; 2629 struct { 2630 NVME_CDW10_IDENTIFY CDW10; 2631 NVME_CDW11_IDENTIFY CDW11; 2632 ULONG CDW12; 2633 ULONG CDW13; 2634 ULONG CDW14; 2635 ULONG CDW15; 2636 } IDENTIFY; 2637 struct { 2638 NVME_CDW10_ABORT CDW10; 2639 ULONG CDW11; 2640 ULONG CDW12; 2641 ULONG CDW13; 2642 ULONG CDW14; 2643 ULONG CDW15; 2644 } ABORT; 2645 struct { 2646 NVME_CDW10_GET_FEATURES CDW10; 2647 NVME_CDW11_FEATURES CDW11; 2648 ULONG CDW12; 2649 ULONG CDW13; 2650 ULONG CDW14; 2651 ULONG CDW15; 2652 } GETFEATURES; 2653 struct { 2654 NVME_CDW10_SET_FEATURES CDW10; 2655 NVME_CDW11_FEATURES CDW11; 2656 NVME_CDW12_FEATURES CDW12; 2657 NVME_CDW13_FEATURES CDW13; 2658 NVME_CDW14_FEATURES CDW14; 2659 NVME_CDW15_FEATURES CDW15; 2660 } SETFEATURES; 2661 struct { 2662 union { 2663 NVME_CDW10_GET_LOG_PAGE CDW10; 2664 NVME_CDW10_GET_LOG_PAGE_V13 CDW10_V13; 2665 }; 2666 NVME_CDW11_GET_LOG_PAGE CDW11; 2667 NVME_CDW12_GET_LOG_PAGE CDW12; 2668 NVME_CDW13_GET_LOG_PAGE CDW13; 2669 NVME_CDW14_GET_LOG_PAGE CDW14; 2670 ULONG CDW15; 2671 } GETLOGPAGE; 2672 struct { 2673 NVME_CDW10_CREATE_IO_QUEUE CDW10; 2674 NVME_CDW11_CREATE_IO_CQ CDW11; 2675 ULONG CDW12; 2676 ULONG CDW13; 2677 ULONG CDW14; 2678 ULONG CDW15; 2679 } CREATEIOCQ; 2680 struct { 2681 NVME_CDW10_CREATE_IO_QUEUE CDW10; 2682 NVME_CDW11_CREATE_IO_SQ CDW11; 2683 ULONG CDW12; 2684 ULONG CDW13; 2685 ULONG CDW14; 2686 ULONG CDW15; 2687 } CREATEIOSQ; 2688 struct { 2689 NVME_CDW10_DATASET_MANAGEMENT CDW10; 2690 NVME_CDW11_DATASET_MANAGEMENT CDW11; 2691 ULONG CDW12; 2692 ULONG CDW13; 2693 ULONG CDW14; 2694 ULONG CDW15; 2695 } DATASETMANAGEMENT; 2696 struct { 2697 NVME_CDW10_SECURITY_SEND_RECEIVE CDW10; 2698 NVME_CDW11_SECURITY_SEND CDW11; 2699 ULONG CDW12; 2700 ULONG CDW13; 2701 ULONG CDW14; 2702 ULONG CDW15; 2703 } SECURITYSEND; 2704 struct { 2705 NVME_CDW10_SECURITY_SEND_RECEIVE CDW10; 2706 NVME_CDW11_SECURITY_RECEIVE CDW11; 2707 ULONG CDW12; 2708 ULONG CDW13; 2709 ULONG CDW14; 2710 ULONG CDW15; 2711 } SECURITYRECEIVE; 2712 struct { 2713 NVME_CDW10_FIRMWARE_DOWNLOAD CDW10; 2714 NVME_CDW11_FIRMWARE_DOWNLOAD CDW11; 2715 ULONG CDW12; 2716 ULONG CDW13; 2717 ULONG CDW14; 2718 ULONG CDW15; 2719 } FIRMWAREDOWNLOAD; 2720 struct { 2721 NVME_CDW10_FIRMWARE_ACTIVATE CDW10; 2722 ULONG CDW11; 2723 ULONG CDW12; 2724 ULONG CDW13; 2725 ULONG CDW14; 2726 ULONG CDW15; 2727 } FIRMWAREACTIVATE; 2728 struct { 2729 NVME_CDW10_FORMAT_NVM CDW10; 2730 ULONG CDW11; 2731 ULONG CDW12; 2732 ULONG CDW13; 2733 ULONG CDW14; 2734 ULONG CDW15; 2735 } FORMATNVM; 2736 struct { 2737 NVME_CDW10_DIRECTIVE_RECEIVE CDW10; 2738 NVME_CDW11_DIRECTIVE_RECEIVE CDW11; 2739 NVME_CDW12_DIRECTIVE_RECEIVE CDW12; 2740 ULONG CDW13; 2741 ULONG CDW14; 2742 ULONG CDW15; 2743 } DIRECTIVERECEIVE; 2744 struct { 2745 NVME_CDW10_DIRECTIVE_SEND CDW10; 2746 NVME_CDW11_DIRECTIVE_SEND CDW11; 2747 NVME_CDW12_DIRECTIVE_SEND CDW12; 2748 ULONG CDW13; 2749 ULONG CDW14; 2750 ULONG CDW15; 2751 } DIRECTIVESEND; 2752 struct { 2753 NVME_CDW10_SANITIZE CDW10; 2754 NVME_CDW11_SANITIZE CDW11; 2755 ULONG CDW12; 2756 ULONG CDW13; 2757 ULONG CDW14; 2758 ULONG CDW15; 2759 } SANITIZE; 2760 struct { 2761 ULONG LBALOW; 2762 ULONG LBAHIGH; 2763 NVME_CDW12_READ_WRITE CDW12; 2764 NVME_CDW13_READ_WRITE CDW13; 2765 ULONG CDW14; 2766 NVME_CDW15_READ_WRITE CDW15; 2767 } READWRITE; 2768 struct { 2769 NVME_CDW10_RESERVATION_ACQUIRE CDW10; 2770 ULONG CDW11; 2771 ULONG CDW12; 2772 ULONG CDW13; 2773 ULONG CDW14; 2774 ULONG CDW15; 2775 } RESERVATIONACQUIRE; 2776 struct { 2777 NVME_CDW10_RESERVATION_REGISTER CDW10; 2778 ULONG CDW11; 2779 ULONG CDW12; 2780 ULONG CDW13; 2781 ULONG CDW14; 2782 ULONG CDW15; 2783 } RESERVATIONREGISTER; 2784 struct { 2785 NVME_CDW10_RESERVATION_RELEASE CDW10; 2786 ULONG CDW11; 2787 ULONG CDW12; 2788 ULONG CDW13; 2789 ULONG CDW14; 2790 ULONG CDW15; 2791 } RESERVATIONRELEASE; 2792 struct { 2793 NVME_CDW10_RESERVATION_REPORT CDW10; 2794 NVME_CDW11_RESERVATION_REPORT CDW11; 2795 ULONG CDW12; 2796 ULONG CDW13; 2797 ULONG CDW14; 2798 ULONG CDW15; 2799 } RESERVATIONREPORT; 2800 struct { 2801 NVME_CDW10_ZONE_MANAGEMENT_SEND CDW1011; 2802 ULONG CDW12; 2803 NVME_CDW13_ZONE_MANAGEMENT_SEND CDW13; 2804 ULONG CDW14; 2805 ULONG CDW15; 2806 } ZONEMANAGEMENTSEND; 2807 struct { 2808 NVME_CDW10_ZONE_MANAGEMENT_RECEIVE CDW1011; 2809 ULONG DWORDCOUNT; 2810 NVME_CDW13_ZONE_MANAGEMENT_RECEIVE CDW13; 2811 ULONG CDW14; 2812 ULONG CDW15; 2813 } ZONEMANAGEMENTRECEIVE; 2814 struct { 2815 NVME_CDW10_ZONE_APPEND CDW1011; 2816 NVME_CDW12_ZONE_APPEND CDW12; 2817 ULONG CDW13; 2818 ULONG ILBRT; 2819 NVME_CDW15_ZONE_APPEND CDW15; 2820 } ZONEAPPEND; 2821 } u; 2822 } NVME_COMMAND, *PNVME_COMMAND; 2823 2824 C_ASSERT(sizeof(NVME_COMMAND) == 64); 2825 2826 typedef struct { 2827 CHAR PCIVendorID[4]; 2828 CHAR ModelNumber[40]; 2829 CHAR NamespaceID[4]; 2830 CHAR SerialNumber[20]; 2831 } NVME_SCSI_NAME_STRING, *PNVME_SCSI_NAME_STRING; 2832 2833 #endif /* WINAPI_PARTITION_DESKTOP */ 2834 2835 #endif /* NVME_INCLUDED */