mfireg.h (54947B) - Raw
1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2006 IronPort Systems 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 /*- 29 * Copyright (c) 2007 LSI Corp. 30 * Copyright (c) 2007 Rajesh Prabhakaran. 31 * All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 42 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 43 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 44 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 45 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 46 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 47 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 48 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 49 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 50 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 51 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 52 * SUCH DAMAGE. 53 */ 54 55 #ifndef _MFIREG_H 56 #define _MFIREG_H 57 58 #include <sys/cdefs.h> 59 /* 60 * MegaRAID SAS MFI firmware definitions 61 * 62 * Calling this driver 'MegaRAID SAS' is a bit misleading. It's a completely 63 * new firmware interface from the old AMI MegaRAID one, and there is no 64 * reason why this interface should be limited to just SAS. In any case, LSI 65 * seems to also call this interface 'MFI', so that will be used here. 66 */ 67 #define MEGAMFI_FRAME_SIZE 64 68 /* 69 * Start with the register set. All registers are 32 bits wide. 70 * The usual Intel IOP style setup. 71 */ 72 #define MFI_IMSG0 0x10 /* Inbound message 0 */ 73 #define MFI_IMSG1 0x14 /* Inbound message 1 */ 74 #define MFI_OMSG0 0x18 /* Outbound message 0 */ 75 #define MFI_OMSG1 0x1c /* Outbound message 1 */ 76 #define MFI_IDB 0x20 /* Inbound doorbell */ 77 #define MFI_ISTS 0x24 /* Inbound interrupt status */ 78 #define MFI_IMSK 0x28 /* Inbound interrupt mask */ 79 #define MFI_ODB 0x2c /* Outbound doorbell */ 80 #define MFI_OSTS 0x30 /* Outbound interrupt status */ 81 #define MFI_OMSK 0x34 /* Outbound interrupt mask */ 82 #define MFI_IQP 0x40 /* Inbound queue port */ 83 #define MFI_OQP 0x44 /* Outbound queue port */ 84 85 /* 86 * ThunderBolt specific Register 87 */ 88 89 #define MFI_RFPI 0x48 /* reply_free_post_host_index */ 90 #define MFI_RPI 0x6c /* reply_post_host_index */ 91 #define MFI_ILQP 0xc0 /* inbound_low_queue_port */ 92 #define MFI_IHQP 0xc4 /* inbound_high_queue_port */ 93 94 /* 95 * 1078 specific related register 96 */ 97 #define MFI_ODR0 0x9c /* outbound doorbell register0 */ 98 #define MFI_ODCR0 0xa0 /* outbound doorbell clear register0 */ 99 #define MFI_OSP0 0xb0 /* outbound scratch pad0 */ 100 #define MFI_1078_EIM 0x80000004 /* 1078 enable interrupt mask */ 101 #define MFI_RMI 0x2 /* reply message interrupt */ 102 #define MFI_1078_RM 0x80000000 /* reply 1078 message interrupt */ 103 #define MFI_ODC 0x4 /* outbound doorbell change interrupt */ 104 105 /* OCR registers */ 106 #define MFI_WSR 0x004 /* write sequence register */ 107 #define MFI_HDR 0x008 /* host diagnostic register */ 108 #define MFI_RSR 0x3c3 /* Reset Status Register */ 109 110 /* 111 * GEN2 specific changes 112 */ 113 #define MFI_GEN2_EIM 0x00000005 /* GEN2 enable interrupt mask */ 114 #define MFI_GEN2_RM 0x00000001 /* reply GEN2 message interrupt */ 115 116 /* 117 * skinny specific changes 118 */ 119 #define MFI_SKINNY_IDB 0x00 /* Inbound doorbell is at 0x00 for skinny */ 120 #define MFI_IQPL 0x000000c0 121 #define MFI_IQPH 0x000000c4 122 #define MFI_SKINNY_RM 0x00000001 /* reply skinny message interrupt */ 123 124 /* Bits for MFI_OSTS */ 125 #define MFI_OSTS_INTR_VALID 0x00000002 126 127 /* OCR specific flags */ 128 #define MFI_FIRMWARE_STATE_CHANGE 0x00000002 129 #define MFI_STATE_CHANGE_INTERRUPT 0x00000004 /* MFI state change interrrupt */ 130 131 /* 132 * Firmware state values. Found in OMSG0 during initialization. 133 */ 134 #define MFI_FWSTATE_MASK 0xf0000000 135 #define MFI_FWSTATE_UNDEFINED 0x00000000 136 #define MFI_FWSTATE_BB_INIT 0x10000000 137 #define MFI_FWSTATE_FW_INIT 0x40000000 138 #define MFI_FWSTATE_WAIT_HANDSHAKE 0x60000000 139 #define MFI_FWSTATE_FW_INIT_2 0x70000000 140 #define MFI_FWSTATE_DEVICE_SCAN 0x80000000 141 #define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000 142 #define MFI_FWSTATE_FLUSH_CACHE 0xa0000000 143 #define MFI_FWSTATE_READY 0xb0000000 144 #define MFI_FWSTATE_OPERATIONAL 0xc0000000 145 #define MFI_FWSTATE_FAULT 0xf0000000 146 #define MFI_FWSTATE_MAXSGL_MASK 0x00ff0000 147 #define MFI_FWSTATE_MAXCMD_MASK 0x0000ffff 148 #define MFI_FWSTATE_HOSTMEMREQD_MASK 0x08000000 149 #define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000 150 #define MFI_RESET_REQUIRED 0x00000001 151 152 /* ThunderBolt Support */ 153 #define MFI_FWSTATE_TB_MASK 0xf0000000 154 #define MFI_FWSTATE_TB_RESET 0x00000000 155 #define MFI_FWSTATE_TB_READY 0x10000000 156 #define MFI_FWSTATE_TB_OPERATIONAL 0x20000000 157 #define MFI_FWSTATE_TB_FAULT 0x40000000 158 159 /* 160 * Control bits to drive the card to ready state. These go into the IDB 161 * register. 162 */ 163 #define MFI_FWINIT_ABORT 0x00000000 /* Abort all pending commands */ 164 #define MFI_FWINIT_READY 0x00000002 /* Move from operational to ready */ 165 #define MFI_FWINIT_MFIMODE 0x00000004 /* unknown */ 166 #define MFI_FWINIT_CLEAR_HANDSHAKE 0x00000008 /* Respond to WAIT_HANDSHAKE */ 167 #define MFI_FWINIT_HOTPLUG 0x00000010 168 169 /* ADP reset flags */ 170 #define MFI_STOP_ADP 0x00000020 171 #define MFI_ADP_RESET 0x00000040 172 #define DIAG_WRITE_ENABLE 0x00000080 173 #define DIAG_RESET_ADAPTER 0x00000004 174 175 /* MFI Commands */ 176 typedef enum { 177 MFI_CMD_INIT = 0x00, 178 MFI_CMD_LD_READ, 179 MFI_CMD_LD_WRITE, 180 MFI_CMD_LD_SCSI_IO, 181 MFI_CMD_PD_SCSI_IO, 182 MFI_CMD_DCMD, 183 MFI_CMD_ABORT, 184 MFI_CMD_SMP, 185 MFI_CMD_STP 186 } mfi_cmd_t; 187 188 /* Direct commands */ 189 typedef enum { 190 MFI_DCMD_CTRL_GETINFO = 0x01010000, 191 MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC =0x0100e100, 192 MFI_DCMD_CTRL_MFC_DEFAULTS_GET =0x010e0201, 193 MFI_DCMD_CTRL_MFC_DEFAULTS_SET =0x010e0202, 194 MFI_DCMD_CTRL_FLUSHCACHE = 0x01101000, 195 MFI_DCMD_CTRL_GET_PROPS = 0x01020100, 196 MFI_DCMD_CTRL_SET_PROPS = 0x01020200, 197 MFI_DCMD_CTRL_SHUTDOWN = 0x01050000, 198 MFI_DCMD_CTRL_EVENT_GETINFO = 0x01040100, 199 MFI_DCMD_CTRL_EVENT_GET = 0x01040300, 200 MFI_DCMD_CTRL_EVENT_WAIT = 0x01040500, 201 MFI_DCMD_PR_GET_STATUS = 0x01070100, 202 MFI_DCMD_PR_GET_PROPERTIES = 0x01070200, 203 MFI_DCMD_PR_SET_PROPERTIES = 0x01070300, 204 MFI_DCMD_PR_START = 0x01070400, 205 MFI_DCMD_PR_STOP = 0x01070500, 206 MFI_DCMD_TIME_SECS_GET = 0x01080201, 207 MFI_DCMD_FLASH_FW_OPEN = 0x010f0100, 208 MFI_DCMD_FLASH_FW_DOWNLOAD = 0x010f0200, 209 MFI_DCMD_FLASH_FW_FLASH = 0x010f0300, 210 MFI_DCMD_FLASH_FW_CLOSE = 0x010f0400, 211 MFI_DCMD_PD_GET_LIST = 0x02010000, 212 MFI_DCMD_PD_LIST_QUERY = 0x02010100, 213 MFI_DCMD_PD_GET_INFO = 0x02020000, 214 MFI_DCMD_PD_STATE_SET = 0x02030100, 215 MFI_DCMD_PD_REBUILD_START = 0x02040100, 216 MFI_DCMD_PD_REBUILD_ABORT = 0x02040200, 217 MFI_DCMD_PD_CLEAR_START = 0x02050100, 218 MFI_DCMD_PD_CLEAR_ABORT = 0x02050200, 219 MFI_DCMD_PD_GET_PROGRESS = 0x02060000, 220 MFI_DCMD_PD_LOCATE_START = 0x02070100, 221 MFI_DCMD_PD_LOCATE_STOP = 0x02070200, 222 MFI_DCMD_LD_MAP_GET_INFO = 0x0300e101, 223 MFI_DCMD_LD_SYNC = 0x0300e102, 224 MFI_DCMD_LD_GET_LIST = 0x03010000, 225 MFI_DCMD_LD_GET_INFO = 0x03020000, 226 MFI_DCMD_LD_GET_PROP = 0x03030000, 227 MFI_DCMD_LD_SET_PROP = 0x03040000, 228 MFI_DCMD_LD_INIT_START = 0x03060100, 229 MFI_DCMD_LD_DELETE = 0x03090000, 230 MFI_DCMD_CFG_READ = 0x04010000, 231 MFI_DCMD_CFG_ADD = 0x04020000, 232 MFI_DCMD_CFG_CLEAR = 0x04030000, 233 MFI_DCMD_CFG_MAKE_SPARE = 0x04040000, 234 MFI_DCMD_CFG_REMOVE_SPARE = 0x04050000, 235 MFI_DCMD_CFG_FOREIGN_SCAN = 0x04060100, 236 MFI_DCMD_CFG_FOREIGN_DISPLAY = 0x04060200, 237 MFI_DCMD_CFG_FOREIGN_PREVIEW = 0x04060300, 238 MFI_DCMD_CFG_FOREIGN_IMPORT = 0x04060400, 239 MFI_DCMD_CFG_FOREIGN_CLEAR = 0x04060500, 240 MFI_DCMD_BBU_GET_STATUS = 0x05010000, 241 MFI_DCMD_BBU_GET_CAPACITY_INFO =0x05020000, 242 MFI_DCMD_BBU_GET_DESIGN_INFO = 0x05030000, 243 MFI_DCMD_BBU_START_LEARN = 0x05040000, 244 MFI_DCMD_BBU_GET_PROP = 0x05050100, 245 MFI_DCMD_BBU_SET_PROP = 0x05050200, 246 MFI_DCMD_CLUSTER = 0x08000000, 247 MFI_DCMD_CLUSTER_RESET_ALL = 0x08010100, 248 MFI_DCMD_CLUSTER_RESET_LD = 0x08010200 249 } mfi_dcmd_t; 250 251 /* Modifiers for MFI_DCMD_CTRL_FLUSHCACHE */ 252 #define MFI_FLUSHCACHE_CTRL 0x01 253 #define MFI_FLUSHCACHE_DISK 0x02 254 255 /* Modifiers for MFI_DCMD_CTRL_SHUTDOWN */ 256 #define MFI_SHUTDOWN_SPINDOWN 0x01 257 258 /* 259 * MFI Frame flags 260 */ 261 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 262 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 263 #define MFI_FRAME_SGL32 0x0000 264 #define MFI_FRAME_SGL64 0x0002 265 #define MFI_FRAME_SENSE32 0x0000 266 #define MFI_FRAME_SENSE64 0x0004 267 #define MFI_FRAME_DIR_NONE 0x0000 268 #define MFI_FRAME_DIR_WRITE 0x0008 269 #define MFI_FRAME_DIR_READ 0x0010 270 #define MFI_FRAME_DIR_BOTH 0x0018 271 #define MFI_FRAME_IEEE_SGL 0x0020 272 #define MFI_FRAME_FMT "\20" \ 273 "\1NOPOST" \ 274 "\2SGL64" \ 275 "\3SENSE64" \ 276 "\4WRITE" \ 277 "\5READ" \ 278 "\6IEEESGL" 279 280 /* ThunderBolt Specific */ 281 282 /* 283 * Pre-TB command size and TB command size. 284 * We will be checking it at the load time for the time being 285 */ 286 #define MR_COMMAND_SIZE (MFI_FRAME_SIZE*20) /* 1280 bytes */ 287 288 #define MEGASAS_THUNDERBOLT_MSG_ALLIGNMENT 256 289 /* 290 * We are defining only 128 byte message to reduce memory move over head 291 * and also it will reduce the SRB extension size by 128byte compared with 292 * 256 message size 293 */ 294 #define MEGASAS_THUNDERBOLT_NEW_MSG_SIZE 256 295 #define MEGASAS_THUNDERBOLT_MAX_COMMANDS 1024 296 #define MEGASAS_THUNDERBOLT_MAX_REPLY_COUNT 1024 297 #define MEGASAS_THUNDERBOLT_REPLY_SIZE 8 298 #define MEGASAS_THUNDERBOLT_MAX_CHAIN_COUNT 1 299 #define MEGASAS_MAX_SZ_CHAIN_FRAME 1024 300 301 #define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 302 #define MPI2_FUNCTION_LD_IO_REQUEST 0xF1 303 304 #define MR_INTERNAL_MFI_FRAMES_SMID 1 305 #define MR_CTRL_EVENT_WAIT_SMID 2 306 #define MR_INTERNAL_DRIVER_RESET_SMID 3 307 308 /* MFI Status codes */ 309 typedef enum { 310 MFI_STAT_OK = 0x00, 311 MFI_STAT_INVALID_CMD, 312 MFI_STAT_INVALID_DCMD, 313 MFI_STAT_INVALID_PARAMETER, 314 MFI_STAT_INVALID_SEQUENCE_NUMBER, 315 MFI_STAT_ABORT_NOT_POSSIBLE, 316 MFI_STAT_APP_HOST_CODE_NOT_FOUND, 317 MFI_STAT_APP_IN_USE, 318 MFI_STAT_APP_NOT_INITIALIZED, 319 MFI_STAT_ARRAY_INDEX_INVALID, 320 MFI_STAT_ARRAY_ROW_NOT_EMPTY, 321 MFI_STAT_CONFIG_RESOURCE_CONFLICT, 322 MFI_STAT_DEVICE_NOT_FOUND, 323 MFI_STAT_DRIVE_TOO_SMALL, 324 MFI_STAT_FLASH_ALLOC_FAIL, 325 MFI_STAT_FLASH_BUSY, 326 MFI_STAT_FLASH_ERROR = 0x10, 327 MFI_STAT_FLASH_IMAGE_BAD, 328 MFI_STAT_FLASH_IMAGE_INCOMPLETE, 329 MFI_STAT_FLASH_NOT_OPEN, 330 MFI_STAT_FLASH_NOT_STARTED, 331 MFI_STAT_FLUSH_FAILED, 332 MFI_STAT_HOST_CODE_NOT_FOUNT, 333 MFI_STAT_LD_CC_IN_PROGRESS, 334 MFI_STAT_LD_INIT_IN_PROGRESS, 335 MFI_STAT_LD_LBA_OUT_OF_RANGE, 336 MFI_STAT_LD_MAX_CONFIGURED, 337 MFI_STAT_LD_NOT_OPTIMAL, 338 MFI_STAT_LD_RBLD_IN_PROGRESS, 339 MFI_STAT_LD_RECON_IN_PROGRESS, 340 MFI_STAT_LD_WRONG_RAID_LEVEL, 341 MFI_STAT_MAX_SPARES_EXCEEDED, 342 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 343 MFI_STAT_MFC_HW_ERROR, 344 MFI_STAT_NO_HW_PRESENT, 345 MFI_STAT_NOT_FOUND, 346 MFI_STAT_NOT_IN_ENCL, 347 MFI_STAT_PD_CLEAR_IN_PROGRESS, 348 MFI_STAT_PD_TYPE_WRONG, 349 MFI_STAT_PR_DISABLED, 350 MFI_STAT_ROW_INDEX_INVALID, 351 MFI_STAT_SAS_CONFIG_INVALID_ACTION, 352 MFI_STAT_SAS_CONFIG_INVALID_DATA, 353 MFI_STAT_SAS_CONFIG_INVALID_PAGE, 354 MFI_STAT_SAS_CONFIG_INVALID_TYPE, 355 MFI_STAT_SCSI_DONE_WITH_ERROR, 356 MFI_STAT_SCSI_IO_FAILED, 357 MFI_STAT_SCSI_RESERVATION_CONFLICT, 358 MFI_STAT_SHUTDOWN_FAILED = 0x30, 359 MFI_STAT_TIME_NOT_SET, 360 MFI_STAT_WRONG_STATE, 361 MFI_STAT_LD_OFFLINE, 362 MFI_STAT_PEER_NOTIFICATION_REJECTED, 363 MFI_STAT_PEER_NOTIFICATION_FAILED, 364 MFI_STAT_RESERVATION_IN_PROGRESS, 365 MFI_STAT_I2C_ERRORS_DETECTED, 366 MFI_STAT_PCI_ERRORS_DETECTED, 367 MFI_STAT_DIAG_FAILED, 368 MFI_STAT_BOOT_MSG_PENDING, 369 MFI_STAT_FOREIGN_CONFIG_INCOMPLETE, 370 MFI_STAT_INVALID_STATUS = 0xFF 371 } mfi_status_t; 372 373 typedef enum { 374 MFI_EVT_CLASS_DEBUG = -2, 375 MFI_EVT_CLASS_PROGRESS = -1, 376 MFI_EVT_CLASS_INFO = 0, 377 MFI_EVT_CLASS_WARNING = 1, 378 MFI_EVT_CLASS_CRITICAL = 2, 379 MFI_EVT_CLASS_FATAL = 3, 380 MFI_EVT_CLASS_DEAD = 4 381 } mfi_evt_class_t; 382 383 typedef enum { 384 MFI_EVT_LOCALE_LD = 0x0001, 385 MFI_EVT_LOCALE_PD = 0x0002, 386 MFI_EVT_LOCALE_ENCL = 0x0004, 387 MFI_EVT_LOCALE_BBU = 0x0008, 388 MFI_EVT_LOCALE_SAS = 0x0010, 389 MFI_EVT_LOCALE_CTRL = 0x0020, 390 MFI_EVT_LOCALE_CONFIG = 0x0040, 391 MFI_EVT_LOCALE_CLUSTER = 0x0080, 392 MFI_EVT_LOCALE_ALL = 0xffff 393 } mfi_evt_locale_t; 394 395 typedef enum { 396 MR_EVT_ARGS_NONE = 0x00, 397 MR_EVT_ARGS_CDB_SENSE, 398 MR_EVT_ARGS_LD, 399 MR_EVT_ARGS_LD_COUNT, 400 MR_EVT_ARGS_LD_LBA, 401 MR_EVT_ARGS_LD_OWNER, 402 MR_EVT_ARGS_LD_LBA_PD_LBA, 403 MR_EVT_ARGS_LD_PROG, 404 MR_EVT_ARGS_LD_STATE, 405 MR_EVT_ARGS_LD_STRIP, 406 MR_EVT_ARGS_PD, 407 MR_EVT_ARGS_PD_ERR, 408 MR_EVT_ARGS_PD_LBA, 409 MR_EVT_ARGS_PD_LBA_LD, 410 MR_EVT_ARGS_PD_PROG, 411 MR_EVT_ARGS_PD_STATE, 412 MR_EVT_ARGS_PCI, 413 MR_EVT_ARGS_RATE, 414 MR_EVT_ARGS_STR, 415 MR_EVT_ARGS_TIME, 416 MR_EVT_ARGS_ECC 417 } mfi_evt_args; 418 419 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 420 #define MR_EVT_PD_REMOVED 0x0070 421 #define MR_EVT_PD_INSERTED 0x005b 422 #define MR_EVT_LD_CHANGE 0x0051 423 424 typedef enum { 425 MR_LD_CACHE_WRITE_BACK = 0x01, 426 MR_LD_CACHE_WRITE_ADAPTIVE = 0x02, 427 MR_LD_CACHE_READ_AHEAD = 0x04, 428 MR_LD_CACHE_READ_ADAPTIVE = 0x08, 429 MR_LD_CACHE_WRITE_CACHE_BAD_BBU=0x10, 430 MR_LD_CACHE_ALLOW_WRITE_CACHE = 0x20, 431 MR_LD_CACHE_ALLOW_READ_CACHE = 0x40 432 } mfi_ld_cache; 433 #define MR_LD_CACHE_MASK 0x7f 434 435 #define MR_LD_CACHE_POLICY_READ_AHEAD_NONE 0 436 #define MR_LD_CACHE_POLICY_READ_AHEAD_ALWAYS MR_LD_CACHE_READ_AHEAD 437 #define MR_LD_CACHE_POLICY_READ_AHEAD_ADAPTIVE \ 438 (MR_LD_CACHE_READ_AHEAD | MR_LD_CACHE_READ_ADAPTIVE) 439 #define MR_LD_CACHE_POLICY_WRITE_THROUGH 0 440 #define MR_LD_CACHE_POLICY_WRITE_BACK MR_LD_CACHE_WRITE_BACK 441 #define MR_LD_CACHE_POLICY_IO_CACHED \ 442 (MR_LD_CACHE_ALLOW_WRITE_CACHE | MR_LD_CACHE_ALLOW_READ_CACHE) 443 #define MR_LD_CACHE_POLICY_IO_DIRECT 0 444 445 typedef enum { 446 MR_PD_CACHE_UNCHANGED = 0, 447 MR_PD_CACHE_ENABLE = 1, 448 MR_PD_CACHE_DISABLE = 2 449 } mfi_pd_cache; 450 451 typedef enum { 452 MR_PD_QUERY_TYPE_ALL = 0, 453 MR_PD_QUERY_TYPE_STATE = 1, 454 MR_PD_QUERY_TYPE_POWER_STATE = 2, 455 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 456 MR_PD_QUERY_TYPE_SPEED = 4, 457 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5 /*query for system drives */ 458 } mfi_pd_query_type; 459 460 /* 461 * Other propertities and definitions 462 */ 463 #define MFI_MAX_PD_CHANNELS 2 464 #define MFI_MAX_LD_CHANNELS 2 465 #define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 466 #define MFI_MAX_CHANNEL_DEVS 128 467 #define MFI_DEFAULT_ID -1 468 #define MFI_MAX_LUN 8 469 #define MFI_MAX_LD 64 470 #define MFI_MAX_PD 256 471 472 #define MFI_FRAME_SIZE 64 473 #define MFI_MBOX_SIZE 12 474 475 /* Firmware flashing can take 50+ seconds */ 476 #define MFI_POLL_TIMEOUT_SECS 60 477 478 /* Allow for speedier math calculations */ 479 #define MFI_SECTOR_LEN 512 480 481 /* Scatter Gather elements */ 482 struct mfi_sg32 { 483 uint32_t addr; 484 uint32_t len; 485 } __packed; 486 487 struct mfi_sg64 { 488 uint64_t addr; 489 uint32_t len; 490 } __packed; 491 492 struct mfi_sg_skinny { 493 uint64_t addr; 494 uint32_t len; 495 uint32_t flag; 496 } __packed; 497 498 union mfi_sgl { 499 struct mfi_sg32 sg32[1]; 500 struct mfi_sg64 sg64[1]; 501 struct mfi_sg_skinny sg_skinny[1]; 502 } __packed; 503 504 /* Message frames. All messages have a common header */ 505 struct mfi_frame_header { 506 uint8_t cmd; 507 uint8_t sense_len; 508 uint8_t cmd_status; 509 uint8_t scsi_status; 510 uint8_t target_id; 511 uint8_t lun_id; 512 uint8_t cdb_len; 513 uint8_t sg_count; 514 uint32_t context; 515 /* 516 * pad0 is MSI Specific. Not used by Driver. Zero the value before 517 * sending the command to f/w. 518 */ 519 uint32_t pad0; 520 uint16_t flags; 521 #define MFI_FRAME_DATAOUT 0x08 522 #define MFI_FRAME_DATAIN 0x10 523 uint16_t timeout; 524 uint32_t data_len; 525 } __packed; 526 527 struct mfi_init_frame { 528 struct mfi_frame_header header; 529 uint32_t qinfo_new_addr_lo; 530 uint32_t qinfo_new_addr_hi; 531 uint32_t qinfo_old_addr_lo; 532 uint32_t qinfo_old_addr_hi; 533 // Start LSIP200113393 534 uint32_t driver_ver_lo; /*28h */ 535 uint32_t driver_ver_hi; /*2Ch */ 536 537 uint32_t reserved[4]; 538 // End LSIP200113393 539 } __packed; 540 541 /* 542 * Define MFI Address Context union. 543 */ 544 #ifdef MFI_ADDRESS_IS_uint64_t 545 typedef uint64_t MFI_ADDRESS; 546 #else 547 typedef union _MFI_ADDRESS { 548 struct { 549 uint32_t addressLow; 550 uint32_t addressHigh; 551 } u; 552 uint64_t address; 553 } MFI_ADDRESS, *PMFI_ADDRESS; 554 #endif 555 556 #define MFI_IO_FRAME_SIZE 40 557 struct mfi_io_frame { 558 struct mfi_frame_header header; 559 uint32_t sense_addr_lo; 560 uint32_t sense_addr_hi; 561 uint32_t lba_lo; 562 uint32_t lba_hi; 563 union mfi_sgl sgl; 564 } __packed; 565 566 #define MFI_PASS_FRAME_SIZE 48 567 struct mfi_pass_frame { 568 struct mfi_frame_header header; 569 uint32_t sense_addr_lo; 570 uint32_t sense_addr_hi; 571 uint8_t cdb[16]; 572 union mfi_sgl sgl; 573 } __packed; 574 575 #define MFI_DCMD_FRAME_SIZE 40 576 struct mfi_dcmd_frame { 577 struct mfi_frame_header header; 578 uint32_t opcode; 579 uint8_t mbox[MFI_MBOX_SIZE]; 580 union mfi_sgl sgl; 581 } __packed; 582 583 struct mfi_abort_frame { 584 struct mfi_frame_header header; 585 uint32_t abort_context; 586 /* pad is changed to reserved.*/ 587 uint32_t reserved0; 588 uint32_t abort_mfi_addr_lo; 589 uint32_t abort_mfi_addr_hi; 590 uint32_t reserved1[6]; 591 } __packed; 592 593 struct mfi_smp_frame { 594 struct mfi_frame_header header; 595 uint64_t sas_addr; 596 union { 597 struct mfi_sg32 sg32[2]; 598 struct mfi_sg64 sg64[2]; 599 } sgl; 600 } __packed; 601 602 struct mfi_stp_frame { 603 struct mfi_frame_header header; 604 uint16_t fis[10]; 605 uint32_t stp_flags; 606 union { 607 struct mfi_sg32 sg32[2]; 608 struct mfi_sg64 sg64[2]; 609 } sgl; 610 } __packed; 611 612 union mfi_frame { 613 struct mfi_frame_header header; 614 struct mfi_init_frame init; 615 /* ThunderBolt Initialization */ 616 struct mfi_io_frame io; 617 struct mfi_pass_frame pass; 618 struct mfi_dcmd_frame dcmd; 619 struct mfi_abort_frame abort; 620 struct mfi_smp_frame smp; 621 struct mfi_stp_frame stp; 622 uint8_t bytes[MFI_FRAME_SIZE]; 623 }; 624 625 #define MFI_SENSE_LEN 128 626 struct mfi_sense { 627 uint8_t data[MFI_SENSE_LEN]; 628 }; 629 630 /* The queue init structure that is passed with the init message */ 631 struct mfi_init_qinfo { 632 uint32_t flags; 633 uint32_t rq_entries; 634 uint32_t rq_addr_lo; 635 uint32_t rq_addr_hi; 636 uint32_t pi_addr_lo; 637 uint32_t pi_addr_hi; 638 uint32_t ci_addr_lo; 639 uint32_t ci_addr_hi; 640 } __packed; 641 642 /* SAS (?) controller properties, part of mfi_ctrl_info */ 643 struct mfi_ctrl_props { 644 uint16_t seq_num; 645 uint16_t pred_fail_poll_interval; 646 uint16_t intr_throttle_cnt; 647 uint16_t intr_throttle_timeout; 648 uint8_t rebuild_rate; 649 uint8_t patrol_read_rate; 650 uint8_t bgi_rate; 651 uint8_t cc_rate; 652 uint8_t recon_rate; 653 uint8_t cache_flush_interval; 654 uint8_t spinup_drv_cnt; 655 uint8_t spinup_delay; 656 uint8_t cluster_enable; 657 uint8_t coercion_mode; 658 uint8_t alarm_enable; 659 uint8_t disable_auto_rebuild; 660 uint8_t disable_battery_warn; 661 uint8_t ecc_bucket_size; 662 uint16_t ecc_bucket_leak_rate; 663 uint8_t restore_hotspare_on_insertion; 664 uint8_t expose_encl_devices; 665 uint8_t maintainPdFailHistory; 666 uint8_t disallowHostRequestReordering; 667 /* set TRUE to abort CC on detecting an inconsistency */ 668 uint8_t abortCCOnError; 669 /* load balance mode (MR_LOAD_BALANCE_MODE) */ 670 uint8_t loadBalanceMode; 671 /* 672 * 0 - use auto detect logic of backplanes like SGPIO, i2c SEP using 673 * h/w mechansim like GPIO pins 674 * 1 - disable auto detect SGPIO, 675 * 2 - disable i2c SEP auto detect 676 * 3 - disable both auto detect 677 */ 678 uint8_t disableAutoDetectBackplane; 679 /* 680 * % of source LD to be reserved for a VDs snapshot in snapshot 681 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on 682 */ 683 uint8_t snapVDSpace; 684 685 /* 686 * Add properties that can be controlled by a bit in the following 687 * structure. 688 */ 689 struct { 690 /* set TRUE to disable copyBack (0=copback enabled) */ 691 uint32_t copyBackDisabled :1; 692 uint32_t SMARTerEnabled :1; 693 uint32_t prCorrectUnconfiguredAreas :1; 694 uint32_t useFdeOnly :1; 695 uint32_t disableNCQ :1; 696 uint32_t SSDSMARTerEnabled :1; 697 uint32_t SSDPatrolReadEnabled :1; 698 uint32_t enableSpinDownUnconfigured :1; 699 uint32_t autoEnhancedImport :1; 700 uint32_t enableSecretKeyControl :1; 701 uint32_t disableOnlineCtrlReset :1; 702 uint32_t allowBootWithPinnedCache :1; 703 uint32_t disableSpinDownHS :1; 704 uint32_t enableJBOD :1; 705 uint32_t reserved :18; 706 } OnOffProperties; 707 /* 708 * % of source LD to be reserved for auto snapshot in snapshot 709 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on. 710 */ 711 uint8_t autoSnapVDSpace; 712 /* 713 * Snapshot writeable VIEWs capacity as a % of source LD capacity: 714 * 0=READ only, 1=5%, 2=10%, 3=15% and so on. 715 */ 716 uint8_t viewSpace; 717 /* # of idle minutes before device is spun down (0=use FW defaults) */ 718 uint16_t spinDownTime; 719 uint8_t reserved[24]; 720 } __packed; 721 722 /* PCI information about the card. */ 723 struct mfi_info_pci { 724 uint16_t vendor; 725 uint16_t device; 726 uint16_t subvendor; 727 uint16_t subdevice; 728 uint8_t reserved[24]; 729 } __packed; 730 731 /* Host (front end) interface information */ 732 struct mfi_info_host { 733 uint8_t type; 734 #define MFI_INFO_HOST_PCIX 0x01 735 #define MFI_INFO_HOST_PCIE 0x02 736 #define MFI_INFO_HOST_ISCSI 0x04 737 #define MFI_INFO_HOST_SAS3G 0x08 738 uint8_t reserved[6]; 739 uint8_t port_count; 740 uint64_t port_addr[8]; 741 } __packed; 742 743 /* Device (back end) interface information */ 744 struct mfi_info_device { 745 uint8_t type; 746 #define MFI_INFO_DEV_SPI 0x01 747 #define MFI_INFO_DEV_SAS3G 0x02 748 #define MFI_INFO_DEV_SATA1 0x04 749 #define MFI_INFO_DEV_SATA3G 0x08 750 uint8_t reserved[6]; 751 uint8_t port_count; 752 uint64_t port_addr[8]; 753 } __packed; 754 755 /* Firmware component information */ 756 struct mfi_info_component { 757 char name[8]; 758 char version[32]; 759 char build_date[16]; 760 char build_time[16]; 761 } __packed; 762 763 /* Controller default settings */ 764 struct mfi_defaults { 765 uint64_t sas_addr; 766 uint8_t phy_polarity; 767 uint8_t background_rate; 768 uint8_t stripe_size; 769 uint8_t flush_time; 770 uint8_t write_back; 771 uint8_t read_ahead; 772 uint8_t cache_when_bbu_bad; 773 uint8_t cached_io; 774 uint8_t smart_mode; 775 uint8_t alarm_disable; 776 uint8_t coercion; 777 uint8_t zrc_config; 778 uint8_t dirty_led_shows_drive_activity; 779 uint8_t bios_continue_on_error; 780 uint8_t spindown_mode; 781 uint8_t allowed_device_types; 782 uint8_t allow_mix_in_enclosure; 783 uint8_t allow_mix_in_ld; 784 uint8_t allow_sata_in_cluster; 785 uint8_t max_chained_enclosures; 786 uint8_t disable_ctrl_r; 787 uint8_t enabel_web_bios; 788 uint8_t phy_polarity_split; 789 uint8_t direct_pd_mapping; 790 uint8_t bios_enumerate_lds; 791 uint8_t restored_hot_spare_on_insertion; 792 uint8_t expose_enclosure_devices; 793 uint8_t maintain_pd_fail_history; 794 uint8_t resv[28]; 795 } __packed; 796 797 /* Controller default settings */ 798 struct mfi_bios_data { 799 uint16_t boot_target_id; 800 uint8_t do_not_int_13; 801 uint8_t continue_on_error; 802 uint8_t verbose; 803 uint8_t geometry; 804 uint8_t expose_all_drives; 805 uint8_t reserved[56]; 806 uint8_t check_sum; 807 } __packed; 808 809 /* SAS (?) controller info, returned from MFI_DCMD_CTRL_GETINFO. */ 810 struct mfi_ctrl_info { 811 struct mfi_info_pci pci; 812 struct mfi_info_host host; 813 struct mfi_info_device device; 814 815 /* Firmware components that are present and active. */ 816 uint32_t image_check_word; 817 uint32_t image_component_count; 818 struct mfi_info_component image_component[8]; 819 820 /* Firmware components that have been flashed but are inactive */ 821 uint32_t pending_image_component_count; 822 struct mfi_info_component pending_image_component[8]; 823 824 uint8_t max_arms; 825 uint8_t max_spans; 826 uint8_t max_arrays; 827 uint8_t max_lds; 828 char product_name[80]; 829 char serial_number[32]; 830 uint32_t hw_present; 831 #define MFI_INFO_HW_BBU 0x01 832 #define MFI_INFO_HW_ALARM 0x02 833 #define MFI_INFO_HW_NVRAM 0x04 834 #define MFI_INFO_HW_UART 0x08 835 uint32_t current_fw_time; 836 uint16_t max_cmds; 837 uint16_t max_sg_elements; 838 uint32_t max_request_size; 839 uint16_t lds_present; 840 uint16_t lds_degraded; 841 uint16_t lds_offline; 842 uint16_t pd_present; 843 uint16_t pd_disks_present; 844 uint16_t pd_disks_pred_failure; 845 uint16_t pd_disks_failed; 846 uint16_t nvram_size; 847 uint16_t memory_size; 848 uint16_t flash_size; 849 uint16_t ram_correctable_errors; 850 uint16_t ram_uncorrectable_errors; 851 uint8_t cluster_allowed; 852 uint8_t cluster_active; 853 uint16_t max_strips_per_io; 854 855 uint32_t raid_levels; 856 #define MFI_INFO_RAID_0 0x01 857 #define MFI_INFO_RAID_1 0x02 858 #define MFI_INFO_RAID_5 0x04 859 #define MFI_INFO_RAID_1E 0x08 860 #define MFI_INFO_RAID_6 0x10 861 862 uint32_t adapter_ops; 863 #define MFI_INFO_AOPS_RBLD_RATE 0x0001 864 #define MFI_INFO_AOPS_CC_RATE 0x0002 865 #define MFI_INFO_AOPS_BGI_RATE 0x0004 866 #define MFI_INFO_AOPS_RECON_RATE 0x0008 867 #define MFI_INFO_AOPS_PATROL_RATE 0x0010 868 #define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 869 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 870 #define MFI_INFO_AOPS_BBU 0x0080 871 #define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 872 #define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 873 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 874 #define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 875 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 876 #define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 877 #define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 878 879 uint32_t ld_ops; 880 #define MFI_INFO_LDOPS_READ_POLICY 0x01 881 #define MFI_INFO_LDOPS_WRITE_POLICY 0x02 882 #define MFI_INFO_LDOPS_IO_POLICY 0x04 883 #define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 884 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 885 886 struct { 887 uint8_t min; 888 uint8_t max; 889 uint8_t reserved[2]; 890 } __packed stripe_sz_ops; 891 892 uint32_t pd_ops; 893 #define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 894 #define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 895 #define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 896 897 uint32_t pd_mix_support; 898 #define MFI_INFO_PDMIX_SAS 0x01 899 #define MFI_INFO_PDMIX_SATA 0x02 900 #define MFI_INFO_PDMIX_ENCL 0x04 901 #define MFI_INFO_PDMIX_LD 0x08 902 #define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 903 904 uint8_t ecc_bucket_count; 905 uint8_t reserved2[11]; 906 struct mfi_ctrl_props properties; 907 char package_version[0x60]; 908 uint8_t pad[0x800 - 0x6a0]; 909 } __packed; 910 911 /* keep track of an event. */ 912 union mfi_evt { 913 struct { 914 uint16_t locale; 915 uint8_t reserved; 916 int8_t evt_class; 917 } members; 918 uint32_t word; 919 } __packed; 920 921 /* event log state. */ 922 struct mfi_evt_log_state { 923 uint32_t newest_seq_num; 924 uint32_t oldest_seq_num; 925 uint32_t clear_seq_num; 926 uint32_t shutdown_seq_num; 927 uint32_t boot_seq_num; 928 } __packed; 929 930 struct mfi_progress { 931 uint16_t progress; 932 uint16_t elapsed_seconds; 933 } __packed; 934 935 struct mfi_evt_ld { 936 uint16_t target_id; 937 uint8_t ld_index; 938 uint8_t reserved; 939 } __packed; 940 941 struct mfi_evt_pd { 942 uint16_t device_id; 943 uint8_t enclosure_index; 944 uint8_t slot_number; 945 } __packed; 946 947 /* SAS (?) event detail, returned from MFI_DCMD_CTRL_EVENT_WAIT. */ 948 struct mfi_evt_detail { 949 uint32_t seq; 950 uint32_t time; 951 uint32_t code; 952 union mfi_evt evt_class; 953 uint8_t arg_type; 954 uint8_t reserved1[15]; 955 956 union { 957 struct { 958 struct mfi_evt_pd pd; 959 uint8_t cdb_len; 960 uint8_t sense_len; 961 uint8_t reserved[2]; 962 uint8_t cdb[16]; 963 uint8_t sense[64]; 964 } cdb_sense; 965 966 struct mfi_evt_ld ld; 967 968 struct { 969 struct mfi_evt_ld ld; 970 uint64_t count; 971 } ld_count; 972 973 struct { 974 uint64_t lba; 975 struct mfi_evt_ld ld; 976 } ld_lba; 977 978 struct { 979 struct mfi_evt_ld ld; 980 uint32_t pre_owner; 981 uint32_t new_owner; 982 } ld_owner; 983 984 struct { 985 uint64_t ld_lba; 986 uint64_t pd_lba; 987 struct mfi_evt_ld ld; 988 struct mfi_evt_pd pd; 989 } ld_lba_pd_lba; 990 991 struct { 992 struct mfi_evt_ld ld; 993 struct mfi_progress prog; 994 } ld_prog; 995 996 struct { 997 struct mfi_evt_ld ld; 998 uint32_t prev_state; 999 uint32_t new_state; 1000 } ld_state; 1001 1002 struct { 1003 uint64_t strip; 1004 struct mfi_evt_ld ld; 1005 } ld_strip; 1006 1007 struct mfi_evt_pd pd; 1008 1009 struct { 1010 struct mfi_evt_pd pd; 1011 uint32_t err; 1012 } pd_err; 1013 1014 struct { 1015 uint64_t lba; 1016 struct mfi_evt_pd pd; 1017 } pd_lba; 1018 1019 struct { 1020 uint64_t lba; 1021 struct mfi_evt_pd pd; 1022 struct mfi_evt_ld ld; 1023 } pd_lba_ld; 1024 1025 struct { 1026 struct mfi_evt_pd pd; 1027 struct mfi_progress prog; 1028 } pd_prog; 1029 1030 struct { 1031 struct mfi_evt_pd ld; 1032 uint32_t prev_state; 1033 uint32_t new_state; 1034 } pd_state; 1035 1036 struct { 1037 uint16_t venderId; 1038 uint16_t deviceId; 1039 uint16_t subVenderId; 1040 uint16_t subDeviceId; 1041 } pci; 1042 1043 uint32_t rate; 1044 1045 char str[96]; 1046 1047 struct { 1048 uint32_t rtc; 1049 uint16_t elapsedSeconds; 1050 } time; 1051 1052 struct { 1053 uint32_t ecar; 1054 uint32_t elog; 1055 char str[64]; 1056 } ecc; 1057 1058 uint8_t b[96]; 1059 uint16_t s[48]; 1060 uint32_t w[24]; 1061 uint64_t d[12]; 1062 } args; 1063 1064 char description[128]; 1065 } __packed; 1066 1067 struct mfi_evt_list { 1068 uint32_t count; 1069 uint32_t reserved; 1070 struct mfi_evt_detail event[1]; 1071 } __packed; 1072 1073 union mfi_pd_ref { 1074 struct { 1075 uint16_t device_id; 1076 uint16_t seq_num; 1077 } v; 1078 uint32_t ref; 1079 } __packed; 1080 1081 union mfi_pd_ddf_type { 1082 struct { 1083 union { 1084 struct { 1085 uint16_t forced_pd_guid : 1; 1086 uint16_t in_vd : 1; 1087 uint16_t is_global_spare : 1; 1088 uint16_t is_spare : 1; 1089 uint16_t is_foreign : 1; 1090 uint16_t reserved : 7; 1091 uint16_t intf : 4; 1092 } pd_type; 1093 uint16_t type; 1094 } v; 1095 uint16_t reserved; 1096 } ddf; 1097 struct { 1098 uint32_t reserved; 1099 } non_disk; 1100 uint32_t type; 1101 } __packed; 1102 1103 struct mfi_pd_progress { 1104 uint32_t active; 1105 #define MFI_PD_PROGRESS_REBUILD (1<<0) 1106 #define MFI_PD_PROGRESS_PATROL (1<<1) 1107 #define MFI_PD_PROGRESS_CLEAR (1<<2) 1108 struct mfi_progress rbld; 1109 struct mfi_progress patrol; 1110 struct mfi_progress clear; 1111 struct mfi_progress reserved[4]; 1112 } __packed; 1113 1114 struct mfi_pd_info { 1115 union mfi_pd_ref ref; 1116 uint8_t inquiry_data[96]; 1117 uint8_t vpd_page83[64]; 1118 uint8_t not_supported; 1119 uint8_t scsi_dev_type; 1120 uint8_t connected_port_bitmap; 1121 uint8_t device_speed; 1122 uint32_t media_err_count; 1123 uint32_t other_err_count; 1124 uint32_t pred_fail_count; 1125 uint32_t last_pred_fail_event_seq_num; 1126 uint16_t fw_state; /* MFI_PD_STATE_* */ 1127 uint8_t disabled_for_removal; 1128 uint8_t link_speed; 1129 union mfi_pd_ddf_type state; 1130 struct { 1131 uint8_t count; 1132 uint8_t is_path_broken; 1133 uint8_t reserved[6]; 1134 uint64_t sas_addr[4]; 1135 } path_info; 1136 uint64_t raw_size; 1137 uint64_t non_coerced_size; 1138 uint64_t coerced_size; 1139 uint16_t encl_device_id; 1140 uint8_t encl_index; 1141 uint8_t slot_number; 1142 struct mfi_pd_progress prog_info; 1143 uint8_t bad_block_table_full; 1144 uint8_t unusable_in_current_config; 1145 uint8_t vpd_page83_ext[64]; 1146 uint8_t reserved[512-358]; 1147 } __packed; 1148 1149 struct mfi_pd_address { 1150 uint16_t device_id; 1151 uint16_t encl_device_id; 1152 uint8_t encl_index; 1153 uint8_t slot_number; 1154 uint8_t scsi_dev_type; /* 0 = disk */ 1155 uint8_t connect_port_bitmap; 1156 uint64_t sas_addr[2]; 1157 } __packed; 1158 1159 #define MAX_SYS_PDS 240 1160 struct mfi_pd_list { 1161 uint32_t size; 1162 uint32_t count; 1163 struct mfi_pd_address addr[MAX_SYS_PDS]; 1164 } __packed; 1165 1166 enum mfi_pd_state { 1167 MFI_PD_STATE_UNCONFIGURED_GOOD = 0x00, 1168 MFI_PD_STATE_UNCONFIGURED_BAD = 0x01, 1169 MFI_PD_STATE_HOT_SPARE = 0x02, 1170 MFI_PD_STATE_OFFLINE = 0x10, 1171 MFI_PD_STATE_FAILED = 0x11, 1172 MFI_PD_STATE_REBUILD = 0x14, 1173 MFI_PD_STATE_ONLINE = 0x18, 1174 MFI_PD_STATE_COPYBACK = 0x20, 1175 MFI_PD_STATE_SYSTEM = 0x40 1176 }; 1177 1178 /* 1179 * "SYSTEM" disk appears to be "JBOD" support from the RAID controller. 1180 * Adding a #define to denote this. 1181 */ 1182 #define MFI_PD_STATE_JBOD MFI_PD_STATE_SYSTEM 1183 1184 union mfi_ld_ref { 1185 struct { 1186 uint8_t target_id; 1187 uint8_t reserved; 1188 uint16_t seq; 1189 } v; 1190 uint32_t ref; 1191 } __packed; 1192 1193 struct mfi_ld_list { 1194 uint32_t ld_count; 1195 uint32_t reserved1; 1196 struct { 1197 union mfi_ld_ref ld; 1198 uint8_t state; 1199 uint8_t reserved2[3]; 1200 uint64_t size; 1201 } ld_list[MFI_MAX_LD]; 1202 } __packed; 1203 1204 enum mfi_ld_access { 1205 MFI_LD_ACCESS_RW = 0, 1206 MFI_LD_ACCSSS_RO = 2, 1207 MFI_LD_ACCESS_BLOCKED = 3, 1208 }; 1209 #define MFI_LD_ACCESS_MASK 3 1210 1211 enum mfi_ld_state { 1212 MFI_LD_STATE_OFFLINE = 0, 1213 MFI_LD_STATE_PARTIALLY_DEGRADED = 1, 1214 MFI_LD_STATE_DEGRADED = 2, 1215 MFI_LD_STATE_OPTIMAL = 3 1216 }; 1217 1218 struct mfi_ld_props { 1219 union mfi_ld_ref ld; 1220 char name[16]; 1221 uint8_t default_cache_policy; 1222 uint8_t access_policy; 1223 uint8_t disk_cache_policy; 1224 uint8_t current_cache_policy; 1225 uint8_t no_bgi; 1226 uint8_t reserved[7]; 1227 } __packed; 1228 1229 struct mfi_ld_params { 1230 uint8_t primary_raid_level; 1231 uint8_t raid_level_qualifier; 1232 uint8_t secondary_raid_level; 1233 uint8_t stripe_size; 1234 uint8_t num_drives; 1235 uint8_t span_depth; 1236 uint8_t state; 1237 uint8_t init_state; 1238 #define MFI_LD_PARAMS_INIT_NO 0 1239 #define MFI_LD_PARAMS_INIT_QUICK 1 1240 #define MFI_LD_PARAMS_INIT_FULL 2 1241 uint8_t is_consistent; 1242 uint8_t reserved1[6]; 1243 uint8_t isSSCD; 1244 uint8_t reserved2[16]; 1245 } __packed; 1246 1247 struct mfi_ld_progress { 1248 uint32_t active; 1249 #define MFI_LD_PROGRESS_CC (1<<0) 1250 #define MFI_LD_PROGRESS_BGI (1<<1) 1251 #define MFI_LD_PROGRESS_FGI (1<<2) 1252 #define MFI_LD_PROGRESS_RECON (1<<3) 1253 struct mfi_progress cc; 1254 struct mfi_progress bgi; 1255 struct mfi_progress fgi; 1256 struct mfi_progress recon; 1257 struct mfi_progress reserved[4]; 1258 } __packed; 1259 1260 struct mfi_span { 1261 uint64_t start_block; 1262 uint64_t num_blocks; 1263 uint16_t array_ref; 1264 uint8_t reserved[6]; 1265 } __packed; 1266 1267 #define MFI_MAX_SPAN_DEPTH 8 1268 struct mfi_ld_config { 1269 struct mfi_ld_props properties; 1270 struct mfi_ld_params params; 1271 struct mfi_span span[MFI_MAX_SPAN_DEPTH]; 1272 } __packed; 1273 1274 struct mfi_ld_info { 1275 struct mfi_ld_config ld_config; 1276 uint64_t size; 1277 struct mfi_ld_progress progress; 1278 uint16_t cluster_owner; 1279 uint8_t reconstruct_active; 1280 uint8_t reserved1[1]; 1281 uint8_t vpd_page83[64]; 1282 uint8_t reserved2[16]; 1283 } __packed; 1284 1285 #define MFI_MAX_ARRAYS 16 1286 struct mfi_spare { 1287 union mfi_pd_ref ref; 1288 uint8_t spare_type; 1289 #define MFI_SPARE_DEDICATED (1 << 0) 1290 #define MFI_SPARE_REVERTIBLE (1 << 1) 1291 #define MFI_SPARE_ENCL_AFFINITY (1 << 2) 1292 uint8_t reserved[2]; 1293 uint8_t array_count; 1294 uint16_t array_ref[MFI_MAX_ARRAYS]; 1295 } __packed; 1296 1297 #define MFI_MAX_ROW_SIZE 32 1298 struct mfi_array { 1299 uint64_t size; 1300 uint8_t num_drives; 1301 uint8_t reserved; 1302 uint16_t array_ref; 1303 uint8_t pad[20]; 1304 struct { 1305 union mfi_pd_ref ref; /* 0xffff == missing drive */ 1306 uint16_t fw_state; /* MFI_PD_STATE_* */ 1307 struct { 1308 uint8_t pd; 1309 uint8_t slot; 1310 } encl; 1311 } pd[MFI_MAX_ROW_SIZE]; 1312 } __packed; 1313 1314 struct mfi_config_data { 1315 uint32_t size; 1316 uint16_t array_count; 1317 uint16_t array_size; 1318 uint16_t log_drv_count; 1319 uint16_t log_drv_size; 1320 uint16_t spares_count; 1321 uint16_t spares_size; 1322 uint8_t reserved[16]; 1323 struct mfi_array array[0]; 1324 struct mfi_ld_config ld[0]; 1325 struct mfi_spare spare[0]; 1326 } __packed; 1327 1328 struct mfi_bbu_capacity_info { 1329 uint16_t relative_charge; 1330 uint16_t absolute_charge; 1331 uint16_t remaining_capacity; 1332 uint16_t full_charge_capacity; 1333 uint16_t run_time_to_empty; 1334 uint16_t average_time_to_empty; 1335 uint16_t average_time_to_full; 1336 uint16_t cycle_count; 1337 uint16_t max_error; 1338 uint16_t remaining_capacity_alarm; 1339 uint16_t remaining_time_alarm; 1340 uint8_t reserved[26]; 1341 } __packed; 1342 1343 struct mfi_bbu_design_info { 1344 uint32_t mfg_date; 1345 uint16_t design_capacity; 1346 uint16_t design_voltage; 1347 uint16_t spec_info; 1348 uint16_t serial_number; 1349 uint16_t pack_stat_config; 1350 uint8_t mfg_name[12]; 1351 uint8_t device_name[8]; 1352 uint8_t device_chemistry[8]; 1353 uint8_t mfg_data[8]; 1354 uint8_t reserved[17]; 1355 } __packed; 1356 1357 struct mfi_ibbu_state { 1358 uint16_t gas_guage_status; 1359 uint16_t relative_charge; 1360 uint16_t charger_system_state; 1361 uint16_t charger_system_ctrl; 1362 uint16_t charging_current; 1363 uint16_t absolute_charge; 1364 uint16_t max_error; 1365 uint8_t reserved[18]; 1366 } __packed; 1367 1368 struct mfi_bbu_state { 1369 uint16_t gas_guage_status; 1370 uint16_t relative_charge; 1371 uint16_t charger_status; 1372 uint16_t remaining_capacity; 1373 uint16_t full_charge_capacity; 1374 uint8_t is_SOH_good; 1375 uint8_t reserved[21]; 1376 } __packed; 1377 1378 struct mfi_bbu_properties { 1379 uint32_t auto_learn_period; 1380 uint32_t next_learn_time; 1381 uint8_t learn_delay_interval; 1382 uint8_t auto_learn_mode; 1383 uint8_t bbu_mode; 1384 uint8_t reserved[21]; 1385 } __packed; 1386 1387 union mfi_bbu_status_detail { 1388 struct mfi_ibbu_state ibbu; 1389 struct mfi_bbu_state bbu; 1390 }; 1391 1392 struct mfi_bbu_status { 1393 uint8_t battery_type; 1394 #define MFI_BBU_TYPE_NONE 0 1395 #define MFI_BBU_TYPE_IBBU 1 1396 #define MFI_BBU_TYPE_BBU 2 1397 uint8_t reserved; 1398 uint16_t voltage; 1399 int16_t current; 1400 uint16_t temperature; 1401 uint32_t fw_status; 1402 #define MFI_BBU_STATE_PACK_MISSING (1 << 0) 1403 #define MFI_BBU_STATE_VOLTAGE_LOW (1 << 1) 1404 #define MFI_BBU_STATE_TEMPERATURE_HIGH (1 << 2) 1405 #define MFI_BBU_STATE_CHARGE_ACTIVE (1 << 3) 1406 #define MFI_BBU_STATE_DISCHARGE_ACTIVE (1 << 4) 1407 #define MFI_BBU_STATE_LEARN_CYC_REQ (1 << 5) 1408 #define MFI_BBU_STATE_LEARN_CYC_ACTIVE (1 << 6) 1409 #define MFI_BBU_STATE_LEARN_CYC_FAIL (1 << 7) 1410 #define MFI_BBU_STATE_LEARN_CYC_TIMEOUT (1 << 8) 1411 #define MFI_BBU_STATE_I2C_ERR_DETECT (1 << 9) 1412 uint8_t pad[20]; 1413 union mfi_bbu_status_detail detail; 1414 } __packed; 1415 1416 enum mfi_pr_state { 1417 MFI_PR_STATE_STOPPED = 0, 1418 MFI_PR_STATE_READY = 1, 1419 MFI_PR_STATE_ACTIVE = 2, 1420 MFI_PR_STATE_ABORTED = 0xff 1421 }; 1422 1423 struct mfi_pr_status { 1424 uint32_t num_iteration; 1425 uint8_t state; 1426 uint8_t num_pd_done; 1427 uint8_t reserved[10]; 1428 }; 1429 1430 enum mfi_pr_opmode { 1431 MFI_PR_OPMODE_AUTO = 0, 1432 MFI_PR_OPMODE_MANUAL = 1, 1433 MFI_PR_OPMODE_DISABLED = 2 1434 }; 1435 1436 struct mfi_pr_properties { 1437 uint8_t op_mode; 1438 uint8_t max_pd; 1439 uint8_t reserved; 1440 uint8_t exclude_ld_count; 1441 uint16_t excluded_ld[MFI_MAX_LD]; 1442 uint8_t cur_pd_map[MFI_MAX_PD / 8]; 1443 uint8_t last_pd_map[MFI_MAX_PD / 8]; 1444 uint32_t next_exec; 1445 uint32_t exec_freq; 1446 uint32_t clear_freq; 1447 }; 1448 1449 /* ThunderBolt support */ 1450 1451 /* 1452 * Raid Context structure which describes MegaRAID specific IO Paramenters 1453 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 1454 */ 1455 typedef struct _MPI2_SCSI_IO_VENDOR_UNIQUE { 1456 uint16_t resvd0; /* 0x00 - 0x01 */ 1457 uint16_t timeoutValue; /* 0x02 - 0x03 */ 1458 uint8_t regLockFlags; 1459 uint8_t armId; 1460 uint16_t TargetID; /* 0x06 - 0x07 */ 1461 1462 uint64_t RegLockLBA; /* 0x08 - 0x0F */ 1463 1464 uint32_t RegLockLength; /* 0x10 - 0x13 */ 1465 1466 uint16_t SMID; /* 0x14 - 0x15 nextLMId */ 1467 uint8_t exStatus; /* 0x16 */ 1468 uint8_t Status; /* 0x17 status */ 1469 1470 uint8_t RAIDFlags; /* 0x18 */ 1471 uint8_t numSGE; /* 0x19 numSge */ 1472 uint16_t configSeqNum; /* 0x1A - 0x1B */ 1473 uint8_t spanArm; /* 0x1C */ 1474 uint8_t resvd2[3]; /* 0x1D - 0x1F */ 1475 } MPI2_SCSI_IO_VENDOR_UNIQUE, MPI25_SCSI_IO_VENDOR_UNIQUE; 1476 1477 /***************************************************************************** 1478 * 1479 * Message Functions 1480 * 1481 *****************************************************************************/ 1482 1483 #define NA_MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 1484 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 1485 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 1486 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 1487 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 1488 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 1489 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 1490 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 1491 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 1492 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 1493 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 1494 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 1495 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 1496 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 1497 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 1498 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 1499 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 1500 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 1501 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 1502 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ 1503 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 1504 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 1505 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 1506 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 1507 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 1508 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ 1509 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ 1510 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ 1511 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ 1512 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ 1513 1514 /* Doorbell functions */ 1515 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 1516 #define MPI2_FUNCTION_HANDSHAKE (0x42) 1517 1518 /***************************************************************************** 1519 * 1520 * MPI Version Definitions 1521 * 1522 *****************************************************************************/ 1523 1524 #define MPI2_VERSION_MAJOR (0x02) 1525 #define MPI2_VERSION_MINOR (0x00) 1526 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 1527 #define MPI2_VERSION_MAJOR_SHIFT (8) 1528 #define MPI2_VERSION_MINOR_MASK (0x00FF) 1529 #define MPI2_VERSION_MINOR_SHIFT (0) 1530 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 1531 MPI2_VERSION_MINOR) 1532 1533 #define MPI2_VERSION_02_00 (0x0200) 1534 1535 /* versioning for this MPI header set */ 1536 #define MPI2_HEADER_VERSION_UNIT (0x10) 1537 #define MPI2_HEADER_VERSION_DEV (0x00) 1538 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 1539 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 1540 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 1541 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 1542 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 1543 MPI2_HEADER_VERSION_DEV) 1544 1545 /* IOCInit Request message */ 1546 struct MPI2_IOC_INIT_REQUEST { 1547 uint8_t WhoInit; /* 0x00 */ 1548 uint8_t Reserved1; /* 0x01 */ 1549 uint8_t ChainOffset; /* 0x02 */ 1550 uint8_t Function; /* 0x03 */ 1551 uint16_t Reserved2; /* 0x04 */ 1552 uint8_t Reserved3; /* 0x06 */ 1553 uint8_t MsgFlags; /* 0x07 */ 1554 uint8_t VP_ID; /* 0x08 */ 1555 uint8_t VF_ID; /* 0x09 */ 1556 uint16_t Reserved4; /* 0x0A */ 1557 uint16_t MsgVersion; /* 0x0C */ 1558 uint16_t HeaderVersion; /* 0x0E */ 1559 uint32_t Reserved5; /* 0x10 */ 1560 uint16_t Reserved6; /* 0x14 */ 1561 uint8_t Reserved7; /* 0x16 */ 1562 uint8_t HostMSIxVectors; /* 0x17 */ 1563 uint16_t Reserved8; /* 0x18 */ 1564 uint16_t SystemRequestFrameSize; /* 0x1A */ 1565 uint16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 1566 uint16_t ReplyFreeQueueDepth; /* 0x1E */ 1567 uint32_t SenseBufferAddressHigh; /* 0x20 */ 1568 uint32_t SystemReplyAddressHigh; /* 0x24 */ 1569 uint64_t SystemRequestFrameBaseAddress; /* 0x28 */ 1570 uint64_t ReplyDescriptorPostQueueAddress;/* 0x30 */ 1571 uint64_t ReplyFreeQueueAddress; /* 0x38 */ 1572 uint64_t TimeStamp; /* 0x40 */ 1573 }; 1574 1575 /* WhoInit values */ 1576 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 1577 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 1578 #define MPI2_WHOINIT_ROM_BIOS (0x02) 1579 #define MPI2_WHOINIT_PCI_PEER (0x03) 1580 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 1581 #define MPI2_WHOINIT_MANUFACTURER (0x05) 1582 1583 struct MPI2_SGE_CHAIN_UNION { 1584 uint16_t Length; 1585 uint8_t NextChainOffset; 1586 uint8_t Flags; 1587 union { 1588 uint32_t Address32; 1589 uint64_t Address64; 1590 } u; 1591 }; 1592 1593 struct MPI2_IEEE_SGE_SIMPLE32 { 1594 uint32_t Address; 1595 uint32_t FlagsLength; 1596 }; 1597 1598 struct MPI2_IEEE_SGE_SIMPLE64 { 1599 uint64_t Address; 1600 uint32_t Length; 1601 uint16_t Reserved1; 1602 uint8_t Reserved2; 1603 uint8_t Flags; 1604 }; 1605 1606 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION { 1607 struct MPI2_IEEE_SGE_SIMPLE32 Simple32; 1608 struct MPI2_IEEE_SGE_SIMPLE64 Simple64; 1609 } MPI2_IEEE_SGE_SIMPLE_UNION; 1610 1611 typedef struct _MPI2_SGE_SIMPLE_UNION { 1612 uint32_t FlagsLength; 1613 union { 1614 uint32_t Address32; 1615 uint64_t Address64; 1616 } u; 1617 } MPI2_SGE_SIMPLE_UNION; 1618 1619 /**************************************************************************** 1620 * IEEE SGE field definitions and masks 1621 ****************************************************************************/ 1622 1623 /* Flags field bit definitions */ 1624 1625 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1626 1627 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1628 1629 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1630 1631 /* Element Type */ 1632 1633 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1634 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1635 1636 /* Data Location Address Space */ 1637 1638 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1639 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1640 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1641 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1642 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1643 1644 /* Address Size */ 1645 1646 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 1647 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 1648 1649 /*******************/ 1650 /* SCSI IO Control bits */ 1651 #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_MASK (0xFC000000) 1652 #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26) 1653 1654 #define MPI2_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000) 1655 #define MPI2_SCSIIO_CONTROL_NODATATRANSFER (0x00000000) 1656 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 1657 #define MPI2_SCSIIO_CONTROL_READ (0x02000000) 1658 #define MPI2_SCSIIO_CONTROL_BIDIRECTIONAL (0x03000000) 1659 1660 #define MPI2_SCSIIO_CONTROL_TASKPRI_MASK (0x00007800) 1661 #define MPI2_SCSIIO_CONTROL_TASKPRI_SHIFT (11) 1662 1663 #define MPI2_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700) 1664 #define MPI2_SCSIIO_CONTROL_SIMPLEQ (0x00000000) 1665 #define MPI2_SCSIIO_CONTROL_HEADOFQ (0x00000100) 1666 #define MPI2_SCSIIO_CONTROL_ORDEREDQ (0x00000200) 1667 #define MPI2_SCSIIO_CONTROL_ACAQ (0x00000400) 1668 1669 #define MPI2_SCSIIO_CONTROL_TLR_MASK (0x000000C0) 1670 #define MPI2_SCSIIO_CONTROL_NO_TLR (0x00000000) 1671 #define MPI2_SCSIIO_CONTROL_TLR_ON (0x00000040) 1672 #define MPI2_SCSIIO_CONTROL_TLR_OFF (0x00000080) 1673 1674 /*******************/ 1675 1676 typedef struct { 1677 uint8_t CDB[20]; /* 0x00 */ 1678 uint32_t PrimaryReferenceTag; /* 0x14 */ 1679 uint16_t PrimaryApplicationTag; /* 0x18 */ 1680 uint16_t PrimaryApplicationTagMask; /* 0x1A */ 1681 uint32_t TransferLength; /* 0x1C */ 1682 } MPI2_SCSI_IO_CDB_EEDP32; 1683 1684 typedef union _MPI2_IEEE_SGE_CHAIN_UNION { 1685 struct MPI2_IEEE_SGE_SIMPLE32 Chain32; 1686 struct MPI2_IEEE_SGE_SIMPLE64 Chain64; 1687 } MPI2_IEEE_SGE_CHAIN_UNION; 1688 1689 typedef union _MPI2_SIMPLE_SGE_UNION { 1690 MPI2_SGE_SIMPLE_UNION MpiSimple; 1691 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1692 } MPI2_SIMPLE_SGE_UNION; 1693 1694 typedef union _MPI2_SGE_IO_UNION { 1695 MPI2_SGE_SIMPLE_UNION MpiSimple; 1696 struct MPI2_SGE_CHAIN_UNION MpiChain; 1697 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1698 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1699 } MPI2_SGE_IO_UNION; 1700 1701 typedef union { 1702 uint8_t CDB32[32]; 1703 MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 1704 MPI2_SGE_SIMPLE_UNION SGE; 1705 } MPI2_SCSI_IO_CDB_UNION; 1706 1707 /* MPI 2.5 SGLs */ 1708 1709 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1710 1711 typedef struct _MPI25_IEEE_SGE_CHAIN64 { 1712 uint64_t Address; 1713 uint32_t Length; 1714 uint16_t Reserved1; 1715 uint8_t NextChainOffset; 1716 uint8_t Flags; 1717 } MPI25_IEEE_SGE_CHAIN64, *pMpi25IeeeSgeChain64_t; 1718 1719 /* use MPI2_IEEE_SGE_FLAGS_ defines for the Flags field */ 1720 1721 /********/ 1722 1723 /* 1724 * RAID SCSI IO Request Message 1725 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST 1726 */ 1727 struct mfi_mpi2_request_raid_scsi_io { 1728 uint16_t DevHandle; /* 0x00 */ 1729 uint8_t ChainOffset; /* 0x02 */ 1730 uint8_t Function; /* 0x03 */ 1731 uint16_t Reserved1; /* 0x04 */ 1732 uint8_t Reserved2; /* 0x06 */ 1733 uint8_t MsgFlags; /* 0x07 */ 1734 uint8_t VP_ID; /* 0x08 */ 1735 uint8_t VF_ID; /* 0x09 */ 1736 uint16_t Reserved3; /* 0x0A */ 1737 uint32_t SenseBufferLowAddress; /* 0x0C */ 1738 uint16_t SGLFlags; /* 0x10 */ 1739 uint8_t SenseBufferLength; /* 0x12 */ 1740 uint8_t Reserved4; /* 0x13 */ 1741 uint8_t SGLOffset0; /* 0x14 */ 1742 uint8_t SGLOffset1; /* 0x15 */ 1743 uint8_t SGLOffset2; /* 0x16 */ 1744 uint8_t SGLOffset3; /* 0x17 */ 1745 uint32_t SkipCount; /* 0x18 */ 1746 uint32_t DataLength; /* 0x1C */ 1747 uint32_t BidirectionalDataLength; /* 0x20 */ 1748 uint16_t IoFlags; /* 0x24 */ 1749 uint16_t EEDPFlags; /* 0x26 */ 1750 uint32_t EEDPBlockSize; /* 0x28 */ 1751 uint32_t SecondaryReferenceTag; /* 0x2C */ 1752 uint16_t SecondaryApplicationTag; /* 0x30 */ 1753 uint16_t ApplicationTagTranslationMask; /* 0x32 */ 1754 uint8_t LUN[8]; /* 0x34 */ 1755 uint32_t Control; /* 0x3C */ 1756 MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 1757 MPI2_SCSI_IO_VENDOR_UNIQUE RaidContext; /* 0x60 */ 1758 MPI2_SGE_IO_UNION SGL; /* 0x80 */ 1759 } __packed; 1760 1761 /* 1762 * MPT RAID MFA IO Descriptor. 1763 */ 1764 typedef struct _MFI_RAID_MFA_IO_DESCRIPTOR { 1765 uint32_t RequestFlags : 8; 1766 uint32_t MessageAddress1 : 24; /* bits 31:8*/ 1767 uint32_t MessageAddress2; /* bits 61:32 */ 1768 } MFI_RAID_MFA_IO_REQUEST_DESCRIPTOR,*PMFI_RAID_MFA_IO_REQUEST_DESCRIPTOR; 1769 1770 struct mfi_mpi2_request_header { 1771 uint8_t RequestFlags; /* 0x00 */ 1772 uint8_t MSIxIndex; /* 0x01 */ 1773 uint16_t SMID; /* 0x02 */ 1774 uint16_t LMID; /* 0x04 */ 1775 }; 1776 1777 /* defines for the RequestFlags field */ 1778 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 1779 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 1780 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 1781 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 1782 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 1783 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 1784 1785 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 1786 1787 struct mfi_mpi2_request_high_priority { 1788 struct mfi_mpi2_request_header header; 1789 uint16_t reserved; 1790 }; 1791 1792 struct mfi_mpi2_request_scsi_io { 1793 struct mfi_mpi2_request_header header; 1794 uint16_t scsi_io_dev_handle; 1795 }; 1796 1797 struct mfi_mpi2_request_scsi_target { 1798 struct mfi_mpi2_request_header header; 1799 uint16_t scsi_target_io_index; 1800 }; 1801 1802 /* Request Descriptors */ 1803 union mfi_mpi2_request_descriptor { 1804 struct mfi_mpi2_request_header header; 1805 struct mfi_mpi2_request_high_priority high_priority; 1806 struct mfi_mpi2_request_scsi_io scsi_io; 1807 struct mfi_mpi2_request_scsi_target scsi_target; 1808 uint64_t words; 1809 }; 1810 1811 struct mfi_mpi2_reply_header { 1812 uint8_t ReplyFlags; /* 0x00 */ 1813 uint8_t MSIxIndex; /* 0x01 */ 1814 uint16_t SMID; /* 0x02 */ 1815 }; 1816 1817 /* defines for the ReplyFlags field */ 1818 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 1819 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 1820 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 1821 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 1822 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 1823 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 1824 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 1825 1826 /* values for marking a reply descriptor as unused */ 1827 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 1828 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 1829 1830 struct mfi_mpi2_reply_default { 1831 struct mfi_mpi2_reply_header header; 1832 uint32_t DescriptorTypeDependent2; 1833 }; 1834 1835 struct mfi_mpi2_reply_address { 1836 struct mfi_mpi2_reply_header header; 1837 uint32_t ReplyFrameAddress; 1838 }; 1839 1840 struct mfi_mpi2_reply_scsi_io { 1841 struct mfi_mpi2_reply_header header; 1842 uint16_t TaskTag; /* 0x04 */ 1843 uint16_t Reserved1; /* 0x06 */ 1844 }; 1845 1846 struct mfi_mpi2_reply_target_assist { 1847 struct mfi_mpi2_reply_header header; 1848 uint8_t SequenceNumber; /* 0x04 */ 1849 uint8_t Reserved1; /* 0x04 */ 1850 uint16_t IoIndex; /* 0x06 */ 1851 }; 1852 1853 struct mfi_mpi2_reply_target_cmd_buffer { 1854 struct mfi_mpi2_reply_header header; 1855 uint8_t SequenceNumber; /* 0x04 */ 1856 uint8_t Flags; /* 0x04 */ 1857 uint16_t InitiatorDevHandle; /* 0x06 */ 1858 uint16_t IoIndex; /* 0x06 */ 1859 }; 1860 1861 struct mfi_mpi2_reply_raid_accel { 1862 struct mfi_mpi2_reply_header header; 1863 uint8_t SequenceNumber; /* 0x04 */ 1864 uint32_t Reserved; /* 0x04 */ 1865 }; 1866 1867 /* union of Reply Descriptors */ 1868 union mfi_mpi2_reply_descriptor { 1869 struct mfi_mpi2_reply_header header; 1870 struct mfi_mpi2_reply_scsi_io scsi_io; 1871 struct mfi_mpi2_reply_target_assist target_assist; 1872 struct mfi_mpi2_reply_target_cmd_buffer target_cmd; 1873 struct mfi_mpi2_reply_raid_accel raid_accel; 1874 struct mfi_mpi2_reply_default reply_default; 1875 uint64_t words; 1876 }; 1877 1878 struct IO_REQUEST_INFO { 1879 uint64_t ldStartBlock; 1880 uint32_t numBlocks; 1881 uint16_t ldTgtId; 1882 uint8_t isRead; 1883 uint16_t devHandle; 1884 uint64_t pdBlock; 1885 uint8_t fpOkForIo; 1886 }; 1887 1888 #define MFI_SCSI_MAX_TARGETS 128 1889 #define MFI_SCSI_MAX_LUNS 8 1890 #define MFI_SCSI_INITIATOR_ID 255 1891 #define MFI_SCSI_MAX_CMDS 8 1892 #define MFI_SCSI_MAX_CDB_LEN 16 1893 1894 #endif /* _MFIREG_H */