mpi_ioc.h (62526B) - Raw
1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2000-2010, LSI Logic Corporation and its contributors. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are 9 * met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 13 * substantially similar to the "NO WARRANTY" disclaimer below 14 * ("Disclaimer") and any redistribution must be conditioned upon including 15 * a substantially similar Disclaimer requirement for further binary 16 * redistribution. 17 * 3. Neither the name of the LSI Logic Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF THE COPYRIGHT 31 * OWNER OR CONTRIBUTOR IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * Name: mpi_ioc.h 34 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages 35 * Creation Date: August 11, 2000 36 * 37 * mpi_ioc.h Version: 01.05.16 38 * 39 * Version History 40 * --------------- 41 * 42 * Date Version Description 43 * -------- -------- ------------------------------------------------------ 44 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 45 * 05-24-00 00.10.02 Added _MSG_IOC_INIT_REPLY structure. 46 * 06-06-00 01.00.01 Added CurReplyFrameSize field to _MSG_IOC_FACTS_REPLY. 47 * 06-12-00 01.00.02 Added _MSG_PORT_ENABLE_REPLY structure. 48 * Added _MSG_EVENT_ACK_REPLY structure. 49 * Added _MSG_FW_DOWNLOAD_REPLY structure. 50 * Added _MSG_TOOLBOX_REPLY structure. 51 * 06-30-00 01.00.03 Added MaxLanBuckets to _PORT_FACT_REPLY structure. 52 * 07-27-00 01.00.04 Added _EVENT_DATA structure definitions for _SCSI, 53 * _LINK_STATUS, _LOOP_STATE and _LOGOUT. 54 * 08-11-00 01.00.05 Switched positions of MsgLength and Function fields in 55 * _MSG_EVENT_ACK_REPLY structure to match specification. 56 * 11-02-00 01.01.01 Original release for post 1.0 work. 57 * Added a value for Manufacturer to WhoInit. 58 * 12-04-00 01.01.02 Modified IOCFacts reply, added FWUpload messages, and 59 * removed toolbox message. 60 * 01-09-01 01.01.03 Added event enabled and disabled defines. 61 * Added structures for FwHeader and DataHeader. 62 * Added ImageType to FwUpload reply. 63 * 02-20-01 01.01.04 Started using MPI_POINTER. 64 * 02-27-01 01.01.05 Added event for RAID status change and its event data. 65 * Added IocNumber field to MSG_IOC_FACTS_REPLY. 66 * 03-27-01 01.01.06 Added defines for ProductId field of MPI_FW_HEADER. 67 * Added structure offset comments. 68 * 04-09-01 01.01.07 Added structure EVENT_DATA_EVENT_CHANGE. 69 * 08-08-01 01.02.01 Original release for v1.2 work. 70 * New format for FWVersion and ProductId in 71 * MSG_IOC_FACTS_REPLY and MPI_FW_HEADER. 72 * 08-31-01 01.02.02 Addded event MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE and 73 * related structure and defines. 74 * Added event MPI_EVENT_ON_BUS_TIMER_EXPIRED. 75 * Added MPI_IOCINIT_FLAGS_DISCARD_FW_IMAGE. 76 * Replaced a reserved field in MSG_IOC_FACTS_REPLY with 77 * IOCExceptions and changed DataImageSize to reserved. 78 * Added MPI_FW_DOWNLOAD_ITYPE_NVSTORE_DATA and 79 * MPI_FW_UPLOAD_ITYPE_NVDATA. 80 * 09-28-01 01.02.03 Modified Event Data for Integrated RAID. 81 * 11-01-01 01.02.04 Added defines for MPI_EXT_IMAGE_HEADER ImageType field. 82 * 03-14-02 01.02.05 Added HeaderVersion field to MSG_IOC_FACTS_REPLY. 83 * 05-31-02 01.02.06 Added define for 84 * MPI_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID. 85 * Added AliasIndex to EVENT_DATA_LOGOUT structure. 86 * 04-01-03 01.02.07 Added defines for MPI_FW_HEADER_SIGNATURE_. 87 * 06-26-03 01.02.08 Added new values to the product family defines. 88 * 04-29-04 01.02.09 Added IOCCapabilities field to MSG_IOC_FACTS_REPLY and 89 * added related defines. 90 * 05-11-04 01.03.01 Original release for MPI v1.3. 91 * 08-19-04 01.05.01 Added four new fields to MSG_IOC_INIT. 92 * Added three new fields to MSG_IOC_FACTS_REPLY. 93 * Defined four new bits for the IOCCapabilities field of 94 * the IOCFacts reply. 95 * Added two new PortTypes for the PortFacts reply. 96 * Added six new events along with their EventData 97 * structures. 98 * Added a new MsgFlag to the FwDownload request to 99 * indicate last segment. 100 * Defined a new image type of boot loader. 101 * Added FW family codes for SAS product families. 102 * 10-05-04 01.05.02 Added ReplyFifoHostSignalingAddr field to 103 * MSG_IOC_FACTS_REPLY. 104 * 12-07-04 01.05.03 Added more defines for SAS Discovery Error event. 105 * 12-09-04 01.05.04 Added Unsupported device to SAS Device event. 106 * 01-15-05 01.05.05 Added event data for SAS SES Event. 107 * 02-09-05 01.05.06 Added MPI_FW_UPLOAD_ITYPE_FW_BACKUP define. 108 * 02-22-05 01.05.07 Added Host Page Buffer Persistent flag to IOC Facts 109 * Reply and IOC Init Request. 110 * 03-11-05 01.05.08 Added family code for 1068E family. 111 * Removed IOCFacts Reply EEDP Capability bit. 112 * 06-24-05 01.05.09 Added 5 new IOCFacts Reply IOCCapabilities bits. 113 * Added Max SATA Targets to SAS Discovery Error event. 114 * 08-30-05 01.05.10 Added 4 new events and their event data structures. 115 * Added new ReasonCode value for SAS Device Status Change 116 * event. 117 * Added new family code for FC949E. 118 * 03-27-06 01.05.11 Added MPI_IOCFACTS_CAPABILITY_TLR. 119 * Added additional Reason Codes and more event data fields 120 * to EVENT_DATA_SAS_DEVICE_STATUS_CHANGE. 121 * Added EVENT_DATA_SAS_BROADCAST_PRIMITIVE structure and 122 * new event. 123 * Added MPI_EVENT_SAS_SMP_ERROR and event data structure. 124 * Added MPI_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE and event 125 * data structure. 126 * Added MPI_EVENT_SAS_INIT_TABLE_OVERFLOW and event 127 * data structure. 128 * Added MPI_EXT_IMAGE_TYPE_INITIALIZATION. 129 * 10-11-06 01.05.12 Added MPI_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED. 130 * Added MaxInitiators field to PortFacts reply. 131 * Added SAS Device Status Change ReasonCode for 132 * asynchronous notificaiton. 133 * Added MPI_EVENT_SAS_EXPANDER_STATUS_CHANGE and event 134 * data structure. 135 * Added new ImageType values for FWDownload and FWUpload 136 * requests. 137 * 02-28-07 01.05.13 Added MPI_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT for SAS 138 * Broadcast Event Data (replacing _RESERVED2). 139 * For Discovery Error Event Data DiscoveryStatus field, 140 * replaced _MULTPL_PATHS with _UNSUPPORTED_DEVICE and 141 * added _MULTI_PORT_DOMAIN. 142 * 05-24-07 01.05.14 Added Common Boot Block type to FWDownload Request. 143 * Added Common Boot Block type to FWUpload Request. 144 * 08-07-07 01.05.15 Added MPI_EVENT_SAS_INIT_RC_REMOVED define. 145 * Added MPI_EVENT_IR2_RC_DUAL_PORT_ADDED and 146 * MPI_EVENT_IR2_RC_DUAL_PORT_REMOVED for IR2 event data. 147 * Added SASAddress field to SAS Initiator Device Table 148 * Overflow event data structure. 149 * 03-28-08 01.05.16 Added two new ReasonCode values to SAS Device Status 150 * Change Event data to indicate completion of internally 151 * generated task management. 152 * Added MPI_EVENT_DSCVRY_ERR_DS_SATA_INIT_FAILURE define. 153 * Added MPI_EVENT_SAS_INIT_RC_INACCESSIBLE define. 154 * -------------------------------------------------------------------------- 155 */ 156 157 #ifndef MPI_IOC_H 158 #define MPI_IOC_H 159 160 /***************************************************************************** 161 * 162 * I O C M e s s a g e s 163 * 164 *****************************************************************************/ 165 166 /****************************************************************************/ 167 /* IOCInit message */ 168 /****************************************************************************/ 169 170 typedef struct _MSG_IOC_INIT 171 { 172 U8 WhoInit; /* 00h */ 173 U8 Reserved; /* 01h */ 174 U8 ChainOffset; /* 02h */ 175 U8 Function; /* 03h */ 176 U8 Flags; /* 04h */ 177 U8 MaxDevices; /* 05h */ 178 U8 MaxBuses; /* 06h */ 179 U8 MsgFlags; /* 07h */ 180 U32 MsgContext; /* 08h */ 181 U16 ReplyFrameSize; /* 0Ch */ 182 U8 Reserved1[2]; /* 0Eh */ 183 U32 HostMfaHighAddr; /* 10h */ 184 U32 SenseBufferHighAddr; /* 14h */ 185 U32 ReplyFifoHostSignalingAddr; /* 18h */ 186 SGE_SIMPLE_UNION HostPageBufferSGE; /* 1Ch */ 187 U16 MsgVersion; /* 28h */ 188 U16 HeaderVersion; /* 2Ah */ 189 } MSG_IOC_INIT, MPI_POINTER PTR_MSG_IOC_INIT, 190 IOCInit_t, MPI_POINTER pIOCInit_t; 191 192 /* WhoInit values */ 193 #define MPI_WHOINIT_NO_ONE (0x00) 194 #define MPI_WHOINIT_SYSTEM_BIOS (0x01) 195 #define MPI_WHOINIT_ROM_BIOS (0x02) 196 #define MPI_WHOINIT_PCI_PEER (0x03) 197 #define MPI_WHOINIT_HOST_DRIVER (0x04) 198 #define MPI_WHOINIT_MANUFACTURER (0x05) 199 200 /* Flags values */ 201 #define MPI_IOCINIT_FLAGS_HOST_PAGE_BUFFER_PERSISTENT (0x04) 202 #define MPI_IOCINIT_FLAGS_REPLY_FIFO_HOST_SIGNAL (0x02) 203 #define MPI_IOCINIT_FLAGS_DISCARD_FW_IMAGE (0x01) 204 205 /* MsgVersion */ 206 #define MPI_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00) 207 #define MPI_IOCINIT_MSGVERSION_MAJOR_SHIFT (8) 208 #define MPI_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF) 209 #define MPI_IOCINIT_MSGVERSION_MINOR_SHIFT (0) 210 211 /* HeaderVersion */ 212 #define MPI_IOCINIT_HEADERVERSION_UNIT_MASK (0xFF00) 213 #define MPI_IOCINIT_HEADERVERSION_UNIT_SHIFT (8) 214 #define MPI_IOCINIT_HEADERVERSION_DEV_MASK (0x00FF) 215 #define MPI_IOCINIT_HEADERVERSION_DEV_SHIFT (0) 216 217 typedef struct _MSG_IOC_INIT_REPLY 218 { 219 U8 WhoInit; /* 00h */ 220 U8 Reserved; /* 01h */ 221 U8 MsgLength; /* 02h */ 222 U8 Function; /* 03h */ 223 U8 Flags; /* 04h */ 224 U8 MaxDevices; /* 05h */ 225 U8 MaxBuses; /* 06h */ 226 U8 MsgFlags; /* 07h */ 227 U32 MsgContext; /* 08h */ 228 U16 Reserved2; /* 0Ch */ 229 U16 IOCStatus; /* 0Eh */ 230 U32 IOCLogInfo; /* 10h */ 231 } MSG_IOC_INIT_REPLY, MPI_POINTER PTR_MSG_IOC_INIT_REPLY, 232 IOCInitReply_t, MPI_POINTER pIOCInitReply_t; 233 234 /****************************************************************************/ 235 /* IOC Facts message */ 236 /****************************************************************************/ 237 238 typedef struct _MSG_IOC_FACTS 239 { 240 U8 Reserved[2]; /* 00h */ 241 U8 ChainOffset; /* 01h */ 242 U8 Function; /* 02h */ 243 U8 Reserved1[3]; /* 03h */ 244 U8 MsgFlags; /* 04h */ 245 U32 MsgContext; /* 08h */ 246 } MSG_IOC_FACTS, MPI_POINTER PTR_IOC_FACTS, 247 IOCFacts_t, MPI_POINTER pIOCFacts_t; 248 249 typedef struct _MPI_FW_VERSION_STRUCT 250 { 251 U8 Dev; /* 00h */ 252 U8 Unit; /* 01h */ 253 U8 Minor; /* 02h */ 254 U8 Major; /* 03h */ 255 } MPI_FW_VERSION_STRUCT; 256 257 typedef union _MPI_FW_VERSION 258 { 259 MPI_FW_VERSION_STRUCT Struct; 260 U32 Word; 261 } MPI_FW_VERSION; 262 263 /* IOC Facts Reply */ 264 typedef struct _MSG_IOC_FACTS_REPLY 265 { 266 U16 MsgVersion; /* 00h */ 267 U8 MsgLength; /* 02h */ 268 U8 Function; /* 03h */ 269 U16 HeaderVersion; /* 04h */ 270 U8 IOCNumber; /* 06h */ 271 U8 MsgFlags; /* 07h */ 272 U32 MsgContext; /* 08h */ 273 U16 IOCExceptions; /* 0Ch */ 274 U16 IOCStatus; /* 0Eh */ 275 U32 IOCLogInfo; /* 10h */ 276 U8 MaxChainDepth; /* 14h */ 277 U8 WhoInit; /* 15h */ 278 U8 BlockSize; /* 16h */ 279 U8 Flags; /* 17h */ 280 U16 ReplyQueueDepth; /* 18h */ 281 U16 RequestFrameSize; /* 1Ah */ 282 U16 Reserved_0101_FWVersion; /* 1Ch */ /* obsolete 16-bit FWVersion */ 283 U16 ProductID; /* 1Eh */ 284 U32 CurrentHostMfaHighAddr; /* 20h */ 285 U16 GlobalCredits; /* 24h */ 286 U8 NumberOfPorts; /* 26h */ 287 U8 EventState; /* 27h */ 288 U32 CurrentSenseBufferHighAddr; /* 28h */ 289 U16 CurReplyFrameSize; /* 2Ch */ 290 U8 MaxDevices; /* 2Eh */ 291 U8 MaxBuses; /* 2Fh */ 292 U32 FWImageSize; /* 30h */ 293 U32 IOCCapabilities; /* 34h */ 294 MPI_FW_VERSION FWVersion; /* 38h */ 295 U16 HighPriorityQueueDepth; /* 3Ch */ 296 U16 Reserved2; /* 3Eh */ 297 SGE_SIMPLE_UNION HostPageBufferSGE; /* 40h */ 298 U32 ReplyFifoHostSignalingAddr; /* 4Ch */ 299 } MSG_IOC_FACTS_REPLY, MPI_POINTER PTR_MSG_IOC_FACTS_REPLY, 300 IOCFactsReply_t, MPI_POINTER pIOCFactsReply_t; 301 302 #define MPI_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00) 303 #define MPI_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8) 304 #define MPI_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF) 305 #define MPI_IOCFACTS_MSGVERSION_MINOR_SHIFT (0) 306 307 #define MPI_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00) 308 #define MPI_IOCFACTS_HDRVERSION_UNIT_SHIFT (8) 309 #define MPI_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF) 310 #define MPI_IOCFACTS_HDRVERSION_DEV_SHIFT (0) 311 312 #define MPI_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001) 313 #define MPI_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002) 314 #define MPI_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004) 315 #define MPI_IOCFACTS_EXCEPT_PERSISTENT_TABLE_FULL (0x0008) 316 #define MPI_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010) 317 318 #define MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT (0x01) 319 #define MPI_IOCFACTS_FLAGS_REPLY_FIFO_HOST_SIGNAL (0x02) 320 #define MPI_IOCFACTS_FLAGS_HOST_PAGE_BUFFER_PERSISTENT (0x04) 321 322 #define MPI_IOCFACTS_EVENTSTATE_DISABLED (0x00) 323 #define MPI_IOCFACTS_EVENTSTATE_ENABLED (0x01) 324 325 #define MPI_IOCFACTS_CAPABILITY_HIGH_PRI_Q (0x00000001) 326 #define MPI_IOCFACTS_CAPABILITY_REPLY_HOST_SIGNAL (0x00000002) 327 #define MPI_IOCFACTS_CAPABILITY_QUEUE_FULL_HANDLING (0x00000004) 328 #define MPI_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008) 329 #define MPI_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010) 330 #define MPI_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020) 331 #define MPI_IOCFACTS_CAPABILITY_EEDP (0x00000040) 332 #define MPI_IOCFACTS_CAPABILITY_BIDIRECTIONAL (0x00000080) 333 #define MPI_IOCFACTS_CAPABILITY_MULTICAST (0x00000100) 334 #define MPI_IOCFACTS_CAPABILITY_SCSIIO32 (0x00000200) 335 #define MPI_IOCFACTS_CAPABILITY_NO_SCSIIO16 (0x00000400) 336 #define MPI_IOCFACTS_CAPABILITY_TLR (0x00000800) 337 338 /***************************************************************************** 339 * 340 * P o r t M e s s a g e s 341 * 342 *****************************************************************************/ 343 344 /****************************************************************************/ 345 /* Port Facts message and Reply */ 346 /****************************************************************************/ 347 348 typedef struct _MSG_PORT_FACTS 349 { 350 U8 Reserved[2]; /* 00h */ 351 U8 ChainOffset; /* 02h */ 352 U8 Function; /* 03h */ 353 U8 Reserved1[2]; /* 04h */ 354 U8 PortNumber; /* 06h */ 355 U8 MsgFlags; /* 07h */ 356 U32 MsgContext; /* 08h */ 357 } MSG_PORT_FACTS, MPI_POINTER PTR_MSG_PORT_FACTS, 358 PortFacts_t, MPI_POINTER pPortFacts_t; 359 360 typedef struct _MSG_PORT_FACTS_REPLY 361 { 362 U16 Reserved; /* 00h */ 363 U8 MsgLength; /* 02h */ 364 U8 Function; /* 03h */ 365 U16 Reserved1; /* 04h */ 366 U8 PortNumber; /* 06h */ 367 U8 MsgFlags; /* 07h */ 368 U32 MsgContext; /* 08h */ 369 U16 Reserved2; /* 0Ch */ 370 U16 IOCStatus; /* 0Eh */ 371 U32 IOCLogInfo; /* 10h */ 372 U8 Reserved3; /* 14h */ 373 U8 PortType; /* 15h */ 374 U16 MaxDevices; /* 16h */ 375 U16 PortSCSIID; /* 18h */ 376 U16 ProtocolFlags; /* 1Ah */ 377 U16 MaxPostedCmdBuffers; /* 1Ch */ 378 U16 MaxPersistentIDs; /* 1Eh */ 379 U16 MaxLanBuckets; /* 20h */ 380 U8 MaxInitiators; /* 22h */ 381 U8 Reserved4; /* 23h */ 382 U32 Reserved5; /* 24h */ 383 } MSG_PORT_FACTS_REPLY, MPI_POINTER PTR_MSG_PORT_FACTS_REPLY, 384 PortFactsReply_t, MPI_POINTER pPortFactsReply_t; 385 386 /* PortTypes values */ 387 388 #define MPI_PORTFACTS_PORTTYPE_INACTIVE (0x00) 389 #define MPI_PORTFACTS_PORTTYPE_SCSI (0x01) 390 #define MPI_PORTFACTS_PORTTYPE_FC (0x10) 391 #define MPI_PORTFACTS_PORTTYPE_ISCSI (0x20) 392 #define MPI_PORTFACTS_PORTTYPE_SAS (0x30) 393 394 /* ProtocolFlags values */ 395 396 #define MPI_PORTFACTS_PROTOCOL_LOGBUSADDR (0x01) 397 #define MPI_PORTFACTS_PROTOCOL_LAN (0x02) 398 #define MPI_PORTFACTS_PROTOCOL_TARGET (0x04) 399 #define MPI_PORTFACTS_PROTOCOL_INITIATOR (0x08) 400 401 /****************************************************************************/ 402 /* Port Enable Message */ 403 /****************************************************************************/ 404 405 typedef struct _MSG_PORT_ENABLE 406 { 407 U8 Reserved[2]; /* 00h */ 408 U8 ChainOffset; /* 02h */ 409 U8 Function; /* 03h */ 410 U8 Reserved1[2]; /* 04h */ 411 U8 PortNumber; /* 06h */ 412 U8 MsgFlags; /* 07h */ 413 U32 MsgContext; /* 08h */ 414 } MSG_PORT_ENABLE, MPI_POINTER PTR_MSG_PORT_ENABLE, 415 PortEnable_t, MPI_POINTER pPortEnable_t; 416 417 typedef struct _MSG_PORT_ENABLE_REPLY 418 { 419 U8 Reserved[2]; /* 00h */ 420 U8 MsgLength; /* 02h */ 421 U8 Function; /* 03h */ 422 U8 Reserved1[2]; /* 04h */ 423 U8 PortNumber; /* 05h */ 424 U8 MsgFlags; /* 07h */ 425 U32 MsgContext; /* 08h */ 426 U16 Reserved2; /* 0Ch */ 427 U16 IOCStatus; /* 0Eh */ 428 U32 IOCLogInfo; /* 10h */ 429 } MSG_PORT_ENABLE_REPLY, MPI_POINTER PTR_MSG_PORT_ENABLE_REPLY, 430 PortEnableReply_t, MPI_POINTER pPortEnableReply_t; 431 432 /***************************************************************************** 433 * 434 * E v e n t M e s s a g e s 435 * 436 *****************************************************************************/ 437 438 /****************************************************************************/ 439 /* Event Notification messages */ 440 /****************************************************************************/ 441 442 typedef struct _MSG_EVENT_NOTIFY 443 { 444 U8 Switch; /* 00h */ 445 U8 Reserved; /* 01h */ 446 U8 ChainOffset; /* 02h */ 447 U8 Function; /* 03h */ 448 U8 Reserved1[3]; /* 04h */ 449 U8 MsgFlags; /* 07h */ 450 U32 MsgContext; /* 08h */ 451 } MSG_EVENT_NOTIFY, MPI_POINTER PTR_MSG_EVENT_NOTIFY, 452 EventNotification_t, MPI_POINTER pEventNotification_t; 453 454 /* Event Notification Reply */ 455 456 typedef struct _MSG_EVENT_NOTIFY_REPLY 457 { 458 U16 EventDataLength; /* 00h */ 459 U8 MsgLength; /* 02h */ 460 U8 Function; /* 03h */ 461 U8 Reserved1[2]; /* 04h */ 462 U8 AckRequired; /* 06h */ 463 U8 MsgFlags; /* 07h */ 464 U32 MsgContext; /* 08h */ 465 U8 Reserved2[2]; /* 0Ch */ 466 U16 IOCStatus; /* 0Eh */ 467 U32 IOCLogInfo; /* 10h */ 468 U32 Event; /* 14h */ 469 U32 EventContext; /* 18h */ 470 U32 Data[1]; /* 1Ch */ 471 } MSG_EVENT_NOTIFY_REPLY, MPI_POINTER PTR_MSG_EVENT_NOTIFY_REPLY, 472 EventNotificationReply_t, MPI_POINTER pEventNotificationReply_t; 473 474 /* Event Acknowledge */ 475 476 typedef struct _MSG_EVENT_ACK 477 { 478 U8 Reserved[2]; /* 00h */ 479 U8 ChainOffset; /* 02h */ 480 U8 Function; /* 03h */ 481 U8 Reserved1[3]; /* 04h */ 482 U8 MsgFlags; /* 07h */ 483 U32 MsgContext; /* 08h */ 484 U32 Event; /* 0Ch */ 485 U32 EventContext; /* 10h */ 486 } MSG_EVENT_ACK, MPI_POINTER PTR_MSG_EVENT_ACK, 487 EventAck_t, MPI_POINTER pEventAck_t; 488 489 typedef struct _MSG_EVENT_ACK_REPLY 490 { 491 U8 Reserved[2]; /* 00h */ 492 U8 MsgLength; /* 02h */ 493 U8 Function; /* 03h */ 494 U8 Reserved1[3]; /* 04h */ 495 U8 MsgFlags; /* 07h */ 496 U32 MsgContext; /* 08h */ 497 U16 Reserved2; /* 0Ch */ 498 U16 IOCStatus; /* 0Eh */ 499 U32 IOCLogInfo; /* 10h */ 500 } MSG_EVENT_ACK_REPLY, MPI_POINTER PTR_MSG_EVENT_ACK_REPLY, 501 EventAckReply_t, MPI_POINTER pEventAckReply_t; 502 503 /* Switch */ 504 505 #define MPI_EVENT_NOTIFICATION_SWITCH_OFF (0x00) 506 #define MPI_EVENT_NOTIFICATION_SWITCH_ON (0x01) 507 508 /* Event */ 509 510 #define MPI_EVENT_NONE (0x00000000) 511 #define MPI_EVENT_LOG_DATA (0x00000001) 512 #define MPI_EVENT_STATE_CHANGE (0x00000002) 513 #define MPI_EVENT_UNIT_ATTENTION (0x00000003) 514 #define MPI_EVENT_IOC_BUS_RESET (0x00000004) 515 #define MPI_EVENT_EXT_BUS_RESET (0x00000005) 516 #define MPI_EVENT_RESCAN (0x00000006) 517 #define MPI_EVENT_LINK_STATUS_CHANGE (0x00000007) 518 #define MPI_EVENT_LOOP_STATE_CHANGE (0x00000008) 519 #define MPI_EVENT_LOGOUT (0x00000009) 520 #define MPI_EVENT_EVENT_CHANGE (0x0000000A) 521 #define MPI_EVENT_INTEGRATED_RAID (0x0000000B) 522 #define MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE (0x0000000C) 523 #define MPI_EVENT_ON_BUS_TIMER_EXPIRED (0x0000000D) 524 #define MPI_EVENT_QUEUE_FULL (0x0000000E) 525 #define MPI_EVENT_SAS_DEVICE_STATUS_CHANGE (0x0000000F) 526 #define MPI_EVENT_SAS_SES (0x00000010) 527 #define MPI_EVENT_PERSISTENT_TABLE_FULL (0x00000011) 528 #define MPI_EVENT_SAS_PHY_LINK_STATUS (0x00000012) 529 #define MPI_EVENT_SAS_DISCOVERY_ERROR (0x00000013) 530 #define MPI_EVENT_IR_RESYNC_UPDATE (0x00000014) 531 #define MPI_EVENT_IR2 (0x00000015) 532 #define MPI_EVENT_SAS_DISCOVERY (0x00000016) 533 #define MPI_EVENT_SAS_BROADCAST_PRIMITIVE (0x00000017) 534 #define MPI_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x00000018) 535 #define MPI_EVENT_SAS_INIT_TABLE_OVERFLOW (0x00000019) 536 #define MPI_EVENT_SAS_SMP_ERROR (0x0000001A) 537 #define MPI_EVENT_SAS_EXPANDER_STATUS_CHANGE (0x0000001B) 538 #define MPI_EVENT_LOG_ENTRY_ADDED (0x00000021) 539 540 /* AckRequired field values */ 541 542 #define MPI_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00) 543 #define MPI_EVENT_NOTIFICATION_ACK_REQUIRED (0x01) 544 545 /* EventChange Event data */ 546 547 typedef struct _EVENT_DATA_EVENT_CHANGE 548 { 549 U8 EventState; /* 00h */ 550 U8 Reserved; /* 01h */ 551 U16 Reserved1; /* 02h */ 552 } EVENT_DATA_EVENT_CHANGE, MPI_POINTER PTR_EVENT_DATA_EVENT_CHANGE, 553 EventDataEventChange_t, MPI_POINTER pEventDataEventChange_t; 554 555 /* LogEntryAdded Event data */ 556 557 /* this structure matches MPI_LOG_0_ENTRY in mpi_cnfg.h */ 558 #define MPI_EVENT_DATA_LOG_ENTRY_DATA_LENGTH (0x1C) 559 typedef struct _EVENT_DATA_LOG_ENTRY 560 { 561 U32 TimeStamp; /* 00h */ 562 U32 Reserved1; /* 04h */ 563 U16 LogSequence; /* 08h */ 564 U16 LogEntryQualifier; /* 0Ah */ 565 U8 LogData[MPI_EVENT_DATA_LOG_ENTRY_DATA_LENGTH]; /* 0Ch */ 566 } EVENT_DATA_LOG_ENTRY, MPI_POINTER PTR_EVENT_DATA_LOG_ENTRY, 567 MpiEventDataLogEntry_t, MPI_POINTER pMpiEventDataLogEntry_t; 568 569 typedef struct _EVENT_DATA_LOG_ENTRY_ADDED 570 { 571 U16 LogSequence; /* 00h */ 572 U16 Reserved1; /* 02h */ 573 U32 Reserved2; /* 04h */ 574 EVENT_DATA_LOG_ENTRY LogEntry; /* 08h */ 575 } EVENT_DATA_LOG_ENTRY_ADDED, MPI_POINTER PTR_EVENT_DATA_LOG_ENTRY_ADDED, 576 MpiEventDataLogEntryAdded_t, MPI_POINTER pMpiEventDataLogEntryAdded_t; 577 578 /* SCSI Event data for Port, Bus and Device forms */ 579 580 typedef struct _EVENT_DATA_SCSI 581 { 582 U8 TargetID; /* 00h */ 583 U8 BusPort; /* 01h */ 584 U16 Reserved; /* 02h */ 585 } EVENT_DATA_SCSI, MPI_POINTER PTR_EVENT_DATA_SCSI, 586 EventDataScsi_t, MPI_POINTER pEventDataScsi_t; 587 588 /* SCSI Device Status Change Event data */ 589 590 typedef struct _EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE 591 { 592 U8 TargetID; /* 00h */ 593 U8 Bus; /* 01h */ 594 U8 ReasonCode; /* 02h */ 595 U8 LUN; /* 03h */ 596 U8 ASC; /* 04h */ 597 U8 ASCQ; /* 05h */ 598 U16 Reserved; /* 06h */ 599 } EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE, 600 MPI_POINTER PTR_EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE, 601 MpiEventDataScsiDeviceStatusChange_t, 602 MPI_POINTER pMpiEventDataScsiDeviceStatusChange_t; 603 604 /* MPI SCSI Device Status Change Event data ReasonCode values */ 605 #define MPI_EVENT_SCSI_DEV_STAT_RC_ADDED (0x03) 606 #define MPI_EVENT_SCSI_DEV_STAT_RC_NOT_RESPONDING (0x04) 607 #define MPI_EVENT_SCSI_DEV_STAT_RC_SMART_DATA (0x05) 608 609 /* SAS Device Status Change Event data */ 610 611 typedef struct _EVENT_DATA_SAS_DEVICE_STATUS_CHANGE 612 { 613 U8 TargetID; /* 00h */ 614 U8 Bus; /* 01h */ 615 U8 ReasonCode; /* 02h */ 616 U8 Reserved; /* 03h */ 617 U8 ASC; /* 04h */ 618 U8 ASCQ; /* 05h */ 619 U16 DevHandle; /* 06h */ 620 U32 DeviceInfo; /* 08h */ 621 U16 ParentDevHandle; /* 0Ch */ 622 U8 PhyNum; /* 0Eh */ 623 U8 Reserved1; /* 0Fh */ 624 U64 SASAddress; /* 10h */ 625 U8 LUN[8]; /* 18h */ 626 U16 TaskTag; /* 20h */ 627 U16 Reserved2; /* 22h */ 628 } EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 629 MPI_POINTER PTR_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 630 MpiEventDataSasDeviceStatusChange_t, 631 MPI_POINTER pMpiEventDataSasDeviceStatusChange_t; 632 633 /* MPI SAS Device Status Change Event data ReasonCode values */ 634 #define MPI_EVENT_SAS_DEV_STAT_RC_ADDED (0x03) 635 #define MPI_EVENT_SAS_DEV_STAT_RC_NOT_RESPONDING (0x04) 636 #define MPI_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05) 637 #define MPI_EVENT_SAS_DEV_STAT_RC_NO_PERSIST_ADDED (0x06) 638 #define MPI_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07) 639 #define MPI_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08) 640 #define MPI_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09) 641 #define MPI_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A) 642 #define MPI_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B) 643 #define MPI_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C) 644 #define MPI_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D) 645 #define MPI_EVENT_SAS_DEV_STAT_RC_CMPL_INTERNAL_DEV_RESET (0x0E) 646 #define MPI_EVENT_SAS_DEV_STAT_RC_CMPL_TASK_ABORT_INTERNAL (0x0F) 647 648 /* SCSI Event data for Queue Full event */ 649 650 typedef struct _EVENT_DATA_QUEUE_FULL 651 { 652 U8 TargetID; /* 00h */ 653 U8 Bus; /* 01h */ 654 U16 CurrentDepth; /* 02h */ 655 } EVENT_DATA_QUEUE_FULL, MPI_POINTER PTR_EVENT_DATA_QUEUE_FULL, 656 EventDataQueueFull_t, MPI_POINTER pEventDataQueueFull_t; 657 658 /* MPI Integrated RAID Event data */ 659 660 typedef struct _EVENT_DATA_RAID 661 { 662 U8 VolumeID; /* 00h */ 663 U8 VolumeBus; /* 01h */ 664 U8 ReasonCode; /* 02h */ 665 U8 PhysDiskNum; /* 03h */ 666 U8 ASC; /* 04h */ 667 U8 ASCQ; /* 05h */ 668 U16 Reserved; /* 06h */ 669 U32 SettingsStatus; /* 08h */ 670 } EVENT_DATA_RAID, MPI_POINTER PTR_EVENT_DATA_RAID, 671 MpiEventDataRaid_t, MPI_POINTER pMpiEventDataRaid_t; 672 673 /* MPI Integrated RAID Event data ReasonCode values */ 674 #define MPI_EVENT_RAID_RC_VOLUME_CREATED (0x00) 675 #define MPI_EVENT_RAID_RC_VOLUME_DELETED (0x01) 676 #define MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED (0x02) 677 #define MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED (0x03) 678 #define MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED (0x04) 679 #define MPI_EVENT_RAID_RC_PHYSDISK_CREATED (0x05) 680 #define MPI_EVENT_RAID_RC_PHYSDISK_DELETED (0x06) 681 #define MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED (0x07) 682 #define MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED (0x08) 683 #define MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED (0x09) 684 #define MPI_EVENT_RAID_RC_SMART_DATA (0x0A) 685 #define MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED (0x0B) 686 687 /* MPI Integrated RAID Resync Update Event data */ 688 689 typedef struct _MPI_EVENT_DATA_IR_RESYNC_UPDATE 690 { 691 U8 VolumeID; /* 00h */ 692 U8 VolumeBus; /* 01h */ 693 U8 ResyncComplete; /* 02h */ 694 U8 Reserved1; /* 03h */ 695 U32 Reserved2; /* 04h */ 696 } MPI_EVENT_DATA_IR_RESYNC_UPDATE, 697 MPI_POINTER PTR_MPI_EVENT_DATA_IR_RESYNC_UPDATE, 698 MpiEventDataIrResyncUpdate_t, MPI_POINTER pMpiEventDataIrResyncUpdate_t; 699 700 /* MPI IR2 Event data */ 701 702 /* MPI_LD_STATE or MPI_PD_STATE */ 703 typedef struct _IR2_STATE_CHANGED 704 { 705 U16 PreviousState; /* 00h */ 706 U16 NewState; /* 02h */ 707 } IR2_STATE_CHANGED, MPI_POINTER PTR_IR2_STATE_CHANGED; 708 709 typedef struct _IR2_PD_INFO 710 { 711 U16 DeviceHandle; /* 00h */ 712 U8 TruncEnclosureHandle; /* 02h */ 713 U8 TruncatedSlot; /* 03h */ 714 } IR2_PD_INFO, MPI_POINTER PTR_IR2_PD_INFO; 715 716 typedef union _MPI_IR2_RC_EVENT_DATA 717 { 718 IR2_STATE_CHANGED StateChanged; 719 U32 Lba; 720 IR2_PD_INFO PdInfo; 721 } MPI_IR2_RC_EVENT_DATA, MPI_POINTER PTR_MPI_IR2_RC_EVENT_DATA; 722 723 typedef struct _MPI_EVENT_DATA_IR2 724 { 725 U8 TargetID; /* 00h */ 726 U8 Bus; /* 01h */ 727 U8 ReasonCode; /* 02h */ 728 U8 PhysDiskNum; /* 03h */ 729 MPI_IR2_RC_EVENT_DATA IR2EventData; /* 04h */ 730 } MPI_EVENT_DATA_IR2, MPI_POINTER PTR_MPI_EVENT_DATA_IR2, 731 MpiEventDataIR2_t, MPI_POINTER pMpiEventDataIR2_t; 732 733 /* MPI IR2 Event data ReasonCode values */ 734 #define MPI_EVENT_IR2_RC_LD_STATE_CHANGED (0x01) 735 #define MPI_EVENT_IR2_RC_PD_STATE_CHANGED (0x02) 736 #define MPI_EVENT_IR2_RC_BAD_BLOCK_TABLE_FULL (0x03) 737 #define MPI_EVENT_IR2_RC_PD_INSERTED (0x04) 738 #define MPI_EVENT_IR2_RC_PD_REMOVED (0x05) 739 #define MPI_EVENT_IR2_RC_FOREIGN_CFG_DETECTED (0x06) 740 #define MPI_EVENT_IR2_RC_REBUILD_MEDIUM_ERROR (0x07) 741 #define MPI_EVENT_IR2_RC_DUAL_PORT_ADDED (0x08) 742 #define MPI_EVENT_IR2_RC_DUAL_PORT_REMOVED (0x09) 743 744 /* defines for logical disk states */ 745 #define MPI_LD_STATE_OPTIMAL (0x00) 746 #define MPI_LD_STATE_DEGRADED (0x01) 747 #define MPI_LD_STATE_FAILED (0x02) 748 #define MPI_LD_STATE_MISSING (0x03) 749 #define MPI_LD_STATE_OFFLINE (0x04) 750 751 /* defines for physical disk states */ 752 #define MPI_PD_STATE_ONLINE (0x00) 753 #define MPI_PD_STATE_MISSING (0x01) 754 #define MPI_PD_STATE_NOT_COMPATIBLE (0x02) 755 #define MPI_PD_STATE_FAILED (0x03) 756 #define MPI_PD_STATE_INITIALIZING (0x04) 757 #define MPI_PD_STATE_OFFLINE_AT_HOST_REQUEST (0x05) 758 #define MPI_PD_STATE_FAILED_AT_HOST_REQUEST (0x06) 759 #define MPI_PD_STATE_OFFLINE_FOR_ANOTHER_REASON (0xFF) 760 761 /* MPI Link Status Change Event data */ 762 763 typedef struct _EVENT_DATA_LINK_STATUS 764 { 765 U8 State; /* 00h */ 766 U8 Reserved; /* 01h */ 767 U16 Reserved1; /* 02h */ 768 U8 Reserved2; /* 04h */ 769 U8 Port; /* 05h */ 770 U16 Reserved3; /* 06h */ 771 } EVENT_DATA_LINK_STATUS, MPI_POINTER PTR_EVENT_DATA_LINK_STATUS, 772 EventDataLinkStatus_t, MPI_POINTER pEventDataLinkStatus_t; 773 774 #define MPI_EVENT_LINK_STATUS_FAILURE (0x00000000) 775 #define MPI_EVENT_LINK_STATUS_ACTIVE (0x00000001) 776 777 /* MPI Loop State Change Event data */ 778 779 typedef struct _EVENT_DATA_LOOP_STATE 780 { 781 U8 Character4; /* 00h */ 782 U8 Character3; /* 01h */ 783 U8 Type; /* 02h */ 784 U8 Reserved; /* 03h */ 785 U8 Reserved1; /* 04h */ 786 U8 Port; /* 05h */ 787 U16 Reserved2; /* 06h */ 788 } EVENT_DATA_LOOP_STATE, MPI_POINTER PTR_EVENT_DATA_LOOP_STATE, 789 EventDataLoopState_t, MPI_POINTER pEventDataLoopState_t; 790 791 #define MPI_EVENT_LOOP_STATE_CHANGE_LIP (0x0001) 792 #define MPI_EVENT_LOOP_STATE_CHANGE_LPE (0x0002) 793 #define MPI_EVENT_LOOP_STATE_CHANGE_LPB (0x0003) 794 795 /* MPI LOGOUT Event data */ 796 797 typedef struct _EVENT_DATA_LOGOUT 798 { 799 U32 NPortID; /* 00h */ 800 U8 AliasIndex; /* 04h */ 801 U8 Port; /* 05h */ 802 U16 Reserved1; /* 06h */ 803 } EVENT_DATA_LOGOUT, MPI_POINTER PTR_EVENT_DATA_LOGOUT, 804 EventDataLogout_t, MPI_POINTER pEventDataLogout_t; 805 806 #define MPI_EVENT_LOGOUT_ALL_ALIASES (0xFF) 807 808 /* SAS SES Event data */ 809 810 typedef struct _EVENT_DATA_SAS_SES 811 { 812 U8 PhyNum; /* 00h */ 813 U8 Port; /* 01h */ 814 U8 PortWidth; /* 02h */ 815 U8 Reserved1; /* 04h */ 816 } EVENT_DATA_SAS_SES, MPI_POINTER PTR_EVENT_DATA_SAS_SES, 817 MpiEventDataSasSes_t, MPI_POINTER pMpiEventDataSasSes_t; 818 819 /* SAS Broadcast Primitive Event data */ 820 821 typedef struct _EVENT_DATA_SAS_BROADCAST_PRIMITIVE 822 { 823 U8 PhyNum; /* 00h */ 824 U8 Port; /* 01h */ 825 U8 PortWidth; /* 02h */ 826 U8 Primitive; /* 04h */ 827 } EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 828 MPI_POINTER PTR_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 829 MpiEventDataSasBroadcastPrimitive_t, 830 MPI_POINTER pMpiEventDataSasBroadcastPrimitive_t; 831 832 #define MPI_EVENT_PRIMITIVE_CHANGE (0x01) 833 #define MPI_EVENT_PRIMITIVE_EXPANDER (0x03) 834 #define MPI_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04) 835 #define MPI_EVENT_PRIMITIVE_RESERVED3 (0x05) 836 #define MPI_EVENT_PRIMITIVE_RESERVED4 (0x06) 837 #define MPI_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07) 838 #define MPI_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08) 839 840 /* SAS Phy Link Status Event data */ 841 842 typedef struct _EVENT_DATA_SAS_PHY_LINK_STATUS 843 { 844 U8 PhyNum; /* 00h */ 845 U8 LinkRates; /* 01h */ 846 U16 DevHandle; /* 02h */ 847 U64 SASAddress; /* 04h */ 848 } EVENT_DATA_SAS_PHY_LINK_STATUS, MPI_POINTER PTR_EVENT_DATA_SAS_PHY_LINK_STATUS, 849 MpiEventDataSasPhyLinkStatus_t, MPI_POINTER pMpiEventDataSasPhyLinkStatus_t; 850 851 /* defines for the LinkRates field of the SAS PHY Link Status event */ 852 #define MPI_EVENT_SAS_PLS_LR_CURRENT_MASK (0xF0) 853 #define MPI_EVENT_SAS_PLS_LR_CURRENT_SHIFT (4) 854 #define MPI_EVENT_SAS_PLS_LR_PREVIOUS_MASK (0x0F) 855 #define MPI_EVENT_SAS_PLS_LR_PREVIOUS_SHIFT (0) 856 #define MPI_EVENT_SAS_PLS_LR_RATE_UNKNOWN (0x00) 857 #define MPI_EVENT_SAS_PLS_LR_RATE_PHY_DISABLED (0x01) 858 #define MPI_EVENT_SAS_PLS_LR_RATE_FAILED_SPEED_NEGOTIATION (0x02) 859 #define MPI_EVENT_SAS_PLS_LR_RATE_SATA_OOB_COMPLETE (0x03) 860 #define MPI_EVENT_SAS_PLS_LR_RATE_1_5 (0x08) 861 #define MPI_EVENT_SAS_PLS_LR_RATE_3_0 (0x09) 862 #define MPI_EVENT_SAS_PLS_LR_RATE_6_0 (0x0A) 863 864 /* SAS Discovery Event data */ 865 866 typedef struct _EVENT_DATA_SAS_DISCOVERY 867 { 868 U32 DiscoveryStatus; /* 00h */ 869 U32 Reserved1; /* 04h */ 870 } EVENT_DATA_SAS_DISCOVERY, MPI_POINTER PTR_EVENT_DATA_SAS_DISCOVERY, 871 EventDataSasDiscovery_t, MPI_POINTER pEventDataSasDiscovery_t; 872 873 #define MPI_EVENT_SAS_DSCVRY_COMPLETE (0x00000000) 874 #define MPI_EVENT_SAS_DSCVRY_IN_PROGRESS (0x00000001) 875 #define MPI_EVENT_SAS_DSCVRY_PHY_BITS_MASK (0xFFFF0000) 876 #define MPI_EVENT_SAS_DSCVRY_PHY_BITS_SHIFT (16) 877 878 /* SAS Discovery Errror Event data */ 879 880 typedef struct _EVENT_DATA_DISCOVERY_ERROR 881 { 882 U32 DiscoveryStatus; /* 00h */ 883 U8 Port; /* 04h */ 884 U8 Reserved1; /* 05h */ 885 U16 Reserved2; /* 06h */ 886 } EVENT_DATA_DISCOVERY_ERROR, MPI_POINTER PTR_EVENT_DATA_DISCOVERY_ERROR, 887 EventDataDiscoveryError_t, MPI_POINTER pEventDataDiscoveryError_t; 888 889 #define MPI_EVENT_DSCVRY_ERR_DS_LOOP_DETECTED (0x00000001) 890 #define MPI_EVENT_DSCVRY_ERR_DS_UNADDRESSABLE_DEVICE (0x00000002) 891 #define MPI_EVENT_DSCVRY_ERR_DS_MULTIPLE_PORTS (0x00000004) 892 #define MPI_EVENT_DSCVRY_ERR_DS_EXPANDER_ERR (0x00000008) 893 #define MPI_EVENT_DSCVRY_ERR_DS_SMP_TIMEOUT (0x00000010) 894 #define MPI_EVENT_DSCVRY_ERR_DS_OUT_ROUTE_ENTRIES (0x00000020) 895 #define MPI_EVENT_DSCVRY_ERR_DS_INDEX_NOT_EXIST (0x00000040) 896 #define MPI_EVENT_DSCVRY_ERR_DS_SMP_FUNCTION_FAILED (0x00000080) 897 #define MPI_EVENT_DSCVRY_ERR_DS_SMP_CRC_ERROR (0x00000100) 898 #define MPI_EVENT_DSCVRY_ERR_DS_MULTPL_SUBTRACTIVE (0x00000200) 899 #define MPI_EVENT_DSCVRY_ERR_DS_TABLE_TO_TABLE (0x00000400) 900 #define MPI_EVENT_DSCVRY_ERR_DS_UNSUPPORTED_DEVICE (0x00000800) 901 #define MPI_EVENT_DSCVRY_ERR_DS_MAX_SATA_TARGETS (0x00001000) 902 #define MPI_EVENT_DSCVRY_ERR_DS_MULTI_PORT_DOMAIN (0x00002000) 903 #define MPI_EVENT_DSCVRY_ERR_DS_SATA_INIT_FAILURE (0x00004000) 904 905 /* SAS SMP Error Event data */ 906 907 typedef struct _EVENT_DATA_SAS_SMP_ERROR 908 { 909 U8 Status; /* 00h */ 910 U8 Port; /* 01h */ 911 U8 SMPFunctionResult; /* 02h */ 912 U8 Reserved1; /* 03h */ 913 U64 SASAddress; /* 04h */ 914 } EVENT_DATA_SAS_SMP_ERROR, MPI_POINTER PTR_EVENT_DATA_SAS_SMP_ERROR, 915 MpiEventDataSasSmpError_t, MPI_POINTER pMpiEventDataSasSmpError_t; 916 917 /* defines for the Status field of the SAS SMP Error event */ 918 #define MPI_EVENT_SAS_SMP_FUNCTION_RESULT_VALID (0x00) 919 #define MPI_EVENT_SAS_SMP_CRC_ERROR (0x01) 920 #define MPI_EVENT_SAS_SMP_TIMEOUT (0x02) 921 #define MPI_EVENT_SAS_SMP_NO_DESTINATION (0x03) 922 #define MPI_EVENT_SAS_SMP_BAD_DESTINATION (0x04) 923 924 /* SAS Initiator Device Status Change Event data */ 925 926 typedef struct _EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE 927 { 928 U8 ReasonCode; /* 00h */ 929 U8 Port; /* 01h */ 930 U16 DevHandle; /* 02h */ 931 U64 SASAddress; /* 04h */ 932 } EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 933 MPI_POINTER PTR_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 934 MpiEventDataSasInitDevStatusChange_t, 935 MPI_POINTER pMpiEventDataSasInitDevStatusChange_t; 936 937 /* defines for the ReasonCode field of the SAS Initiator Device Status Change event */ 938 #define MPI_EVENT_SAS_INIT_RC_ADDED (0x01) 939 #define MPI_EVENT_SAS_INIT_RC_REMOVED (0x02) 940 #define MPI_EVENT_SAS_INIT_RC_INACCESSIBLE (0x03) 941 942 /* SAS Initiator Device Table Overflow Event data */ 943 944 typedef struct _EVENT_DATA_SAS_INIT_TABLE_OVERFLOW 945 { 946 U8 MaxInit; /* 00h */ 947 U8 CurrentInit; /* 01h */ 948 U16 Reserved1; /* 02h */ 949 U64 SASAddress; /* 04h */ 950 } EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 951 MPI_POINTER PTR_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 952 MpiEventDataSasInitTableOverflow_t, 953 MPI_POINTER pMpiEventDataSasInitTableOverflow_t; 954 955 /* SAS Expander Status Change Event data */ 956 957 typedef struct _EVENT_DATA_SAS_EXPANDER_STATUS_CHANGE 958 { 959 U8 ReasonCode; /* 00h */ 960 U8 Reserved1; /* 01h */ 961 U16 Reserved2; /* 02h */ 962 U8 PhysicalPort; /* 04h */ 963 U8 Reserved3; /* 05h */ 964 U16 EnclosureHandle; /* 06h */ 965 U64 SASAddress; /* 08h */ 966 U32 DiscoveryStatus; /* 10h */ 967 U16 DevHandle; /* 14h */ 968 U16 ParentDevHandle; /* 16h */ 969 U16 ExpanderChangeCount; /* 18h */ 970 U16 ExpanderRouteIndexes; /* 1Ah */ 971 U8 NumPhys; /* 1Ch */ 972 U8 SASLevel; /* 1Dh */ 973 U8 Flags; /* 1Eh */ 974 U8 Reserved4; /* 1Fh */ 975 } EVENT_DATA_SAS_EXPANDER_STATUS_CHANGE, 976 MPI_POINTER PTR_EVENT_DATA_SAS_EXPANDER_STATUS_CHANGE, 977 MpiEventDataSasExpanderStatusChange_t, 978 MPI_POINTER pMpiEventDataSasExpanderStatusChange_t; 979 980 /* values for ReasonCode field of SAS Expander Status Change Event data */ 981 #define MPI_EVENT_SAS_EXP_RC_ADDED (0x00) 982 #define MPI_EVENT_SAS_EXP_RC_NOT_RESPONDING (0x01) 983 984 /* values for DiscoveryStatus field of SAS Expander Status Change Event data */ 985 #define MPI_EVENT_SAS_EXP_DS_LOOP_DETECTED (0x00000001) 986 #define MPI_EVENT_SAS_EXP_DS_UNADDRESSABLE_DEVICE (0x00000002) 987 #define MPI_EVENT_SAS_EXP_DS_MULTIPLE_PORTS (0x00000004) 988 #define MPI_EVENT_SAS_EXP_DS_EXPANDER_ERR (0x00000008) 989 #define MPI_EVENT_SAS_EXP_DS_SMP_TIMEOUT (0x00000010) 990 #define MPI_EVENT_SAS_EXP_DS_OUT_ROUTE_ENTRIES (0x00000020) 991 #define MPI_EVENT_SAS_EXP_DS_INDEX_NOT_EXIST (0x00000040) 992 #define MPI_EVENT_SAS_EXP_DS_SMP_FUNCTION_FAILED (0x00000080) 993 #define MPI_EVENT_SAS_EXP_DS_SMP_CRC_ERROR (0x00000100) 994 #define MPI_EVENT_SAS_EXP_DS_SUBTRACTIVE_LINK (0x00000200) 995 #define MPI_EVENT_SAS_EXP_DS_TABLE_LINK (0x00000400) 996 #define MPI_EVENT_SAS_EXP_DS_UNSUPPORTED_DEVICE (0x00000800) 997 998 /* values for Flags field of SAS Expander Status Change Event data */ 999 #define MPI_EVENT_SAS_EXP_FLAGS_ROUTE_TABLE_CONFIG (0x02) 1000 #define MPI_EVENT_SAS_EXP_FLAGS_CONFIG_IN_PROGRESS (0x01) 1001 1002 /***************************************************************************** 1003 * 1004 * F i r m w a r e L o a d M e s s a g e s 1005 * 1006 *****************************************************************************/ 1007 1008 /****************************************************************************/ 1009 /* Firmware Download message and associated structures */ 1010 /****************************************************************************/ 1011 1012 typedef struct _MSG_FW_DOWNLOAD 1013 { 1014 U8 ImageType; /* 00h */ 1015 U8 Reserved; /* 01h */ 1016 U8 ChainOffset; /* 02h */ 1017 U8 Function; /* 03h */ 1018 U8 Reserved1[3]; /* 04h */ 1019 U8 MsgFlags; /* 07h */ 1020 U32 MsgContext; /* 08h */ 1021 SGE_MPI_UNION SGL; /* 0Ch */ 1022 } MSG_FW_DOWNLOAD, MPI_POINTER PTR_MSG_FW_DOWNLOAD, 1023 FWDownload_t, MPI_POINTER pFWDownload_t; 1024 1025 #define MPI_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01) 1026 1027 #define MPI_FW_DOWNLOAD_ITYPE_RESERVED (0x00) 1028 #define MPI_FW_DOWNLOAD_ITYPE_FW (0x01) 1029 #define MPI_FW_DOWNLOAD_ITYPE_BIOS (0x02) 1030 #define MPI_FW_DOWNLOAD_ITYPE_NVDATA (0x03) 1031 #define MPI_FW_DOWNLOAD_ITYPE_BOOTLOADER (0x04) 1032 #define MPI_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06) 1033 #define MPI_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07) 1034 #define MPI_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08) 1035 #define MPI_FW_DOWNLOAD_ITYPE_MEGARAID (0x09) 1036 #define MPI_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1037 1038 typedef struct _FWDownloadTCSGE 1039 { 1040 U8 Reserved; /* 00h */ 1041 U8 ContextSize; /* 01h */ 1042 U8 DetailsLength; /* 02h */ 1043 U8 Flags; /* 03h */ 1044 U32 Reserved_0100_Checksum; /* 04h */ /* obsolete Checksum */ 1045 U32 ImageOffset; /* 08h */ 1046 U32 ImageSize; /* 0Ch */ 1047 } FW_DOWNLOAD_TCSGE, MPI_POINTER PTR_FW_DOWNLOAD_TCSGE, 1048 FWDownloadTCSGE_t, MPI_POINTER pFWDownloadTCSGE_t; 1049 1050 /* Firmware Download reply */ 1051 typedef struct _MSG_FW_DOWNLOAD_REPLY 1052 { 1053 U8 ImageType; /* 00h */ 1054 U8 Reserved; /* 01h */ 1055 U8 MsgLength; /* 02h */ 1056 U8 Function; /* 03h */ 1057 U8 Reserved1[3]; /* 04h */ 1058 U8 MsgFlags; /* 07h */ 1059 U32 MsgContext; /* 08h */ 1060 U16 Reserved2; /* 0Ch */ 1061 U16 IOCStatus; /* 0Eh */ 1062 U32 IOCLogInfo; /* 10h */ 1063 } MSG_FW_DOWNLOAD_REPLY, MPI_POINTER PTR_MSG_FW_DOWNLOAD_REPLY, 1064 FWDownloadReply_t, MPI_POINTER pFWDownloadReply_t; 1065 1066 /****************************************************************************/ 1067 /* Firmware Upload message and associated structures */ 1068 /****************************************************************************/ 1069 1070 typedef struct _MSG_FW_UPLOAD 1071 { 1072 U8 ImageType; /* 00h */ 1073 U8 Reserved; /* 01h */ 1074 U8 ChainOffset; /* 02h */ 1075 U8 Function; /* 03h */ 1076 U8 Reserved1[3]; /* 04h */ 1077 U8 MsgFlags; /* 07h */ 1078 U32 MsgContext; /* 08h */ 1079 SGE_MPI_UNION SGL; /* 0Ch */ 1080 } MSG_FW_UPLOAD, MPI_POINTER PTR_MSG_FW_UPLOAD, 1081 FWUpload_t, MPI_POINTER pFWUpload_t; 1082 1083 #define MPI_FW_UPLOAD_ITYPE_FW_IOC_MEM (0x00) 1084 #define MPI_FW_UPLOAD_ITYPE_FW_FLASH (0x01) 1085 #define MPI_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02) 1086 #define MPI_FW_UPLOAD_ITYPE_NVDATA (0x03) 1087 #define MPI_FW_UPLOAD_ITYPE_BOOTLOADER (0x04) 1088 #define MPI_FW_UPLOAD_ITYPE_FW_BACKUP (0x05) 1089 #define MPI_FW_UPLOAD_ITYPE_MANUFACTURING (0x06) 1090 #define MPI_FW_UPLOAD_ITYPE_CONFIG_1 (0x07) 1091 #define MPI_FW_UPLOAD_ITYPE_CONFIG_2 (0x08) 1092 #define MPI_FW_UPLOAD_ITYPE_MEGARAID (0x09) 1093 #define MPI_FW_UPLOAD_ITYPE_COMPLETE (0x0A) 1094 #define MPI_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1095 1096 typedef struct _FWUploadTCSGE 1097 { 1098 U8 Reserved; /* 00h */ 1099 U8 ContextSize; /* 01h */ 1100 U8 DetailsLength; /* 02h */ 1101 U8 Flags; /* 03h */ 1102 U32 Reserved1; /* 04h */ 1103 U32 ImageOffset; /* 08h */ 1104 U32 ImageSize; /* 0Ch */ 1105 } FW_UPLOAD_TCSGE, MPI_POINTER PTR_FW_UPLOAD_TCSGE, 1106 FWUploadTCSGE_t, MPI_POINTER pFWUploadTCSGE_t; 1107 1108 /* Firmware Upload reply */ 1109 typedef struct _MSG_FW_UPLOAD_REPLY 1110 { 1111 U8 ImageType; /* 00h */ 1112 U8 Reserved; /* 01h */ 1113 U8 MsgLength; /* 02h */ 1114 U8 Function; /* 03h */ 1115 U8 Reserved1[3]; /* 04h */ 1116 U8 MsgFlags; /* 07h */ 1117 U32 MsgContext; /* 08h */ 1118 U16 Reserved2; /* 0Ch */ 1119 U16 IOCStatus; /* 0Eh */ 1120 U32 IOCLogInfo; /* 10h */ 1121 U32 ActualImageSize; /* 14h */ 1122 } MSG_FW_UPLOAD_REPLY, MPI_POINTER PTR_MSG_FW_UPLOAD_REPLY, 1123 FWUploadReply_t, MPI_POINTER pFWUploadReply_t; 1124 1125 typedef struct _MPI_FW_HEADER 1126 { 1127 U32 ArmBranchInstruction0; /* 00h */ 1128 U32 Signature0; /* 04h */ 1129 U32 Signature1; /* 08h */ 1130 U32 Signature2; /* 0Ch */ 1131 U32 ArmBranchInstruction1; /* 10h */ 1132 U32 ArmBranchInstruction2; /* 14h */ 1133 U32 Reserved; /* 18h */ 1134 U32 Checksum; /* 1Ch */ 1135 U16 VendorId; /* 20h */ 1136 U16 ProductId; /* 22h */ 1137 MPI_FW_VERSION FWVersion; /* 24h */ 1138 U32 SeqCodeVersion; /* 28h */ 1139 U32 ImageSize; /* 2Ch */ 1140 U32 NextImageHeaderOffset; /* 30h */ 1141 U32 LoadStartAddress; /* 34h */ 1142 U32 IopResetVectorValue; /* 38h */ 1143 U32 IopResetRegAddr; /* 3Ch */ 1144 U32 VersionNameWhat; /* 40h */ 1145 U8 VersionName[32]; /* 44h */ 1146 U32 VendorNameWhat; /* 64h */ 1147 U8 VendorName[32]; /* 68h */ 1148 } MPI_FW_HEADER, MPI_POINTER PTR_MPI_FW_HEADER, 1149 MpiFwHeader_t, MPI_POINTER pMpiFwHeader_t; 1150 1151 #define MPI_FW_HEADER_WHAT_SIGNATURE (0x29232840) 1152 1153 /* defines for using the ProductId field */ 1154 #define MPI_FW_HEADER_PID_TYPE_MASK (0xF000) 1155 #define MPI_FW_HEADER_PID_TYPE_SCSI (0x0000) 1156 #define MPI_FW_HEADER_PID_TYPE_FC (0x1000) 1157 #define MPI_FW_HEADER_PID_TYPE_SAS (0x2000) 1158 1159 #define MPI_FW_HEADER_SIGNATURE_0 (0x5AEAA55A) 1160 #define MPI_FW_HEADER_SIGNATURE_1 (0xA55AEAA5) 1161 #define MPI_FW_HEADER_SIGNATURE_2 (0x5AA55AEA) 1162 1163 #define MPI_FW_HEADER_PID_PROD_MASK (0x0F00) 1164 #define MPI_FW_HEADER_PID_PROD_INITIATOR_SCSI (0x0100) 1165 #define MPI_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200) 1166 #define MPI_FW_HEADER_PID_PROD_TARGET_SCSI (0x0300) 1167 #define MPI_FW_HEADER_PID_PROD_IM_SCSI (0x0400) 1168 #define MPI_FW_HEADER_PID_PROD_IS_SCSI (0x0500) 1169 #define MPI_FW_HEADER_PID_PROD_CTX_SCSI (0x0600) 1170 #define MPI_FW_HEADER_PID_PROD_IR_SCSI (0x0700) 1171 1172 #define MPI_FW_HEADER_PID_FAMILY_MASK (0x00FF) 1173 /* SCSI */ 1174 #define MPI_FW_HEADER_PID_FAMILY_1030A0_SCSI (0x0001) 1175 #define MPI_FW_HEADER_PID_FAMILY_1030B0_SCSI (0x0002) 1176 #define MPI_FW_HEADER_PID_FAMILY_1030B1_SCSI (0x0003) 1177 #define MPI_FW_HEADER_PID_FAMILY_1030C0_SCSI (0x0004) 1178 #define MPI_FW_HEADER_PID_FAMILY_1020A0_SCSI (0x0005) 1179 #define MPI_FW_HEADER_PID_FAMILY_1020B0_SCSI (0x0006) 1180 #define MPI_FW_HEADER_PID_FAMILY_1020B1_SCSI (0x0007) 1181 #define MPI_FW_HEADER_PID_FAMILY_1020C0_SCSI (0x0008) 1182 #define MPI_FW_HEADER_PID_FAMILY_1035A0_SCSI (0x0009) 1183 #define MPI_FW_HEADER_PID_FAMILY_1035B0_SCSI (0x000A) 1184 #define MPI_FW_HEADER_PID_FAMILY_1030TA0_SCSI (0x000B) 1185 #define MPI_FW_HEADER_PID_FAMILY_1020TA0_SCSI (0x000C) 1186 /* Fibre Channel */ 1187 #define MPI_FW_HEADER_PID_FAMILY_909_FC (0x0000) 1188 #define MPI_FW_HEADER_PID_FAMILY_919_FC (0x0001) /* 919 and 929 */ 1189 #define MPI_FW_HEADER_PID_FAMILY_919X_FC (0x0002) /* 919X and 929X */ 1190 #define MPI_FW_HEADER_PID_FAMILY_919XL_FC (0x0003) /* 919XL and 929XL */ 1191 #define MPI_FW_HEADER_PID_FAMILY_939X_FC (0x0004) /* 939X and 949X */ 1192 #define MPI_FW_HEADER_PID_FAMILY_959_FC (0x0005) 1193 #define MPI_FW_HEADER_PID_FAMILY_949E_FC (0x0006) 1194 /* SAS */ 1195 #define MPI_FW_HEADER_PID_FAMILY_1064_SAS (0x0001) 1196 #define MPI_FW_HEADER_PID_FAMILY_1068_SAS (0x0002) 1197 #define MPI_FW_HEADER_PID_FAMILY_1078_SAS (0x0003) 1198 #define MPI_FW_HEADER_PID_FAMILY_106xE_SAS (0x0004) /* 1068E, 1066E, and 1064E */ 1199 1200 typedef struct _MPI_EXT_IMAGE_HEADER 1201 { 1202 U8 ImageType; /* 00h */ 1203 U8 Reserved; /* 01h */ 1204 U16 Reserved1; /* 02h */ 1205 U32 Checksum; /* 04h */ 1206 U32 ImageSize; /* 08h */ 1207 U32 NextImageHeaderOffset; /* 0Ch */ 1208 U32 LoadStartAddress; /* 10h */ 1209 U32 Reserved2; /* 14h */ 1210 } MPI_EXT_IMAGE_HEADER, MPI_POINTER PTR_MPI_EXT_IMAGE_HEADER, 1211 MpiExtImageHeader_t, MPI_POINTER pMpiExtImageHeader_t; 1212 1213 /* defines for the ImageType field */ 1214 #define MPI_EXT_IMAGE_TYPE_UNSPECIFIED (0x00) 1215 #define MPI_EXT_IMAGE_TYPE_FW (0x01) 1216 #define MPI_EXT_IMAGE_TYPE_NVDATA (0x03) 1217 #define MPI_EXT_IMAGE_TYPE_BOOTLOADER (0x04) 1218 #define MPI_EXT_IMAGE_TYPE_INITIALIZATION (0x05) 1219 1220 #endif