Andrew Kelley d5100dc815 stage2: fix frame_address AIR instruction ...

Various places were assuming different union tags. Now it is
consistently a no-op instruction, just like the similar
instruction ret_addr.

2022-02-28 13:38:33 -07:00

..

bits.zig

stage2 AArch64: remove MIR load_memory instruction

2022-02-23 21:57:59 +01:00

CodeGen.zig

stage2: fix frame_address AIR instruction

2022-02-28 13:38:33 -07:00

Emit.zig

macho: redo selection of segment/section for decls and consts

2022-02-25 21:59:19 +01:00

Mir.zig

stage2 AArch64: more support for MCValue.got_load and direct_load

2022-02-23 21:58:13 +01:00