Files
zig/lib/std/target/cpu/AArch64Cpu.zig
2020-01-19 20:53:18 -05:00

481 lines
12 KiB
Zig

const feature = @import("std").target.feature;
const CpuInfo = @import("std").target.cpu.CpuInfo;
pub const AArch64Cpu = enum {
AppleLatest,
CortexA35,
CortexA53,
CortexA55,
CortexA57,
CortexA65,
CortexA65ae,
CortexA72,
CortexA73,
CortexA75,
CortexA76,
CortexA76ae,
Cyclone,
ExynosM1,
ExynosM2,
ExynosM3,
ExynosM4,
ExynosM5,
Falkor,
Generic,
Kryo,
NeoverseE1,
NeoverseN1,
Saphira,
Thunderx,
Thunderx2t99,
Thunderxt81,
Thunderxt83,
Thunderxt88,
Tsv110,
const FeatureType = feature.AArch64Feature;
pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
return cpu_infos[@enumToInt(self)];
}
pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
CpuInfo(@This(), FeatureType).create(.AppleLatest, "apple-latest", &[_]FeatureType {
.ArithBccFusion,
.ArithCbzFusion,
.ZczFp,
.AlternateSextloadCvtF32Pattern,
.DisableLatencySchedHeuristic,
.Perfmon,
.ZczGp,
.ZczFpWorkaround,
.Zcm,
.FpArmv8,
.FuseCryptoEor,
.FuseAes,
.Cyclone,
}),
CpuInfo(@This(), FeatureType).create(.CortexA35, "cortex-a35", &[_]FeatureType {
.Perfmon,
.FpArmv8,
.Crc,
.A35,
}),
CpuInfo(@This(), FeatureType).create(.CortexA53, "cortex-a53", &[_]FeatureType {
.Perfmon,
.UsePostraScheduler,
.Crc,
.CustomCheapAsMove,
.BalanceFpOps,
.UseAa,
.FpArmv8,
.FuseAes,
.A53,
}),
CpuInfo(@This(), FeatureType).create(.CortexA55, "cortex-a55", &[_]FeatureType {
.Lse,
.Vh,
.Rdm,
.Perfmon,
.Pan,
.Dotprod,
.Crc,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.FpArmv8,
.FuseAes,
.A55,
}),
CpuInfo(@This(), FeatureType).create(.CortexA57, "cortex-a57", &[_]FeatureType {
.Perfmon,
.UsePostraScheduler,
.Crc,
.PredictableSelectExpensive,
.CustomCheapAsMove,
.BalanceFpOps,
.FuseLiterals,
.FpArmv8,
.FuseAes,
.A57,
}),
CpuInfo(@This(), FeatureType).create(.CortexA65, "cortex-a65", &[_]FeatureType {
.Lse,
.Vh,
.Rdm,
.Pan,
.Dotprod,
.Crc,
.Ssbs,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.FpArmv8,
.A65,
}),
CpuInfo(@This(), FeatureType).create(.CortexA65ae, "cortex-a65ae", &[_]FeatureType {
.Lse,
.Vh,
.Rdm,
.Pan,
.Dotprod,
.Crc,
.Ssbs,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.FpArmv8,
.A65,
}),
CpuInfo(@This(), FeatureType).create(.CortexA72, "cortex-a72", &[_]FeatureType {
.Perfmon,
.FpArmv8,
.Crc,
.FuseAes,
.A72,
}),
CpuInfo(@This(), FeatureType).create(.CortexA73, "cortex-a73", &[_]FeatureType {
.Perfmon,
.FpArmv8,
.Crc,
.FuseAes,
.A73,
}),
CpuInfo(@This(), FeatureType).create(.CortexA75, "cortex-a75", &[_]FeatureType {
.Lse,
.Vh,
.Rdm,
.Perfmon,
.Pan,
.Dotprod,
.Crc,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.FpArmv8,
.FuseAes,
.A75,
}),
CpuInfo(@This(), FeatureType).create(.CortexA76, "cortex-a76", &[_]FeatureType {
.Lse,
.Vh,
.Rdm,
.Pan,
.Dotprod,
.Crc,
.Ssbs,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.FpArmv8,
.A76,
}),
CpuInfo(@This(), FeatureType).create(.CortexA76ae, "cortex-a76ae", &[_]FeatureType {
.Lse,
.Vh,
.Rdm,
.Pan,
.Dotprod,
.Crc,
.Ssbs,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.FpArmv8,
.A76,
}),
CpuInfo(@This(), FeatureType).create(.Cyclone, "cyclone", &[_]FeatureType {
.ArithBccFusion,
.ArithCbzFusion,
.ZczFp,
.AlternateSextloadCvtF32Pattern,
.DisableLatencySchedHeuristic,
.Perfmon,
.ZczGp,
.ZczFpWorkaround,
.Zcm,
.FpArmv8,
.FuseCryptoEor,
.FuseAes,
.Cyclone,
}),
CpuInfo(@This(), FeatureType).create(.ExynosM1, "exynos-m1", &[_]FeatureType {
.ZczFp,
.Perfmon,
.UsePostraScheduler,
.Crc,
.UseReciprocalSquareRoot,
.CustomCheapAsMove,
.Force32bitJumpTables,
.SlowMisaligned128store,
.FpArmv8,
.SlowPaired128,
.FuseAes,
.Exynosm1,
}),
CpuInfo(@This(), FeatureType).create(.ExynosM2, "exynos-m2", &[_]FeatureType {
.ZczFp,
.Perfmon,
.UsePostraScheduler,
.Crc,
.CustomCheapAsMove,
.Force32bitJumpTables,
.SlowMisaligned128store,
.FpArmv8,
.SlowPaired128,
.FuseAes,
.Exynosm2,
}),
CpuInfo(@This(), FeatureType).create(.ExynosM3, "exynos-m3", &[_]FeatureType {
.FuseCsel,
.ZczFp,
.Perfmon,
.UsePostraScheduler,
.Crc,
.PredictableSelectExpensive,
.CustomCheapAsMove,
.Force32bitJumpTables,
.FuseLiterals,
.FuseAddress,
.LslFast,
.FpArmv8,
.FuseAes,
.Exynosm3,
}),
CpuInfo(@This(), FeatureType).create(.ExynosM4, "exynos-m4", &[_]FeatureType {
.ArithBccFusion,
.Vh,
.ArithCbzFusion,
.ZczFp,
.Rdm,
.UsePostraScheduler,
.Ras,
.Force32bitJumpTables,
.Ccpp,
.FuseCsel,
.Pan,
.Uaops,
.FuseLiterals,
.LslFast,
.Lse,
.Perfmon,
.Dotprod,
.Lor,
.FuseArithLogic,
.Crc,
.CustomCheapAsMove,
.FuseAddress,
.ZczGp,
.FpArmv8,
.FuseAes,
.Exynosm4,
}),
CpuInfo(@This(), FeatureType).create(.ExynosM5, "exynos-m5", &[_]FeatureType {
.ArithBccFusion,
.Vh,
.ArithCbzFusion,
.ZczFp,
.Rdm,
.UsePostraScheduler,
.Ras,
.Force32bitJumpTables,
.Ccpp,
.FuseCsel,
.Pan,
.Uaops,
.FuseLiterals,
.LslFast,
.Lse,
.Perfmon,
.Dotprod,
.Lor,
.FuseArithLogic,
.Crc,
.CustomCheapAsMove,
.FuseAddress,
.ZczGp,
.FpArmv8,
.FuseAes,
.Exynosm4,
}),
CpuInfo(@This(), FeatureType).create(.Falkor, "falkor", &[_]FeatureType {
.ZczFp,
.Rdm,
.Perfmon,
.UsePostraScheduler,
.Crc,
.PredictableSelectExpensive,
.CustomCheapAsMove,
.ZczGp,
.FpArmv8,
.SlowStrqroStore,
.LslFast,
.Falkor,
}),
CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
.Trbe,
.Ete,
.FpArmv8,
.FuseAes,
.Neon,
.Perfmon,
.UsePostraScheduler,
}),
CpuInfo(@This(), FeatureType).create(.Kryo, "kryo", &[_]FeatureType {
.ZczFp,
.Perfmon,
.UsePostraScheduler,
.Crc,
.PredictableSelectExpensive,
.CustomCheapAsMove,
.ZczGp,
.FpArmv8,
.LslFast,
.Kryo,
}),
CpuInfo(@This(), FeatureType).create(.NeoverseE1, "neoverse-e1", &[_]FeatureType {
.Lse,
.Vh,
.Rdm,
.Pan,
.Dotprod,
.Crc,
.Ssbs,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.FpArmv8,
.Neoversee1,
}),
CpuInfo(@This(), FeatureType).create(.NeoverseN1, "neoverse-n1", &[_]FeatureType {
.Lse,
.Spe,
.Vh,
.Rdm,
.Pan,
.Dotprod,
.Crc,
.Ssbs,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.FpArmv8,
.Neoversen1,
}),
CpuInfo(@This(), FeatureType).create(.Saphira, "saphira", &[_]FeatureType {
.Spe,
.Vh,
.ZczFp,
.Rdm,
.UsePostraScheduler,
.Dit,
.Am,
.Ras,
.Rcpc,
.Sel2,
.Ccpp,
.Pa,
.Pan,
.Uaops,
.Tracev84,
.Mpam,
.LslFast,
.Lse,
.Nv,
.Perfmon,
.Dotprod,
.TlbRmi,
.Lor,
.Ccidx,
.PredictableSelectExpensive,
.Crc,
.CustomCheapAsMove,
.Fmi,
.ZczGp,
.FpArmv8,
.Saphira,
}),
CpuInfo(@This(), FeatureType).create(.Thunderx, "thunderx", &[_]FeatureType {
.Perfmon,
.UsePostraScheduler,
.Crc,
.FpArmv8,
.PredictableSelectExpensive,
.Thunderx,
}),
CpuInfo(@This(), FeatureType).create(.Thunderx2t99, "thunderx2t99", &[_]FeatureType {
.Lse,
.ArithBccFusion,
.Vh,
.Rdm,
.UsePostraScheduler,
.Crc,
.Lor,
.Pan,
.AggressiveFma,
.FpArmv8,
.PredictableSelectExpensive,
.Thunderx2t99,
}),
CpuInfo(@This(), FeatureType).create(.Thunderxt81, "thunderxt81", &[_]FeatureType {
.Perfmon,
.UsePostraScheduler,
.Crc,
.FpArmv8,
.PredictableSelectExpensive,
.Thunderxt81,
}),
CpuInfo(@This(), FeatureType).create(.Thunderxt83, "thunderxt83", &[_]FeatureType {
.Perfmon,
.UsePostraScheduler,
.Crc,
.FpArmv8,
.PredictableSelectExpensive,
.Thunderxt83,
}),
CpuInfo(@This(), FeatureType).create(.Thunderxt88, "thunderxt88", &[_]FeatureType {
.Perfmon,
.UsePostraScheduler,
.Crc,
.FpArmv8,
.PredictableSelectExpensive,
.Thunderxt88,
}),
CpuInfo(@This(), FeatureType).create(.Tsv110, "tsv110", &[_]FeatureType {
.Lse,
.Spe,
.Vh,
.Rdm,
.Perfmon,
.UsePostraScheduler,
.Pan,
.Dotprod,
.Crc,
.Lor,
.Uaops,
.CustomCheapAsMove,
.Ras,
.Ccpp,
.FpArmv8,
.FuseAes,
.Tsv110,
}),
};
};