481 lines
12 KiB
Zig
481 lines
12 KiB
Zig
const feature = @import("std").target.feature;
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const CpuInfo = @import("std").target.cpu.CpuInfo;
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pub const AArch64Cpu = enum {
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AppleLatest,
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CortexA35,
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CortexA53,
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CortexA55,
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CortexA57,
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CortexA65,
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CortexA65ae,
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CortexA72,
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CortexA73,
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CortexA75,
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CortexA76,
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CortexA76ae,
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Cyclone,
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ExynosM1,
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ExynosM2,
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ExynosM3,
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ExynosM4,
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ExynosM5,
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Falkor,
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Generic,
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Kryo,
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NeoverseE1,
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NeoverseN1,
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Saphira,
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Thunderx,
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Thunderx2t99,
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Thunderxt81,
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Thunderxt83,
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Thunderxt88,
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Tsv110,
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const FeatureType = feature.AArch64Feature;
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pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
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return cpu_infos[@enumToInt(self)];
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}
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pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
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CpuInfo(@This(), FeatureType).create(.AppleLatest, "apple-latest", &[_]FeatureType {
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.ArithBccFusion,
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.ArithCbzFusion,
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.ZczFp,
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.AlternateSextloadCvtF32Pattern,
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.DisableLatencySchedHeuristic,
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.Perfmon,
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.ZczGp,
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.ZczFpWorkaround,
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.Zcm,
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.FpArmv8,
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.FuseCryptoEor,
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.FuseAes,
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.Cyclone,
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}),
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CpuInfo(@This(), FeatureType).create(.CortexA35, "cortex-a35", &[_]FeatureType {
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.Perfmon,
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.FpArmv8,
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.Crc,
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.A35,
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}),
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CpuInfo(@This(), FeatureType).create(.CortexA53, "cortex-a53", &[_]FeatureType {
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.Perfmon,
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.UsePostraScheduler,
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.Crc,
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.CustomCheapAsMove,
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.BalanceFpOps,
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.UseAa,
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.FpArmv8,
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.FuseAes,
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.A53,
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}),
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CpuInfo(@This(), FeatureType).create(.CortexA55, "cortex-a55", &[_]FeatureType {
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.Lse,
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.Vh,
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.Rdm,
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.Perfmon,
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.Pan,
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.Dotprod,
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.Crc,
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.Lor,
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.Uaops,
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.Ras,
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.Rcpc,
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.Ccpp,
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.FpArmv8,
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.FuseAes,
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.A55,
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}),
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CpuInfo(@This(), FeatureType).create(.CortexA57, "cortex-a57", &[_]FeatureType {
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.Perfmon,
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.UsePostraScheduler,
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.Crc,
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.PredictableSelectExpensive,
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.CustomCheapAsMove,
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.BalanceFpOps,
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.FuseLiterals,
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.FpArmv8,
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.FuseAes,
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.A57,
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}),
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CpuInfo(@This(), FeatureType).create(.CortexA65, "cortex-a65", &[_]FeatureType {
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.Lse,
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.Vh,
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.Rdm,
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.Pan,
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.Dotprod,
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.Crc,
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.Ssbs,
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.Lor,
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.Uaops,
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.Ras,
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.Rcpc,
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.Ccpp,
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.FpArmv8,
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.A65,
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}),
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CpuInfo(@This(), FeatureType).create(.CortexA65ae, "cortex-a65ae", &[_]FeatureType {
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.Lse,
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.Vh,
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.Rdm,
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.Pan,
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.Dotprod,
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.Crc,
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.Ssbs,
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.Lor,
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.Uaops,
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.Ras,
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.Rcpc,
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.Ccpp,
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.FpArmv8,
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.A65,
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}),
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CpuInfo(@This(), FeatureType).create(.CortexA72, "cortex-a72", &[_]FeatureType {
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.Perfmon,
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.FpArmv8,
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.Crc,
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.FuseAes,
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.A72,
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}),
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CpuInfo(@This(), FeatureType).create(.CortexA73, "cortex-a73", &[_]FeatureType {
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.Perfmon,
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.FpArmv8,
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.Crc,
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.FuseAes,
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.A73,
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}),
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CpuInfo(@This(), FeatureType).create(.CortexA75, "cortex-a75", &[_]FeatureType {
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.Lse,
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.Vh,
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.Rdm,
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.Perfmon,
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.Pan,
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.Dotprod,
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.Crc,
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.Lor,
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.Uaops,
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.Ras,
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.Rcpc,
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.Ccpp,
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.FpArmv8,
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.FuseAes,
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.A75,
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}),
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CpuInfo(@This(), FeatureType).create(.CortexA76, "cortex-a76", &[_]FeatureType {
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.Lse,
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.Vh,
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.Rdm,
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.Pan,
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.Dotprod,
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.Crc,
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.Ssbs,
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.Lor,
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.Uaops,
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.Ras,
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.Rcpc,
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.Ccpp,
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.FpArmv8,
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.A76,
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}),
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CpuInfo(@This(), FeatureType).create(.CortexA76ae, "cortex-a76ae", &[_]FeatureType {
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.Lse,
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.Vh,
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.Rdm,
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.Pan,
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.Dotprod,
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.Crc,
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.Ssbs,
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.Lor,
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.Uaops,
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.Ras,
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.Rcpc,
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.Ccpp,
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.FpArmv8,
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.A76,
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}),
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CpuInfo(@This(), FeatureType).create(.Cyclone, "cyclone", &[_]FeatureType {
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.ArithBccFusion,
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.ArithCbzFusion,
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.ZczFp,
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.AlternateSextloadCvtF32Pattern,
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.DisableLatencySchedHeuristic,
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.Perfmon,
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.ZczGp,
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.ZczFpWorkaround,
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.Zcm,
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.FpArmv8,
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.FuseCryptoEor,
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.FuseAes,
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.Cyclone,
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}),
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CpuInfo(@This(), FeatureType).create(.ExynosM1, "exynos-m1", &[_]FeatureType {
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.ZczFp,
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.Perfmon,
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.UsePostraScheduler,
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.Crc,
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.UseReciprocalSquareRoot,
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.CustomCheapAsMove,
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.Force32bitJumpTables,
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.SlowMisaligned128store,
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.FpArmv8,
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.SlowPaired128,
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.FuseAes,
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.Exynosm1,
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}),
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CpuInfo(@This(), FeatureType).create(.ExynosM2, "exynos-m2", &[_]FeatureType {
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.ZczFp,
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.Perfmon,
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.UsePostraScheduler,
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.Crc,
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.CustomCheapAsMove,
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.Force32bitJumpTables,
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.SlowMisaligned128store,
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.FpArmv8,
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.SlowPaired128,
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.FuseAes,
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.Exynosm2,
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}),
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CpuInfo(@This(), FeatureType).create(.ExynosM3, "exynos-m3", &[_]FeatureType {
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.FuseCsel,
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.ZczFp,
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.Perfmon,
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.UsePostraScheduler,
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.Crc,
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.PredictableSelectExpensive,
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.CustomCheapAsMove,
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.Force32bitJumpTables,
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.FuseLiterals,
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.FuseAddress,
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.LslFast,
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.FpArmv8,
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.FuseAes,
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.Exynosm3,
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}),
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CpuInfo(@This(), FeatureType).create(.ExynosM4, "exynos-m4", &[_]FeatureType {
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.ArithBccFusion,
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.Vh,
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.ArithCbzFusion,
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.ZczFp,
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.Rdm,
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.UsePostraScheduler,
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.Ras,
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.Force32bitJumpTables,
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.Ccpp,
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.FuseCsel,
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.Pan,
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.Uaops,
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.FuseLiterals,
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.LslFast,
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.Lse,
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.Perfmon,
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.Dotprod,
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.Lor,
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.FuseArithLogic,
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.Crc,
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.CustomCheapAsMove,
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.FuseAddress,
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.ZczGp,
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.FpArmv8,
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.FuseAes,
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.Exynosm4,
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}),
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CpuInfo(@This(), FeatureType).create(.ExynosM5, "exynos-m5", &[_]FeatureType {
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.ArithBccFusion,
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.Vh,
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.ArithCbzFusion,
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.ZczFp,
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.Rdm,
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.UsePostraScheduler,
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.Ras,
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.Force32bitJumpTables,
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.Ccpp,
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.FuseCsel,
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.Pan,
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.Uaops,
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.FuseLiterals,
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.LslFast,
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.Lse,
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.Perfmon,
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.Dotprod,
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.Lor,
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.FuseArithLogic,
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.Crc,
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.CustomCheapAsMove,
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.FuseAddress,
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.ZczGp,
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.FpArmv8,
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.FuseAes,
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.Exynosm4,
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}),
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CpuInfo(@This(), FeatureType).create(.Falkor, "falkor", &[_]FeatureType {
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.ZczFp,
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.Rdm,
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.Perfmon,
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.UsePostraScheduler,
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.Crc,
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.PredictableSelectExpensive,
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.CustomCheapAsMove,
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.ZczGp,
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.FpArmv8,
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.SlowStrqroStore,
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.LslFast,
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.Falkor,
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}),
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CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
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.Trbe,
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.Ete,
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.FpArmv8,
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.FuseAes,
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.Neon,
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.Perfmon,
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.UsePostraScheduler,
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}),
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CpuInfo(@This(), FeatureType).create(.Kryo, "kryo", &[_]FeatureType {
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.ZczFp,
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.Perfmon,
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.UsePostraScheduler,
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.Crc,
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.PredictableSelectExpensive,
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.CustomCheapAsMove,
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.ZczGp,
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.FpArmv8,
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.LslFast,
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.Kryo,
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}),
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CpuInfo(@This(), FeatureType).create(.NeoverseE1, "neoverse-e1", &[_]FeatureType {
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.Lse,
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.Vh,
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.Rdm,
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.Pan,
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.Dotprod,
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.Crc,
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.Ssbs,
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.Lor,
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.Uaops,
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.Ras,
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.Rcpc,
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.Ccpp,
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.FpArmv8,
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.Neoversee1,
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}),
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CpuInfo(@This(), FeatureType).create(.NeoverseN1, "neoverse-n1", &[_]FeatureType {
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.Lse,
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.Spe,
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.Vh,
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.Rdm,
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.Pan,
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.Dotprod,
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.Crc,
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.Ssbs,
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.Lor,
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.Uaops,
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.Ras,
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.Rcpc,
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.Ccpp,
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.FpArmv8,
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.Neoversen1,
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}),
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CpuInfo(@This(), FeatureType).create(.Saphira, "saphira", &[_]FeatureType {
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.Spe,
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.Vh,
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.ZczFp,
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.Rdm,
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.UsePostraScheduler,
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.Dit,
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.Am,
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.Ras,
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.Rcpc,
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.Sel2,
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.Ccpp,
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.Pa,
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.Pan,
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.Uaops,
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.Tracev84,
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.Mpam,
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.LslFast,
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.Lse,
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.Nv,
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.Perfmon,
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.Dotprod,
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.TlbRmi,
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.Lor,
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.Ccidx,
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.PredictableSelectExpensive,
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.Crc,
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.CustomCheapAsMove,
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.Fmi,
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.ZczGp,
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.FpArmv8,
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.Saphira,
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}),
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CpuInfo(@This(), FeatureType).create(.Thunderx, "thunderx", &[_]FeatureType {
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.Perfmon,
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.UsePostraScheduler,
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.Crc,
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.FpArmv8,
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.PredictableSelectExpensive,
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.Thunderx,
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}),
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CpuInfo(@This(), FeatureType).create(.Thunderx2t99, "thunderx2t99", &[_]FeatureType {
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.Lse,
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.ArithBccFusion,
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.Vh,
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.Rdm,
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.UsePostraScheduler,
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.Crc,
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.Lor,
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.Pan,
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.AggressiveFma,
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.FpArmv8,
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.PredictableSelectExpensive,
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.Thunderx2t99,
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}),
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CpuInfo(@This(), FeatureType).create(.Thunderxt81, "thunderxt81", &[_]FeatureType {
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.Perfmon,
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.UsePostraScheduler,
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.Crc,
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.FpArmv8,
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.PredictableSelectExpensive,
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.Thunderxt81,
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}),
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CpuInfo(@This(), FeatureType).create(.Thunderxt83, "thunderxt83", &[_]FeatureType {
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.Perfmon,
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.UsePostraScheduler,
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.Crc,
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.FpArmv8,
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.PredictableSelectExpensive,
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.Thunderxt83,
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}),
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CpuInfo(@This(), FeatureType).create(.Thunderxt88, "thunderxt88", &[_]FeatureType {
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.Perfmon,
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.UsePostraScheduler,
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.Crc,
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.FpArmv8,
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.PredictableSelectExpensive,
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.Thunderxt88,
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}),
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CpuInfo(@This(), FeatureType).create(.Tsv110, "tsv110", &[_]FeatureType {
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.Lse,
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.Spe,
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.Vh,
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.Rdm,
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.Perfmon,
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.UsePostraScheduler,
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.Pan,
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.Dotprod,
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.Crc,
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.Lor,
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.Uaops,
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.CustomCheapAsMove,
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.Ras,
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.Ccpp,
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.FpArmv8,
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.FuseAes,
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.Tsv110,
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}),
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};
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};
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