1231 lines
30 KiB
Zig
1231 lines
30 KiB
Zig
const feature = @import("std").target.feature;
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const CpuInfo = @import("std").target.cpu.CpuInfo;
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pub const ArmCpu = enum {
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Arm1020e,
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Arm1020t,
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Arm1022e,
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Arm10e,
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Arm10tdmi,
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Arm1136jS,
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Arm1136jfS,
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Arm1156t2S,
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Arm1156t2fS,
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Arm1176jS,
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Arm1176jzS,
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Arm1176jzfS,
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Arm710t,
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Arm720t,
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Arm7tdmi,
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Arm7tdmiS,
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Arm8,
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Arm810,
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Arm9,
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Arm920,
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Arm920t,
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Arm922t,
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Arm926ejS,
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Arm940t,
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Arm946eS,
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Arm966eS,
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Arm968eS,
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Arm9e,
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Arm9tdmi,
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CortexA12,
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CortexA15,
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CortexA17,
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CortexA32,
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CortexA35,
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CortexA5,
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CortexA53,
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CortexA55,
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CortexA57,
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CortexA7,
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CortexA72,
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CortexA73,
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CortexA75,
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CortexA76,
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CortexA76ae,
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CortexA8,
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CortexA9,
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CortexM0,
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CortexM0plus,
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CortexM1,
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CortexM23,
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CortexM3,
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CortexM33,
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CortexM35p,
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CortexM4,
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CortexM7,
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CortexR4,
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CortexR4f,
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CortexR5,
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CortexR52,
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CortexR7,
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CortexR8,
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Cyclone,
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Ep9312,
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ExynosM1,
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ExynosM2,
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ExynosM3,
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ExynosM4,
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ExynosM5,
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Generic,
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Iwmmxt,
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Krait,
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Kryo,
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Mpcore,
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Mpcorenovfp,
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NeoverseN1,
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Sc000,
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Sc300,
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Strongarm,
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Strongarm110,
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Strongarm1100,
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Strongarm1110,
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Swift,
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Xscale,
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const FeatureType = feature.ArmFeature;
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pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
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return cpu_infos[@enumToInt(self)];
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}
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pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
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CpuInfo(@This(), FeatureType).create(.Arm1020e, "arm1020e", &[_]FeatureType {
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.V4t,
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.Armv5te,
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}),
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CpuInfo(@This(), FeatureType).create(.Arm1020t, "arm1020t", &[_]FeatureType {
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.V4t,
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.Armv5t,
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}),
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CpuInfo(@This(), FeatureType).create(.Arm1022e, "arm1022e", &[_]FeatureType {
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.V4t,
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.Armv5te,
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}),
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CpuInfo(@This(), FeatureType).create(.Arm10e, "arm10e", &[_]FeatureType {
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.V4t,
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.Armv5te,
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}),
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CpuInfo(@This(), FeatureType).create(.Arm10tdmi, "arm10tdmi", &[_]FeatureType {
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.V4t,
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.Armv5t,
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}),
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CpuInfo(@This(), FeatureType).create(.Arm1136jS, "arm1136j-s", &[_]FeatureType {
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.V4t,
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.Dsp,
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.Armv6,
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}),
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CpuInfo(@This(), FeatureType).create(.Arm1136jfS, "arm1136jf-s", &[_]FeatureType {
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.V4t,
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.Dsp,
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.Armv6,
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.Slowfpvmlx,
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.Fpregs,
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.Vfp2,
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}),
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CpuInfo(@This(), FeatureType).create(.Arm1156t2S, "arm1156t2-s", &[_]FeatureType {
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.V4t,
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.Thumb2,
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.Dsp,
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.Armv6t2,
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}),
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CpuInfo(@This(), FeatureType).create(.Arm1156t2fS, "arm1156t2f-s", &[_]FeatureType {
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.V4t,
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.Thumb2,
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.Dsp,
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.Armv6t2,
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.Slowfpvmlx,
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.Fpregs,
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.Vfp2,
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}),
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CpuInfo(@This(), FeatureType).create(.Arm1176jS, "arm1176j-s", &[_]FeatureType {
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.V4t,
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.Trustzone,
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.Armv6kz,
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}),
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CpuInfo(@This(), FeatureType).create(.Arm1176jzS, "arm1176jz-s", &[_]FeatureType {
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.V4t,
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.Trustzone,
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.Armv6kz,
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}),
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CpuInfo(@This(), FeatureType).create(.Arm1176jzfS, "arm1176jzf-s", &[_]FeatureType {
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.V4t,
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.Trustzone,
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.Armv6kz,
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.Slowfpvmlx,
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.Fpregs,
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.Vfp2,
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}),
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CpuInfo(@This(), FeatureType).create(.Arm710t, "arm710t", &[_]FeatureType {
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.V4t,
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.Armv4t,
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}),
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CpuInfo(@This(), FeatureType).create(.Arm720t, "arm720t", &[_]FeatureType {
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.V4t,
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.Armv4t,
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}),
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CpuInfo(@This(), FeatureType).create(.Arm7tdmi, "arm7tdmi", &[_]FeatureType {
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.V4t,
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.Armv4t,
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}),
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CpuInfo(@This(), FeatureType).create(.Arm7tdmiS, "arm7tdmi-s", &[_]FeatureType {
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.V4t,
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.Armv4t,
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}),
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CpuInfo(@This(), FeatureType).create(.Arm8, "arm8", &[_]FeatureType {
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.Armv4,
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}),
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CpuInfo(@This(), FeatureType).create(.Arm810, "arm810", &[_]FeatureType {
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.Armv4,
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}),
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CpuInfo(@This(), FeatureType).create(.Arm9, "arm9", &[_]FeatureType {
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.V4t,
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.Armv4t,
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}),
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CpuInfo(@This(), FeatureType).create(.Arm920, "arm920", &[_]FeatureType {
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.V4t,
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.Armv4t,
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}),
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CpuInfo(@This(), FeatureType).create(.Arm920t, "arm920t", &[_]FeatureType {
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.V4t,
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.Armv4t,
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}),
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CpuInfo(@This(), FeatureType).create(.Arm922t, "arm922t", &[_]FeatureType {
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.V4t,
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.Armv4t,
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}),
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CpuInfo(@This(), FeatureType).create(.Arm926ejS, "arm926ej-s", &[_]FeatureType {
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.V4t,
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.Armv5te,
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}),
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CpuInfo(@This(), FeatureType).create(.Arm940t, "arm940t", &[_]FeatureType {
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.V4t,
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.Armv4t,
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}),
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CpuInfo(@This(), FeatureType).create(.Arm946eS, "arm946e-s", &[_]FeatureType {
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.V4t,
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.Armv5te,
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}),
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CpuInfo(@This(), FeatureType).create(.Arm966eS, "arm966e-s", &[_]FeatureType {
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.V4t,
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.Armv5te,
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}),
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CpuInfo(@This(), FeatureType).create(.Arm968eS, "arm968e-s", &[_]FeatureType {
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.V4t,
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.Armv5te,
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}),
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CpuInfo(@This(), FeatureType).create(.Arm9e, "arm9e", &[_]FeatureType {
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.V4t,
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.Armv5te,
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}),
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CpuInfo(@This(), FeatureType).create(.Arm9tdmi, "arm9tdmi", &[_]FeatureType {
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.V4t,
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.Armv4t,
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}),
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CpuInfo(@This(), FeatureType).create(.CortexA12, "cortex-a12", &[_]FeatureType {
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.Perfmon,
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.V4t,
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.D32,
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.Fpregs,
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.V7clrex,
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.Dsp,
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.Thumb2,
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.Db,
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.Aclass,
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.Armv7A,
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.AvoidPartialCpsr,
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.RetAddrStack,
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.Mp,
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.Trustzone,
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.Fp16,
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.Vfp4,
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.VmlxForwarding,
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.HwdivArm,
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.Hwdiv,
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.Virtualization,
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.A12,
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}),
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CpuInfo(@This(), FeatureType).create(.CortexA15, "cortex-a15", &[_]FeatureType {
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.Perfmon,
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.V4t,
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.D32,
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.Fpregs,
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.V7clrex,
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.Dsp,
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.Thumb2,
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.Db,
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.Aclass,
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.Armv7A,
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.AvoidPartialCpsr,
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.VldnAlign,
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.DontWidenVmovs,
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.RetAddrStack,
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.Mp,
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.MuxedUnits,
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.SplatVfpNeon,
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.Trustzone,
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.Fp16,
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.Vfp4,
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.HwdivArm,
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.Hwdiv,
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.Virtualization,
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.A15,
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}),
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CpuInfo(@This(), FeatureType).create(.CortexA17, "cortex-a17", &[_]FeatureType {
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.Perfmon,
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.V4t,
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.D32,
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.Fpregs,
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.V7clrex,
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.Dsp,
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.Thumb2,
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.Db,
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.Aclass,
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.Armv7A,
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.AvoidPartialCpsr,
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.RetAddrStack,
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.Mp,
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.Trustzone,
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.Fp16,
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.Vfp4,
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.VmlxForwarding,
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.HwdivArm,
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.Hwdiv,
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.Virtualization,
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.A17,
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}),
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CpuInfo(@This(), FeatureType).create(.CortexA32, "cortex-a32", &[_]FeatureType {
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.HwdivArm,
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.Perfmon,
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.D32,
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.Fpregs,
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.Crc,
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.Mp,
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.Fp16,
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.Dsp,
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.V4t,
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.V7clrex,
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.Db,
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.Aclass,
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.Thumb2,
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.AcquireRelease,
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.Hwdiv,
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.Trustzone,
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.Armv8A,
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.Crypto,
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}),
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CpuInfo(@This(), FeatureType).create(.CortexA35, "cortex-a35", &[_]FeatureType {
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.HwdivArm,
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.Perfmon,
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.D32,
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.Fpregs,
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.Crc,
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.Mp,
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.Fp16,
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.Dsp,
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.V4t,
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.V7clrex,
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.Db,
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.Aclass,
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.Thumb2,
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.AcquireRelease,
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.Hwdiv,
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.Trustzone,
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.Armv8A,
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.Crypto,
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.A35,
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}),
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CpuInfo(@This(), FeatureType).create(.CortexA5, "cortex-a5", &[_]FeatureType {
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.Perfmon,
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.V4t,
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.D32,
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.Fpregs,
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.V7clrex,
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.Dsp,
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.Thumb2,
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.Db,
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.Aclass,
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.Armv7A,
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.RetAddrStack,
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.Slowfpvmlx,
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.Mp,
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.SlowFpBrcc,
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.Trustzone,
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.Fp16,
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.Vfp4,
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.VmlxForwarding,
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.A5,
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}),
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CpuInfo(@This(), FeatureType).create(.CortexA53, "cortex-a53", &[_]FeatureType {
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.HwdivArm,
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.Perfmon,
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.D32,
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.Fpregs,
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.Crc,
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.Mp,
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.Fp16,
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.Dsp,
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.V4t,
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.V7clrex,
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.Db,
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.Aclass,
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.Thumb2,
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.AcquireRelease,
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.Hwdiv,
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.Trustzone,
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.Armv8A,
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.Crypto,
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.Fpao,
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.A53,
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}),
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CpuInfo(@This(), FeatureType).create(.CortexA55, "cortex-a55", &[_]FeatureType {
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.HwdivArm,
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.Perfmon,
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.D32,
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.Fpregs,
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.Crc,
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.Mp,
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.Fp16,
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.Dsp,
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.V4t,
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.V7clrex,
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.Db,
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.Aclass,
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.Thumb2,
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.Ras,
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.AcquireRelease,
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.Hwdiv,
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.Trustzone,
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.Armv82A,
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.Dotprod,
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.A55,
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}),
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CpuInfo(@This(), FeatureType).create(.CortexA57, "cortex-a57", &[_]FeatureType {
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.HwdivArm,
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.Perfmon,
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.D32,
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.Fpregs,
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.Crc,
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.Mp,
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.Fp16,
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.Dsp,
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.V4t,
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.V7clrex,
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.Db,
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.Aclass,
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.Thumb2,
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.AcquireRelease,
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.Hwdiv,
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.Trustzone,
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.Armv8A,
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.AvoidPartialCpsr,
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.CheapPredicableCpsr,
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.Crypto,
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.Fpao,
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.A57,
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}),
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CpuInfo(@This(), FeatureType).create(.CortexA7, "cortex-a7", &[_]FeatureType {
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.Perfmon,
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.V4t,
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.D32,
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.Fpregs,
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.V7clrex,
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.Dsp,
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.Thumb2,
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.Db,
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.Aclass,
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.Armv7A,
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.RetAddrStack,
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.Slowfpvmlx,
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.VmlxHazards,
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.Mp,
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.SlowFpBrcc,
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.Trustzone,
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.Fp16,
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.Vfp4,
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.VmlxForwarding,
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.HwdivArm,
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.Hwdiv,
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.Virtualization,
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.A7,
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}),
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CpuInfo(@This(), FeatureType).create(.CortexA72, "cortex-a72", &[_]FeatureType {
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.HwdivArm,
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.Perfmon,
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|
.D32,
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.Fpregs,
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.Crc,
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.Mp,
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|
.Fp16,
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.Dsp,
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|
.V4t,
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.V7clrex,
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|
.Db,
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|
.Aclass,
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|
.Thumb2,
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|
.AcquireRelease,
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|
.Hwdiv,
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|
.Trustzone,
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.Armv8A,
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.Crypto,
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.A72,
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}),
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CpuInfo(@This(), FeatureType).create(.CortexA73, "cortex-a73", &[_]FeatureType {
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.HwdivArm,
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.Perfmon,
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|
.D32,
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|
.Fpregs,
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.Crc,
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|
.Mp,
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|
.Fp16,
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|
.Dsp,
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|
.V4t,
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|
.V7clrex,
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|
.Db,
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|
.Aclass,
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|
.Thumb2,
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|
.AcquireRelease,
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|
.Hwdiv,
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|
.Trustzone,
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.Armv8A,
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.Crypto,
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|
.A73,
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}),
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CpuInfo(@This(), FeatureType).create(.CortexA75, "cortex-a75", &[_]FeatureType {
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.HwdivArm,
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|
.Perfmon,
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|
.D32,
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|
.Fpregs,
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|
.Crc,
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|
.Mp,
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|
.Fp16,
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.Dsp,
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|
.V4t,
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|
.V7clrex,
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|
.Db,
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|
.Aclass,
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|
.Thumb2,
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|
.Ras,
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|
.AcquireRelease,
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|
.Hwdiv,
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|
.Trustzone,
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.Armv82A,
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.Dotprod,
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.A75,
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}),
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CpuInfo(@This(), FeatureType).create(.CortexA76, "cortex-a76", &[_]FeatureType {
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.HwdivArm,
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|
.Perfmon,
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|
.D32,
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.Fpregs,
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.Crc,
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|
.Mp,
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|
.Fp16,
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|
.Dsp,
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|
.V4t,
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.V7clrex,
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|
.Db,
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|
.Aclass,
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|
.Thumb2,
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|
.Ras,
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|
.AcquireRelease,
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|
.Hwdiv,
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|
.Trustzone,
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|
.Armv82A,
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.Crypto,
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.Dotprod,
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.Fullfp16,
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|
.A76,
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}),
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CpuInfo(@This(), FeatureType).create(.CortexA76ae, "cortex-a76ae", &[_]FeatureType {
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.HwdivArm,
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.Perfmon,
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.D32,
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|
.Fpregs,
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.Crc,
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.Mp,
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|
.Fp16,
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|
.Dsp,
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|
.V4t,
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|
.V7clrex,
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|
.Db,
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|
.Aclass,
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|
.Thumb2,
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|
.Ras,
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|
.AcquireRelease,
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.Hwdiv,
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.Trustzone,
|
|
.Armv82A,
|
|
.Crypto,
|
|
.Dotprod,
|
|
.Fullfp16,
|
|
.A76,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.CortexA8, "cortex-a8", &[_]FeatureType {
|
|
.Perfmon,
|
|
.V4t,
|
|
.D32,
|
|
.Fpregs,
|
|
.V7clrex,
|
|
.Dsp,
|
|
.Thumb2,
|
|
.Db,
|
|
.Aclass,
|
|
.Armv7A,
|
|
.RetAddrStack,
|
|
.Slowfpvmlx,
|
|
.VmlxHazards,
|
|
.NonpipelinedVfp,
|
|
.SlowFpBrcc,
|
|
.Trustzone,
|
|
.VmlxForwarding,
|
|
.A8,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.CortexA9, "cortex-a9", &[_]FeatureType {
|
|
.Perfmon,
|
|
.V4t,
|
|
.D32,
|
|
.Fpregs,
|
|
.V7clrex,
|
|
.Dsp,
|
|
.Thumb2,
|
|
.Db,
|
|
.Aclass,
|
|
.Armv7A,
|
|
.AvoidPartialCpsr,
|
|
.VldnAlign,
|
|
.ExpandFpMlx,
|
|
.Fp16,
|
|
.RetAddrStack,
|
|
.VmlxHazards,
|
|
.Mp,
|
|
.MuxedUnits,
|
|
.NeonFpmovs,
|
|
.PreferVmovsr,
|
|
.Trustzone,
|
|
.VmlxForwarding,
|
|
.A9,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.CortexM0, "cortex-m0", &[_]FeatureType {
|
|
.V4t,
|
|
.ThumbMode,
|
|
.Db,
|
|
.StrictAlign,
|
|
.Mclass,
|
|
.Noarm,
|
|
.Armv6M,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.CortexM0plus, "cortex-m0plus", &[_]FeatureType {
|
|
.V4t,
|
|
.ThumbMode,
|
|
.Db,
|
|
.StrictAlign,
|
|
.Mclass,
|
|
.Noarm,
|
|
.Armv6M,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.CortexM1, "cortex-m1", &[_]FeatureType {
|
|
.V4t,
|
|
.ThumbMode,
|
|
.Db,
|
|
.StrictAlign,
|
|
.Mclass,
|
|
.Noarm,
|
|
.Armv6M,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.CortexM23, "cortex-m23", &[_]FeatureType {
|
|
.V4t,
|
|
.ThumbMode,
|
|
.Msecext8,
|
|
.V7clrex,
|
|
.Db,
|
|
.StrictAlign,
|
|
.Mclass,
|
|
.Noarm,
|
|
.AcquireRelease,
|
|
.Hwdiv,
|
|
.Armv8Mbase,
|
|
.NoMovt,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.CortexM3, "cortex-m3", &[_]FeatureType {
|
|
.Perfmon,
|
|
.V4t,
|
|
.ThumbMode,
|
|
.V7clrex,
|
|
.Thumb2,
|
|
.Db,
|
|
.Mclass,
|
|
.Noarm,
|
|
.Hwdiv,
|
|
.Armv7M,
|
|
.NoBranchPredictor,
|
|
.LoopAlign,
|
|
.UseAa,
|
|
.UseMisched,
|
|
.M3,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.CortexM33, "cortex-m33", &[_]FeatureType {
|
|
.Perfmon,
|
|
.V4t,
|
|
.ThumbMode,
|
|
.Msecext8,
|
|
.V7clrex,
|
|
.Thumb2,
|
|
.Db,
|
|
.Mclass,
|
|
.Noarm,
|
|
.AcquireRelease,
|
|
.Hwdiv,
|
|
.Armv8Mmain,
|
|
.Dsp,
|
|
.Fpregs,
|
|
.Fp16,
|
|
.FpArmv8d16sp,
|
|
.NoBranchPredictor,
|
|
.Slowfpvmlx,
|
|
.LoopAlign,
|
|
.UseAa,
|
|
.UseMisched,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.CortexM35p, "cortex-m35p", &[_]FeatureType {
|
|
.Perfmon,
|
|
.V4t,
|
|
.ThumbMode,
|
|
.Msecext8,
|
|
.V7clrex,
|
|
.Thumb2,
|
|
.Db,
|
|
.Mclass,
|
|
.Noarm,
|
|
.AcquireRelease,
|
|
.Hwdiv,
|
|
.Armv8Mmain,
|
|
.Dsp,
|
|
.Fpregs,
|
|
.Fp16,
|
|
.FpArmv8d16sp,
|
|
.NoBranchPredictor,
|
|
.Slowfpvmlx,
|
|
.LoopAlign,
|
|
.UseAa,
|
|
.UseMisched,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.CortexM4, "cortex-m4", &[_]FeatureType {
|
|
.Perfmon,
|
|
.V4t,
|
|
.ThumbMode,
|
|
.V7clrex,
|
|
.Dsp,
|
|
.Thumb2,
|
|
.Db,
|
|
.Mclass,
|
|
.Noarm,
|
|
.Hwdiv,
|
|
.Armv7eM,
|
|
.NoBranchPredictor,
|
|
.Slowfpvmlx,
|
|
.LoopAlign,
|
|
.UseAa,
|
|
.UseMisched,
|
|
.Fpregs,
|
|
.Fp16,
|
|
.Vfp4d16sp,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.CortexM7, "cortex-m7", &[_]FeatureType {
|
|
.Perfmon,
|
|
.V4t,
|
|
.ThumbMode,
|
|
.V7clrex,
|
|
.Dsp,
|
|
.Thumb2,
|
|
.Db,
|
|
.Mclass,
|
|
.Noarm,
|
|
.Hwdiv,
|
|
.Armv7eM,
|
|
.Fpregs,
|
|
.Fp16,
|
|
.FpArmv8d16,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.CortexR4, "cortex-r4", &[_]FeatureType {
|
|
.Perfmon,
|
|
.V4t,
|
|
.V7clrex,
|
|
.Dsp,
|
|
.Thumb2,
|
|
.Db,
|
|
.Hwdiv,
|
|
.Rclass,
|
|
.Armv7R,
|
|
.AvoidPartialCpsr,
|
|
.RetAddrStack,
|
|
.R4,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.CortexR4f, "cortex-r4f", &[_]FeatureType {
|
|
.Perfmon,
|
|
.V4t,
|
|
.V7clrex,
|
|
.Dsp,
|
|
.Thumb2,
|
|
.Db,
|
|
.Hwdiv,
|
|
.Rclass,
|
|
.Armv7R,
|
|
.AvoidPartialCpsr,
|
|
.RetAddrStack,
|
|
.Slowfpvmlx,
|
|
.SlowFpBrcc,
|
|
.Fpregs,
|
|
.Vfp3d16,
|
|
.R4,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.CortexR5, "cortex-r5", &[_]FeatureType {
|
|
.Perfmon,
|
|
.V4t,
|
|
.V7clrex,
|
|
.Dsp,
|
|
.Thumb2,
|
|
.Db,
|
|
.Hwdiv,
|
|
.Rclass,
|
|
.Armv7R,
|
|
.AvoidPartialCpsr,
|
|
.HwdivArm,
|
|
.RetAddrStack,
|
|
.Slowfpvmlx,
|
|
.SlowFpBrcc,
|
|
.Fpregs,
|
|
.Vfp3d16,
|
|
.R5,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.CortexR52, "cortex-r52", &[_]FeatureType {
|
|
.HwdivArm,
|
|
.Perfmon,
|
|
.D32,
|
|
.Crc,
|
|
.Fpregs,
|
|
.Mp,
|
|
.Dfb,
|
|
.Dsp,
|
|
.Fp16,
|
|
.V4t,
|
|
.Db,
|
|
.V7clrex,
|
|
.Thumb2,
|
|
.AcquireRelease,
|
|
.Hwdiv,
|
|
.Rclass,
|
|
.Armv8R,
|
|
.Fpao,
|
|
.UseAa,
|
|
.UseMisched,
|
|
.R52,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.CortexR7, "cortex-r7", &[_]FeatureType {
|
|
.Perfmon,
|
|
.V4t,
|
|
.V7clrex,
|
|
.Dsp,
|
|
.Thumb2,
|
|
.Db,
|
|
.Hwdiv,
|
|
.Rclass,
|
|
.Armv7R,
|
|
.AvoidPartialCpsr,
|
|
.Fp16,
|
|
.HwdivArm,
|
|
.RetAddrStack,
|
|
.Slowfpvmlx,
|
|
.Mp,
|
|
.SlowFpBrcc,
|
|
.Fpregs,
|
|
.Vfp3d16,
|
|
.R7,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.CortexR8, "cortex-r8", &[_]FeatureType {
|
|
.Perfmon,
|
|
.V4t,
|
|
.V7clrex,
|
|
.Dsp,
|
|
.Thumb2,
|
|
.Db,
|
|
.Hwdiv,
|
|
.Rclass,
|
|
.Armv7R,
|
|
.AvoidPartialCpsr,
|
|
.Fp16,
|
|
.HwdivArm,
|
|
.RetAddrStack,
|
|
.Slowfpvmlx,
|
|
.Mp,
|
|
.SlowFpBrcc,
|
|
.Fpregs,
|
|
.Vfp3d16,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.Cyclone, "cyclone", &[_]FeatureType {
|
|
.HwdivArm,
|
|
.Perfmon,
|
|
.D32,
|
|
.Fpregs,
|
|
.Crc,
|
|
.Mp,
|
|
.Fp16,
|
|
.Dsp,
|
|
.V4t,
|
|
.V7clrex,
|
|
.Db,
|
|
.Aclass,
|
|
.Thumb2,
|
|
.AcquireRelease,
|
|
.Hwdiv,
|
|
.Trustzone,
|
|
.Armv8A,
|
|
.AvoidMovsShop,
|
|
.AvoidPartialCpsr,
|
|
.Crypto,
|
|
.RetAddrStack,
|
|
.Slowfpvmlx,
|
|
.Neonfp,
|
|
.DisablePostraScheduler,
|
|
.UseMisched,
|
|
.Vfp4,
|
|
.Zcz,
|
|
.Swift,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.Ep9312, "ep9312", &[_]FeatureType {
|
|
.V4t,
|
|
.Armv4t,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.ExynosM1, "exynos-m1", &[_]FeatureType {
|
|
.HwdivArm,
|
|
.Perfmon,
|
|
.D32,
|
|
.Fpregs,
|
|
.Crc,
|
|
.Mp,
|
|
.Fp16,
|
|
.Dsp,
|
|
.V4t,
|
|
.V7clrex,
|
|
.Db,
|
|
.Aclass,
|
|
.Thumb2,
|
|
.AcquireRelease,
|
|
.Hwdiv,
|
|
.Trustzone,
|
|
.Armv8A,
|
|
.RetAddrStack,
|
|
.SlowVgetlni32,
|
|
.WideStrideVfp,
|
|
.SlowVdup32,
|
|
.SlowFpBrcc,
|
|
.ProfUnpr,
|
|
.DontWidenVmovs,
|
|
.Zcz,
|
|
.FuseAes,
|
|
.Slowfpvmlx,
|
|
.UseAa,
|
|
.FuseLiterals,
|
|
.ExpandFpMlx,
|
|
.Exynos,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.ExynosM2, "exynos-m2", &[_]FeatureType {
|
|
.HwdivArm,
|
|
.Perfmon,
|
|
.D32,
|
|
.Fpregs,
|
|
.Crc,
|
|
.Mp,
|
|
.Fp16,
|
|
.Dsp,
|
|
.V4t,
|
|
.V7clrex,
|
|
.Db,
|
|
.Aclass,
|
|
.Thumb2,
|
|
.AcquireRelease,
|
|
.Hwdiv,
|
|
.Trustzone,
|
|
.Armv8A,
|
|
.RetAddrStack,
|
|
.SlowVgetlni32,
|
|
.WideStrideVfp,
|
|
.SlowVdup32,
|
|
.SlowFpBrcc,
|
|
.ProfUnpr,
|
|
.DontWidenVmovs,
|
|
.Zcz,
|
|
.FuseAes,
|
|
.Slowfpvmlx,
|
|
.UseAa,
|
|
.FuseLiterals,
|
|
.ExpandFpMlx,
|
|
.Exynos,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.ExynosM3, "exynos-m3", &[_]FeatureType {
|
|
.HwdivArm,
|
|
.Perfmon,
|
|
.D32,
|
|
.Fpregs,
|
|
.Crc,
|
|
.Mp,
|
|
.Fp16,
|
|
.Dsp,
|
|
.V4t,
|
|
.V7clrex,
|
|
.Db,
|
|
.Aclass,
|
|
.Thumb2,
|
|
.AcquireRelease,
|
|
.Hwdiv,
|
|
.Trustzone,
|
|
.Armv8A,
|
|
.RetAddrStack,
|
|
.SlowVgetlni32,
|
|
.WideStrideVfp,
|
|
.SlowVdup32,
|
|
.SlowFpBrcc,
|
|
.ProfUnpr,
|
|
.DontWidenVmovs,
|
|
.Zcz,
|
|
.FuseAes,
|
|
.Slowfpvmlx,
|
|
.UseAa,
|
|
.FuseLiterals,
|
|
.ExpandFpMlx,
|
|
.Exynos,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.ExynosM4, "exynos-m4", &[_]FeatureType {
|
|
.HwdivArm,
|
|
.Perfmon,
|
|
.D32,
|
|
.Fpregs,
|
|
.Crc,
|
|
.Mp,
|
|
.Fp16,
|
|
.Dsp,
|
|
.V4t,
|
|
.V7clrex,
|
|
.Db,
|
|
.Aclass,
|
|
.Thumb2,
|
|
.Ras,
|
|
.AcquireRelease,
|
|
.Hwdiv,
|
|
.Trustzone,
|
|
.Armv82A,
|
|
.Dotprod,
|
|
.Fullfp16,
|
|
.RetAddrStack,
|
|
.SlowVgetlni32,
|
|
.WideStrideVfp,
|
|
.SlowVdup32,
|
|
.SlowFpBrcc,
|
|
.ProfUnpr,
|
|
.DontWidenVmovs,
|
|
.Zcz,
|
|
.FuseAes,
|
|
.Slowfpvmlx,
|
|
.UseAa,
|
|
.FuseLiterals,
|
|
.ExpandFpMlx,
|
|
.Exynos,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.ExynosM5, "exynos-m5", &[_]FeatureType {
|
|
.HwdivArm,
|
|
.Perfmon,
|
|
.D32,
|
|
.Fpregs,
|
|
.Crc,
|
|
.Mp,
|
|
.Fp16,
|
|
.Dsp,
|
|
.V4t,
|
|
.V7clrex,
|
|
.Db,
|
|
.Aclass,
|
|
.Thumb2,
|
|
.Ras,
|
|
.AcquireRelease,
|
|
.Hwdiv,
|
|
.Trustzone,
|
|
.Armv82A,
|
|
.Dotprod,
|
|
.Fullfp16,
|
|
.RetAddrStack,
|
|
.SlowVgetlni32,
|
|
.WideStrideVfp,
|
|
.SlowVdup32,
|
|
.SlowFpBrcc,
|
|
.ProfUnpr,
|
|
.DontWidenVmovs,
|
|
.Zcz,
|
|
.FuseAes,
|
|
.Slowfpvmlx,
|
|
.UseAa,
|
|
.FuseLiterals,
|
|
.ExpandFpMlx,
|
|
.Exynos,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.Iwmmxt, "iwmmxt", &[_]FeatureType {
|
|
.V4t,
|
|
.Armv5te,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.Krait, "krait", &[_]FeatureType {
|
|
.Perfmon,
|
|
.V4t,
|
|
.D32,
|
|
.Fpregs,
|
|
.V7clrex,
|
|
.Dsp,
|
|
.Thumb2,
|
|
.Db,
|
|
.Aclass,
|
|
.Armv7A,
|
|
.AvoidPartialCpsr,
|
|
.VldnAlign,
|
|
.Fp16,
|
|
.HwdivArm,
|
|
.Hwdiv,
|
|
.RetAddrStack,
|
|
.MuxedUnits,
|
|
.Vfp4,
|
|
.VmlxForwarding,
|
|
.Krait,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.Kryo, "kryo", &[_]FeatureType {
|
|
.HwdivArm,
|
|
.Perfmon,
|
|
.D32,
|
|
.Fpregs,
|
|
.Crc,
|
|
.Mp,
|
|
.Fp16,
|
|
.Dsp,
|
|
.V4t,
|
|
.V7clrex,
|
|
.Db,
|
|
.Aclass,
|
|
.Thumb2,
|
|
.AcquireRelease,
|
|
.Hwdiv,
|
|
.Trustzone,
|
|
.Armv8A,
|
|
.Crypto,
|
|
.Kryo,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.Mpcore, "mpcore", &[_]FeatureType {
|
|
.V4t,
|
|
.Armv6k,
|
|
.Slowfpvmlx,
|
|
.Fpregs,
|
|
.Vfp2,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.Mpcorenovfp, "mpcorenovfp", &[_]FeatureType {
|
|
.V4t,
|
|
.Armv6k,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.NeoverseN1, "neoverse-n1", &[_]FeatureType {
|
|
.HwdivArm,
|
|
.Perfmon,
|
|
.D32,
|
|
.Fpregs,
|
|
.Crc,
|
|
.Mp,
|
|
.Fp16,
|
|
.Dsp,
|
|
.V4t,
|
|
.V7clrex,
|
|
.Db,
|
|
.Aclass,
|
|
.Thumb2,
|
|
.Ras,
|
|
.AcquireRelease,
|
|
.Hwdiv,
|
|
.Trustzone,
|
|
.Armv82A,
|
|
.Crypto,
|
|
.Dotprod,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.Sc000, "sc000", &[_]FeatureType {
|
|
.V4t,
|
|
.ThumbMode,
|
|
.Db,
|
|
.StrictAlign,
|
|
.Mclass,
|
|
.Noarm,
|
|
.Armv6M,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.Sc300, "sc300", &[_]FeatureType {
|
|
.Perfmon,
|
|
.V4t,
|
|
.ThumbMode,
|
|
.V7clrex,
|
|
.Thumb2,
|
|
.Db,
|
|
.Mclass,
|
|
.Noarm,
|
|
.Hwdiv,
|
|
.Armv7M,
|
|
.NoBranchPredictor,
|
|
.UseAa,
|
|
.UseMisched,
|
|
.M3,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.Strongarm, "strongarm", &[_]FeatureType {
|
|
.Armv4,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.Strongarm110, "strongarm110", &[_]FeatureType {
|
|
.Armv4,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.Strongarm1100, "strongarm1100", &[_]FeatureType {
|
|
.Armv4,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.Strongarm1110, "strongarm1110", &[_]FeatureType {
|
|
.Armv4,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.Swift, "swift", &[_]FeatureType {
|
|
.Perfmon,
|
|
.V4t,
|
|
.D32,
|
|
.Fpregs,
|
|
.V7clrex,
|
|
.Dsp,
|
|
.Thumb2,
|
|
.Db,
|
|
.Aclass,
|
|
.Armv7A,
|
|
.AvoidMovsShop,
|
|
.AvoidPartialCpsr,
|
|
.HwdivArm,
|
|
.Hwdiv,
|
|
.RetAddrStack,
|
|
.Slowfpvmlx,
|
|
.VmlxHazards,
|
|
.Mp,
|
|
.Neonfp,
|
|
.DisablePostraScheduler,
|
|
.PreferIshst,
|
|
.ProfUnpr,
|
|
.SlowLoadDSubreg,
|
|
.SlowOddReg,
|
|
.SlowVdup32,
|
|
.SlowVgetlni32,
|
|
.UseMisched,
|
|
.WideStrideVfp,
|
|
.Fp16,
|
|
.Vfp4,
|
|
.Swift,
|
|
}),
|
|
CpuInfo(@This(), FeatureType).create(.Xscale, "xscale", &[_]FeatureType {
|
|
.V4t,
|
|
.Armv5te,
|
|
}),
|
|
};
|
|
};
|