746 lines
23 KiB
Zig
746 lines
23 KiB
Zig
const std = @import("std");
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const DW = std.dwarf;
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const assert = std.debug.assert;
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const testing = std.testing;
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// zig fmt: off
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/// General purpose registers in the AArch64 instruction set
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pub const Register = enum(u6) {
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// 64-bit registers
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x0, x1, x2, x3, x4, x5, x6, x7,
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x8, x9, x10, x11, x12, x13, x14, x15,
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x16, x17, x18, x19, x20, x21, x22, x23,
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x24, x25, x26, x27, x28, x29, x30, xzr,
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// 32-bit registers
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w0, w1, w2, w3, w4, w5, w6, w7,
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w8, w9, w10, w11, w12, w13, w14, w15,
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w16, w17, w18, w19, w20, w21, w22, w23,
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w24, w25, w26, w27, w28, w29, w30, wzr,
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pub fn id(self: Register) u5 {
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return @truncate(u5, @enumToInt(self));
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}
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/// Returns the bit-width of the register.
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pub fn size(self: Register) u7 {
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return switch (@enumToInt(self)) {
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0...31 => 64,
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32...63 => 32,
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};
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}
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/// Convert from any register to its 64 bit alias.
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pub fn to64(self: Register) Register {
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return @intToEnum(Register, self.id());
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}
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/// Convert from any register to its 32 bit alias.
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pub fn to32(self: Register) Register {
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return @intToEnum(Register, @as(u6, self.id()) + 32);
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}
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/// Returns the index into `callee_preserved_regs`.
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pub fn allocIndex(self: Register) ?u4 {
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inline for (callee_preserved_regs) |cpreg, i| {
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if (self.id() == cpreg.id()) return i;
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}
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return null;
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}
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pub fn dwarfLocOp(self: Register) u8 {
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return @as(u8, self.id()) + DW.OP_reg0;
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}
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};
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// zig fmt: on
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pub const callee_preserved_regs = [_]Register{
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.x19, .x20, .x21, .x22, .x23,
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.x24, .x25, .x26, .x27, .x28,
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};
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pub const c_abi_int_param_regs = [_]Register{ .x0, .x1, .x2, .x3, .x4, .x5, .x6, .x7 };
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pub const c_abi_int_return_regs = [_]Register{ .x0, .x1 };
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test "Register.id" {
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testing.expectEqual(@as(u5, 0), Register.x0.id());
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testing.expectEqual(@as(u5, 0), Register.w0.id());
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testing.expectEqual(@as(u5, 31), Register.xzr.id());
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testing.expectEqual(@as(u5, 31), Register.wzr.id());
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}
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test "Register.size" {
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testing.expectEqual(@as(u7, 64), Register.x19.size());
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testing.expectEqual(@as(u7, 32), Register.w3.size());
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}
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test "Register.to64/to32" {
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testing.expectEqual(Register.x0, Register.w0.to64());
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testing.expectEqual(Register.x0, Register.x0.to64());
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testing.expectEqual(Register.w3, Register.w3.to32());
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testing.expectEqual(Register.w3, Register.x3.to32());
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}
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// zig fmt: off
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/// Scalar floating point registers in the aarch64 instruction set
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pub const FloatingPointRegister = enum(u8) {
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// 128-bit registers
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q0, q1, q2, q3, q4, q5, q6, q7,
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q8, q9, q10, q11, q12, q13, q14, q15,
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q16, q17, q18, q19, q20, q21, q22, q23,
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q24, q25, q26, q27, q28, q29, q30, q31,
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// 64-bit registers
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d0, d1, d2, d3, d4, d5, d6, d7,
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d8, d9, d10, d11, d12, d13, d14, d15,
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d16, d17, d18, d19, d20, d21, d22, d23,
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d24, d25, d26, d27, d28, d29, d30, d31,
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// 32-bit registers
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s0, s1, s2, s3, s4, s5, s6, s7,
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s8, s9, s10, s11, s12, s13, s14, s15,
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s16, s17, s18, s19, s20, s21, s22, s23,
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s24, s25, s26, s27, s28, s29, s30, s31,
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// 16-bit registers
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h0, h1, h2, h3, h4, h5, h6, h7,
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h8, h9, h10, h11, h12, h13, h14, h15,
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h16, h17, h18, h19, h20, h21, h22, h23,
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h24, h25, h26, h27, h28, h29, h30, h31,
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// 8-bit registers
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b0, b1, b2, b3, b4, b5, b6, b7,
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b8, b9, b10, b11, b12, b13, b14, b15,
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b16, b17, b18, b19, b20, b21, b22, b23,
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b24, b25, b26, b27, b28, b29, b30, b31,
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pub fn id(self: FloatingPointRegister) u5 {
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return @truncate(u5, @enumToInt(self));
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}
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/// Returns the bit-width of the register.
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pub fn size(self: FloatingPointRegister) u8 {
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return switch (@enumToInt(self)) {
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0...31 => 128,
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32...63 => 64,
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64...95 => 32,
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96...127 => 16,
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128...159 => 8,
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else => unreachable,
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};
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}
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/// Convert from any register to its 128 bit alias.
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pub fn to128(self: FloatingPointRegister) FloatingPointRegister {
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return @intToEnum(FloatingPointRegister, self.id());
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}
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/// Convert from any register to its 64 bit alias.
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pub fn to64(self: FloatingPointRegister) FloatingPointRegister {
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return @intToEnum(FloatingPointRegister, @as(u8, self.id()) + 32);
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}
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/// Convert from any register to its 32 bit alias.
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pub fn to32(self: FloatingPointRegister) FloatingPointRegister {
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return @intToEnum(FloatingPointRegister, @as(u8, self.id()) + 64);
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}
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/// Convert from any register to its 16 bit alias.
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pub fn to16(self: FloatingPointRegister) FloatingPointRegister {
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return @intToEnum(FloatingPointRegister, @as(u8, self.id()) + 96);
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}
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/// Convert from any register to its 8 bit alias.
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pub fn to8(self: FloatingPointRegister) FloatingPointRegister {
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return @intToEnum(FloatingPointRegister, @as(u8, self.id()) + 128);
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}
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};
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// zig fmt: on
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test "FloatingPointRegister.id" {
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testing.expectEqual(@as(u5, 0), FloatingPointRegister.b0.id());
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testing.expectEqual(@as(u5, 0), FloatingPointRegister.h0.id());
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testing.expectEqual(@as(u5, 0), FloatingPointRegister.s0.id());
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testing.expectEqual(@as(u5, 0), FloatingPointRegister.d0.id());
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testing.expectEqual(@as(u5, 0), FloatingPointRegister.q0.id());
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testing.expectEqual(@as(u5, 2), FloatingPointRegister.q2.id());
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testing.expectEqual(@as(u5, 31), FloatingPointRegister.d31.id());
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}
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test "FloatingPointRegister.size" {
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testing.expectEqual(@as(u8, 128), FloatingPointRegister.q1.size());
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testing.expectEqual(@as(u8, 64), FloatingPointRegister.d2.size());
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testing.expectEqual(@as(u8, 32), FloatingPointRegister.s3.size());
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testing.expectEqual(@as(u8, 16), FloatingPointRegister.h4.size());
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testing.expectEqual(@as(u8, 8), FloatingPointRegister.b5.size());
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}
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test "FloatingPointRegister.toX" {
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testing.expectEqual(FloatingPointRegister.q1, FloatingPointRegister.q1.to128());
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testing.expectEqual(FloatingPointRegister.q2, FloatingPointRegister.b2.to128());
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testing.expectEqual(FloatingPointRegister.q3, FloatingPointRegister.h3.to128());
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testing.expectEqual(FloatingPointRegister.d0, FloatingPointRegister.q0.to64());
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testing.expectEqual(FloatingPointRegister.s1, FloatingPointRegister.d1.to32());
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testing.expectEqual(FloatingPointRegister.h2, FloatingPointRegister.s2.to16());
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testing.expectEqual(FloatingPointRegister.b3, FloatingPointRegister.h3.to8());
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}
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/// Represents an instruction in the AArch64 instruction set
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pub const Instruction = union(enum) {
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MoveWideImmediate: packed struct {
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rd: u5,
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imm16: u16,
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hw: u2,
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fixed: u6 = 0b100101,
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opc: u2,
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sf: u1,
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},
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PCRelativeAddress: packed struct {
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rd: u5,
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immhi: u19,
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fixed: u5 = 0b10000,
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immlo: u2,
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op: u1,
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},
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LoadStoreRegister: packed struct {
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rt: u5,
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rn: u5,
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offset: u12,
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opc: u2,
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op1: u2,
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fixed: u4 = 0b111_0,
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size: u2,
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},
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LoadLiteral: packed struct {
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rt: u5,
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imm19: u19,
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fixed: u6 = 0b011_0_00,
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opc: u2,
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},
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ExceptionGeneration: packed struct {
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ll: u2,
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op2: u3,
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imm16: u16,
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opc: u3,
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fixed: u8 = 0b1101_0100,
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},
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UnconditionalBranchRegister: packed struct {
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op4: u5,
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rn: u5,
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op3: u6,
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op2: u5,
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opc: u4,
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fixed: u7 = 0b1101_011,
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},
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UnconditionalBranchImmediate: packed struct {
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imm26: u26,
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fixed: u5 = 0b00101,
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op: u1,
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},
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NoOperation: packed struct {
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fixed: u32 = 0b1101010100_0_00_011_0010_0000_000_11111,
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},
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pub fn toU32(self: Instruction) u32 {
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return switch (self) {
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.MoveWideImmediate => |v| @bitCast(u32, v),
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.PCRelativeAddress => |v| @bitCast(u32, v),
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.LoadStoreRegister => |v| @bitCast(u32, v),
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.LoadLiteral => |v| @bitCast(u32, v),
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.ExceptionGeneration => |v| @bitCast(u32, v),
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.UnconditionalBranchRegister => |v| @bitCast(u32, v),
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.UnconditionalBranchImmediate => |v| @bitCast(u32, v),
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.NoOperation => |v| @bitCast(u32, v),
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};
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}
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/// Represents the offset operand of a load or store instruction.
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/// Data can be loaded from memory with either an immediate offset
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/// or an offset that is stored in some register.
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pub const Offset = union(enum) {
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Immediate: union(enum) {
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PostIndex: i9,
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PreIndex: i9,
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Unsigned: u12,
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},
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Register: struct {
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rm: u5,
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shift: union(enum) {
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Uxtw: u2,
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Lsl: u2,
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Sxtw: u2,
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Sxtx: u2,
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},
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},
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pub const none = Offset{
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.Immediate = .{ .Unsigned = 0 },
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};
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pub fn toU12(self: Offset) u12 {
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return switch (self) {
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.Immediate => |imm_type| switch (imm_type) {
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.PostIndex => |v| (@intCast(u12, @bitCast(u9, v)) << 2) + 1,
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.PreIndex => |v| (@intCast(u12, @bitCast(u9, v)) << 2) + 3,
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.Unsigned => |v| v,
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},
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.Register => |r| switch (r.shift) {
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.Uxtw => |v| (@intCast(u12, r.rm) << 6) + (@intCast(u12, v) << 2) + 16 + 2050,
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.Lsl => |v| (@intCast(u12, r.rm) << 6) + (@intCast(u12, v) << 2) + 24 + 2050,
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.Sxtw => |v| (@intCast(u12, r.rm) << 6) + (@intCast(u12, v) << 2) + 48 + 2050,
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.Sxtx => |v| (@intCast(u12, r.rm) << 6) + (@intCast(u12, v) << 2) + 56 + 2050,
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},
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};
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}
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pub fn imm(offset: u12) Offset {
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return Offset{
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.Immediate = .{ .Unsigned = offset },
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};
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}
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pub fn imm_post_index(offset: i9) Offset {
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return Offset{
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.Immediate = .{ .PostIndex = offset },
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};
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}
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pub fn imm_pre_index(offset: i9) Offset {
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return Offset{
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.Immediate = .{ .PreIndex = offset },
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};
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}
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pub fn reg(rm: Register) Offset {
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return Offset{
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.Register = .{
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.rm = rm.id(),
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.shift = .{
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.Lsl = 0,
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},
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},
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};
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}
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pub fn reg_uxtw(rm: Register, shift: u2) Offset {
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assert(rm.size() == 32 and (shift == 0 or shift == 2));
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return Offset{
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.Register = .{
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.rm = rm.id(),
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.shift = .{
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.Uxtw = shift,
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},
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},
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};
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}
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pub fn reg_lsl(rm: Register, shift: u2) Offset {
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assert(rm.size() == 64 and (shift == 0 or shift == 3));
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return Offset{
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.Register = .{
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.rm = rm.id(),
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.shift = .{
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.Lsl = shift,
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},
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},
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};
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}
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pub fn reg_sxtw(rm: Register, shift: u2) Offset {
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assert(rm.size() == 32 and (shift == 0 or shift == 2));
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return Offset{
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.Register = .{
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.rm = rm.id(),
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.shift = .{
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.Sxtw = shift,
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},
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},
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};
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}
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pub fn reg_sxtx(rm: Register, shift: u2) Offset {
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assert(rm.size() == 64 and (shift == 0 or shift == 3));
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return Offset{
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.Register = .{
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.rm = rm.id(),
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.shift = .{
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.Sxtx = shift,
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},
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},
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};
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}
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};
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// Helper functions for assembly syntax functions
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fn moveWideImmediate(
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opc: u2,
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rd: Register,
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imm16: u16,
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shift: u6,
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) Instruction {
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switch (rd.size()) {
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32 => {
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assert(shift % 16 == 0 and shift <= 16);
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return Instruction{
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.MoveWideImmediate = .{
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.rd = rd.id(),
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.imm16 = imm16,
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.hw = @intCast(u2, shift / 16),
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.opc = opc,
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.sf = 0,
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},
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};
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},
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64 => {
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assert(shift % 16 == 0 and shift <= 48);
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return Instruction{
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.MoveWideImmediate = .{
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.rd = rd.id(),
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.imm16 = imm16,
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.hw = @intCast(u2, shift / 16),
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.opc = opc,
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.sf = 1,
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},
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};
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},
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else => unreachable, // unexpected register size
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}
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}
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fn pcRelativeAddress(rd: Register, imm21: i21, op: u1) Instruction {
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const imm21_u = @bitCast(u21, imm21);
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return Instruction{
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.PCRelativeAddress = .{
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.rd = rd.id(),
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.immlo = @truncate(u2, imm21_u),
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.immhi = @truncate(u19, imm21_u >> 2),
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.op = op,
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},
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};
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}
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fn loadStoreRegister(rt: Register, rn: Register, offset: Offset, load: bool) Instruction {
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const off = offset.toU12();
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const op1: u2 = blk: {
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switch (offset) {
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.Immediate => |imm| switch (imm) {
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.Unsigned => break :blk 0b01,
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else => {},
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},
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else => {},
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}
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break :blk 0b00;
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};
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const opc: u2 = if (load) 0b01 else 0b00;
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switch (rt.size()) {
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32 => {
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return Instruction{
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.LoadStoreRegister = .{
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.rt = rt.id(),
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.rn = rn.id(),
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.offset = offset.toU12(),
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.opc = opc,
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.op1 = op1,
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.size = 0b10,
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},
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};
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},
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64 => {
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return Instruction{
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.LoadStoreRegister = .{
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.rt = rt.id(),
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.rn = rn.id(),
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.offset = offset.toU12(),
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.opc = opc,
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.op1 = op1,
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.size = 0b11,
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},
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};
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},
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else => unreachable, // unexpected register size
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}
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}
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|
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fn loadLiteral(rt: Register, imm19: u19) Instruction {
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switch (rt.size()) {
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32 => {
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return Instruction{
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.LoadLiteral = .{
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.rt = rt.id(),
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.imm19 = imm19,
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.opc = 0b00,
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},
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};
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},
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64 => {
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return Instruction{
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.LoadLiteral = .{
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.rt = rt.id(),
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.imm19 = imm19,
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.opc = 0b01,
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},
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};
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},
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else => unreachable, // unexpected register size
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}
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}
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|
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fn exceptionGeneration(
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opc: u3,
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op2: u3,
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ll: u2,
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imm16: u16,
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) Instruction {
|
|
return Instruction{
|
|
.ExceptionGeneration = .{
|
|
.ll = ll,
|
|
.op2 = op2,
|
|
.imm16 = imm16,
|
|
.opc = opc,
|
|
},
|
|
};
|
|
}
|
|
|
|
fn unconditionalBranchRegister(
|
|
opc: u4,
|
|
op2: u5,
|
|
op3: u6,
|
|
rn: Register,
|
|
op4: u5,
|
|
) Instruction {
|
|
assert(rn.size() == 64);
|
|
|
|
return Instruction{
|
|
.UnconditionalBranchRegister = .{
|
|
.op4 = op4,
|
|
.rn = rn.id(),
|
|
.op3 = op3,
|
|
.op2 = op2,
|
|
.opc = opc,
|
|
},
|
|
};
|
|
}
|
|
|
|
fn unconditionalBranchImmediate(
|
|
op: u1,
|
|
offset: i28,
|
|
) Instruction {
|
|
return Instruction{
|
|
.UnconditionalBranchImmediate = .{
|
|
.imm26 = @bitCast(u26, @intCast(i26, offset >> 2)),
|
|
.op = op,
|
|
},
|
|
};
|
|
}
|
|
|
|
// Move wide (immediate)
|
|
|
|
pub fn movn(rd: Register, imm16: u16, shift: u6) Instruction {
|
|
return moveWideImmediate(0b00, rd, imm16, shift);
|
|
}
|
|
|
|
pub fn movz(rd: Register, imm16: u16, shift: u6) Instruction {
|
|
return moveWideImmediate(0b10, rd, imm16, shift);
|
|
}
|
|
|
|
pub fn movk(rd: Register, imm16: u16, shift: u6) Instruction {
|
|
return moveWideImmediate(0b11, rd, imm16, shift);
|
|
}
|
|
|
|
// PC relative address
|
|
|
|
pub fn adr(rd: Register, imm21: i21) Instruction {
|
|
return pcRelativeAddress(rd, imm21, 0b0);
|
|
}
|
|
|
|
pub fn adrp(rd: Register, imm21: i21) Instruction {
|
|
return pcRelativeAddress(rd, imm21, 0b1);
|
|
}
|
|
|
|
// Load or store register
|
|
|
|
pub const LdrArgs = struct {
|
|
rn: ?Register = null,
|
|
offset: Offset = Offset.none,
|
|
literal: ?u19 = null,
|
|
};
|
|
pub fn ldr(rt: Register, args: LdrArgs) Instruction {
|
|
if (args.rn) |rn| {
|
|
return loadStoreRegister(rt, rn, args.offset, true);
|
|
} else {
|
|
return loadLiteral(rt, args.literal.?);
|
|
}
|
|
}
|
|
|
|
pub const StrArgs = struct {
|
|
offset: Offset = Offset.none,
|
|
};
|
|
pub fn str(rt: Register, rn: Register, args: StrArgs) Instruction {
|
|
return loadStoreRegister(rt, rn, args.offset, false);
|
|
}
|
|
|
|
// Exception generation
|
|
|
|
pub fn svc(imm16: u16) Instruction {
|
|
return exceptionGeneration(0b000, 0b000, 0b01, imm16);
|
|
}
|
|
|
|
pub fn hvc(imm16: u16) Instruction {
|
|
return exceptionGeneration(0b000, 0b000, 0b10, imm16);
|
|
}
|
|
|
|
pub fn smc(imm16: u16) Instruction {
|
|
return exceptionGeneration(0b000, 0b000, 0b11, imm16);
|
|
}
|
|
|
|
pub fn brk(imm16: u16) Instruction {
|
|
return exceptionGeneration(0b001, 0b000, 0b00, imm16);
|
|
}
|
|
|
|
pub fn hlt(imm16: u16) Instruction {
|
|
return exceptionGeneration(0b010, 0b000, 0b00, imm16);
|
|
}
|
|
|
|
// Unconditional branch (register)
|
|
|
|
pub fn br(rn: Register) Instruction {
|
|
return unconditionalBranchRegister(0b0000, 0b11111, 0b000000, rn, 0b00000);
|
|
}
|
|
|
|
pub fn blr(rn: Register) Instruction {
|
|
return unconditionalBranchRegister(0b0001, 0b11111, 0b000000, rn, 0b00000);
|
|
}
|
|
|
|
pub fn ret(rn: ?Register) Instruction {
|
|
return unconditionalBranchRegister(0b0010, 0b11111, 0b000000, rn orelse .x30, 0b00000);
|
|
}
|
|
|
|
// Unconditional branch (immediate)
|
|
|
|
pub fn b(offset: i28) Instruction {
|
|
return unconditionalBranchImmediate(0, offset);
|
|
}
|
|
|
|
pub fn bl(offset: i28) Instruction {
|
|
return unconditionalBranchImmediate(1, offset);
|
|
}
|
|
|
|
// Nop
|
|
|
|
pub fn nop() Instruction {
|
|
return Instruction{ .NoOperation = {} };
|
|
}
|
|
};
|
|
|
|
test "" {
|
|
testing.refAllDecls(@This());
|
|
}
|
|
|
|
test "serialize instructions" {
|
|
const Testcase = struct {
|
|
inst: Instruction,
|
|
expected: u32,
|
|
};
|
|
|
|
const testcases = [_]Testcase{
|
|
.{ // movz x1 #4
|
|
.inst = Instruction.movz(.x1, 4, 0),
|
|
.expected = 0b1_10_100101_00_0000000000000100_00001,
|
|
},
|
|
.{ // movz x1, #4, lsl 16
|
|
.inst = Instruction.movz(.x1, 4, 16),
|
|
.expected = 0b1_10_100101_01_0000000000000100_00001,
|
|
},
|
|
.{ // movz x1, #4, lsl 32
|
|
.inst = Instruction.movz(.x1, 4, 32),
|
|
.expected = 0b1_10_100101_10_0000000000000100_00001,
|
|
},
|
|
.{ // movz x1, #4, lsl 48
|
|
.inst = Instruction.movz(.x1, 4, 48),
|
|
.expected = 0b1_10_100101_11_0000000000000100_00001,
|
|
},
|
|
.{ // movz w1, #4
|
|
.inst = Instruction.movz(.w1, 4, 0),
|
|
.expected = 0b0_10_100101_00_0000000000000100_00001,
|
|
},
|
|
.{ // movz w1, #4, lsl 16
|
|
.inst = Instruction.movz(.w1, 4, 16),
|
|
.expected = 0b0_10_100101_01_0000000000000100_00001,
|
|
},
|
|
.{ // svc #0
|
|
.inst = Instruction.svc(0),
|
|
.expected = 0b1101_0100_000_0000000000000000_00001,
|
|
},
|
|
.{ // svc #0x80 ; typical on Darwin
|
|
.inst = Instruction.svc(0x80),
|
|
.expected = 0b1101_0100_000_0000000010000000_00001,
|
|
},
|
|
.{ // ret
|
|
.inst = Instruction.ret(null),
|
|
.expected = 0b1101_011_00_10_11111_0000_00_11110_00000,
|
|
},
|
|
.{ // bl #0x10
|
|
.inst = Instruction.bl(0x10),
|
|
.expected = 0b1_00101_00_0000_0000_0000_0000_0000_0100,
|
|
},
|
|
.{ // ldr x2, [x1]
|
|
.inst = Instruction.ldr(.x2, .{ .rn = .x1 }),
|
|
.expected = 0b11_111_0_01_01_000000000000_00001_00010,
|
|
},
|
|
.{ // ldr x2, [x1, #1]!
|
|
.inst = Instruction.ldr(.x2, .{ .rn = .x1, .offset = Instruction.Offset.imm_pre_index(1) }),
|
|
.expected = 0b11_111_0_00_01_0_000000001_11_00001_00010,
|
|
},
|
|
.{ // ldr x2, [x1], #-1
|
|
.inst = Instruction.ldr(.x2, .{ .rn = .x1, .offset = Instruction.Offset.imm_post_index(-1) }),
|
|
.expected = 0b11_111_0_00_01_0_111111111_01_00001_00010,
|
|
},
|
|
.{ // ldr x2, [x1], (x3)
|
|
.inst = Instruction.ldr(.x2, .{ .rn = .x1, .offset = Instruction.Offset.reg(.x3) }),
|
|
.expected = 0b11_111_0_00_01_1_00011_011_0_10_00001_00010,
|
|
},
|
|
.{ // ldr x2, label
|
|
.inst = Instruction.ldr(.x2, .{ .literal = 0x1 }),
|
|
.expected = 0b01_011_0_00_0000000000000000001_00010,
|
|
},
|
|
.{ // str x2, [x1]
|
|
.inst = Instruction.str(.x2, .x1, .{}),
|
|
.expected = 0b11_111_0_01_00_000000000000_00001_00010,
|
|
},
|
|
.{ // str x2, [x1], (x3)
|
|
.inst = Instruction.str(.x2, .x1, .{ .offset = Instruction.Offset.reg(.x3) }),
|
|
.expected = 0b11_111_0_00_00_1_00011_011_0_10_00001_00010,
|
|
},
|
|
.{ // adr x2, #0x8
|
|
.inst = Instruction.adr(.x2, 0x8),
|
|
.expected = 0b0_00_10000_0000000000000000010_00010,
|
|
},
|
|
.{ // adr x2, -#0x8
|
|
.inst = Instruction.adr(.x2, -0x8),
|
|
.expected = 0b0_00_10000_1111111111111111110_00010,
|
|
},
|
|
.{ // adrp x2, #0x8
|
|
.inst = Instruction.adrp(.x2, 0x8),
|
|
.expected = 0b1_00_10000_0000000000000000010_00010,
|
|
},
|
|
.{ // adrp x2, -#0x8
|
|
.inst = Instruction.adrp(.x2, -0x8),
|
|
.expected = 0b1_00_10000_1111111111111111110_00010,
|
|
},
|
|
};
|
|
|
|
for (testcases) |case| {
|
|
const actual = case.inst.toU32();
|
|
testing.expectEqual(case.expected, actual);
|
|
}
|
|
}
|