247 lines
7.7 KiB
Zig
247 lines
7.7 KiB
Zig
const std = @import("std");
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const DW = std.dwarf;
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const testing = std.testing;
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// zig fmt: off
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/// General purpose registers in the AArch64 instruction set
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pub const Register = enum(u6) {
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// 64-bit registers
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x0, x1, x2, x3, x4, x5, x6, x7,
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x8, x9, x10, x11, x12, x13, x14, x15,
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x16, x17, x18, x19, x20, x21, x22, x23,
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x24, x25, x26, x27, x28, x29, x30, xzr,
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// 32-bit registers
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w0, w1, w2, w3, w4, w5, w6, w7,
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w8, w9, w10, w11, w12, w13, w14, w15,
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w16, w17, w18, w19, w20, w21, w22, w23,
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w24, w25, w26, w27, w28, w29, w30, wzr,
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pub fn id(self: Register) u5 {
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return @truncate(u5, @enumToInt(self));
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}
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/// Returns the bit-width of the register.
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pub fn size(self: Register) u7 {
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return switch (@enumToInt(self)) {
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0...31 => 64,
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32...63 => 32,
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};
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}
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/// Convert from any register to its 64 bit alias.
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pub fn to64(self: Register) Register {
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return @intToEnum(Register, self.id());
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}
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/// Convert from any register to its 32 bit alias.
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pub fn to32(self: Register) Register {
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return @intToEnum(Register, @as(u6, self.id()) + 32);
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}
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/// Returns the index into `callee_preserved_regs`.
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pub fn allocIndex(self: Register) ?u4 {
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inline for (callee_preserved_regs) |cpreg, i| {
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if (self.id() == cpreg.id()) return i;
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}
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return null;
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}
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pub fn dwarfLocOp(self: Register) u8 {
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return @as(u8, self.id()) + DW.OP_reg0;
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}
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};
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// zig fmt: on
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pub const callee_preserved_regs = [_]Register{
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.x19, .x20, .x21, .x22, .x23,
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.x24, .x25, .x26, .x27, .x28,
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};
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pub const c_abi_int_param_regs = [_]Register{ .x0, .x1, .x2, .x3, .x4, .x5, .x6, .x7 };
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pub const c_abi_int_return_regs = [_]Register{ .x0, .x1 };
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test "Register.id" {
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testing.expectEqual(@as(u5, 0), Register.x0.id());
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testing.expectEqual(@as(u5, 0), Register.w0.id());
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testing.expectEqual(@as(u5, 31), Register.xzr.id());
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testing.expectEqual(@as(u5, 31), Register.wzr.id());
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}
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test "Register.size" {
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testing.expectEqual(@as(u7, 64), Register.x19.size());
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testing.expectEqual(@as(u7, 32), Register.w3.size());
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}
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test "Register.to64/to32" {
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testing.expectEqual(Register.x0, Register.w0.to64());
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testing.expectEqual(Register.x0, Register.x0.to64());
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testing.expectEqual(Register.w3, Register.w3.to32());
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testing.expectEqual(Register.w3, Register.x3.to32());
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}
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// zig fmt: off
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/// Scalar floating point registers in the aarch64 instruction set
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pub const FloatingPointRegister = enum(u8) {
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// 128-bit registers
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q0, q1, q2, q3, q4, q5, q6, q7,
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q8, q9, q10, q11, q12, q13, q14, q15,
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q16, q17, q18, q19, q20, q21, q22, q23,
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q24, q25, q26, q27, q28, q29, q30, q31,
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// 64-bit registers
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d0, d1, d2, d3, d4, d5, d6, d7,
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d8, d9, d10, d11, d12, d13, d14, d15,
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d16, d17, d18, d19, d20, d21, d22, d23,
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d24, d25, d26, d27, d28, d29, d30, d31,
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// 32-bit registers
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s0, s1, s2, s3, s4, s5, s6, s7,
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s8, s9, s10, s11, s12, s13, s14, s15,
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s16, s17, s18, s19, s20, s21, s22, s23,
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s24, s25, s26, s27, s28, s29, s30, s31,
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// 16-bit registers
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h0, h1, h2, h3, h4, h5, h6, h7,
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h8, h9, h10, h11, h12, h13, h14, h15,
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h16, h17, h18, h19, h20, h21, h22, h23,
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h24, h25, h26, h27, h28, h29, h30, h31,
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// 8-bit registers
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b0, b1, b2, b3, b4, b5, b6, b7,
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b8, b9, b10, b11, b12, b13, b14, b15,
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b16, b17, b18, b19, b20, b21, b22, b23,
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b24, b25, b26, b27, b28, b29, b30, b31,
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pub fn id(self: FloatingPointRegister) u5 {
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return @truncate(u5, @enumToInt(self));
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}
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/// Returns the bit-width of the register.
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pub fn size(self: FloatingPointRegister) u8 {
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return switch (@enumToInt(self)) {
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0...31 => 128,
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32...63 => 64,
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64...95 => 32,
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96...127 => 16,
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128...159 => 8,
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else => unreachable,
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};
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}
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/// Convert from any register to its 128 bit alias.
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pub fn to128(self: FloatingPointRegister) FloatingPointRegister {
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return @intToEnum(FloatingPointRegister, self.id());
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}
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/// Convert from any register to its 64 bit alias.
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pub fn to64(self: FloatingPointRegister) FloatingPointRegister {
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return @intToEnum(FloatingPointRegister, @as(u8, self.id()) + 32);
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}
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/// Convert from any register to its 32 bit alias.
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pub fn to32(self: FloatingPointRegister) FloatingPointRegister {
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return @intToEnum(FloatingPointRegister, @as(u8, self.id()) + 64);
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}
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/// Convert from any register to its 16 bit alias.
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pub fn to16(self: FloatingPointRegister) FloatingPointRegister {
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return @intToEnum(FloatingPointRegister, @as(u8, self.id()) + 96);
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}
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/// Convert from any register to its 8 bit alias.
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pub fn to8(self: FloatingPointRegister) FloatingPointRegister {
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return @intToEnum(FloatingPointRegister, @as(u8, self.id()) + 128);
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}
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};
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// zig fmt: on
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test "FloatingPointRegister.id" {
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testing.expectEqual(@as(u5, 0), FloatingPointRegister.b0.id());
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testing.expectEqual(@as(u5, 0), FloatingPointRegister.h0.id());
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testing.expectEqual(@as(u5, 0), FloatingPointRegister.s0.id());
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testing.expectEqual(@as(u5, 0), FloatingPointRegister.d0.id());
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testing.expectEqual(@as(u5, 0), FloatingPointRegister.q0.id());
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testing.expectEqual(@as(u5, 2), FloatingPointRegister.q2.id());
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testing.expectEqual(@as(u5, 31), FloatingPointRegister.d31.id());
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}
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test "FloatingPointRegister.size" {
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testing.expectEqual(@as(u8, 128), FloatingPointRegister.q1.size());
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testing.expectEqual(@as(u8, 64), FloatingPointRegister.d2.size());
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testing.expectEqual(@as(u8, 32), FloatingPointRegister.s3.size());
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testing.expectEqual(@as(u8, 16), FloatingPointRegister.h4.size());
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testing.expectEqual(@as(u8, 8), FloatingPointRegister.b5.size());
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}
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test "FloatingPointRegister.toX" {
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testing.expectEqual(FloatingPointRegister.q1, FloatingPointRegister.q1.to128());
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testing.expectEqual(FloatingPointRegister.q2, FloatingPointRegister.b2.to128());
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testing.expectEqual(FloatingPointRegister.q3, FloatingPointRegister.h3.to128());
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testing.expectEqual(FloatingPointRegister.d0, FloatingPointRegister.q0.to64());
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testing.expectEqual(FloatingPointRegister.s1, FloatingPointRegister.d1.to32());
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testing.expectEqual(FloatingPointRegister.h2, FloatingPointRegister.s2.to16());
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testing.expectEqual(FloatingPointRegister.b3, FloatingPointRegister.h3.to8());
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}
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/// Represents an instruction in the AArch64 instruction set
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pub const Instruction = union(enum) {
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SupervisorCall: packed struct {
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fixed_1: u5 = 0b00001,
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imm16: u16,
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fixed_2: u11 = 0b11010100000,
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},
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pub fn toU32(self: Instruction) u32 {
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return switch (self) {
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.SupervisorCall => |v| @bitCast(u32, v),
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};
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}
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// Helper functions for assembly syntax functions
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fn supervisorCall(imm16: u16) Instruction {
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return Instruction{
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.SupervisorCall = .{
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.imm16 = imm16,
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},
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};
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}
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// Supervisor Call
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pub fn svc(imm16: u16) Instruction {
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return supervisorCall(imm16);
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}
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};
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test "serialize instructions" {
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const Testcase = struct {
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inst: Instruction,
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expected: u32,
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};
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const testcases = [_]Testcase{
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.{ // svc #0
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.inst = Instruction.svc(0),
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.expected = 0b1101_0100_000_0000000000000000_00001,
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},
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.{ // svc #0x80 ; typical on Darwin
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.inst = Instruction.svc(0x80),
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.expected = 0b1101_0100_000_0000000010000000_00001,
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},
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};
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for (testcases) |case| {
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const actual = case.inst.toU32();
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testing.expectEqual(case.expected, actual);
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}
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}
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