582 lines
27 KiB
Zig
582 lines
27 KiB
Zig
const std = @import("std");
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const Allocator = std.mem.Allocator;
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const Target = std.Target;
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const log = std.log.scoped(.codegen);
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const spec = @import("spirv/spec.zig");
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const Opcode = spec.Opcode;
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const Module = @import("../Module.zig");
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const Decl = Module.Decl;
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const Type = @import("../type.zig").Type;
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const Value = @import("../value.zig").Value;
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const LazySrcLoc = Module.LazySrcLoc;
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const ir = @import("../ir.zig");
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const Inst = ir.Inst;
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pub const TypeMap = std.HashMap(Type, u32, Type.hash, Type.eql, std.hash_map.default_max_load_percentage);
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pub const ValueMap = std.AutoHashMap(*Inst, u32);
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pub fn writeOpcode(code: *std.ArrayList(u32), opcode: Opcode, arg_count: u32) !void {
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const word_count = arg_count + 1;
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try code.append((word_count << 16) | @enumToInt(opcode));
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}
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pub fn writeInstruction(code: *std.ArrayList(u32), opcode: Opcode, args: []const u32) !void {
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try writeOpcode(code, opcode, @intCast(u32, args.len));
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try code.appendSlice(args);
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}
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/// This structure represents a SPIR-V binary module being compiled, and keeps track of relevant information
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/// such as code for the different logical sections, and the next result-id.
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pub const SPIRVModule = struct {
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next_result_id: u32,
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types_globals_constants: std.ArrayList(u32),
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fn_decls: std.ArrayList(u32),
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pub fn init(allocator: *Allocator) SPIRVModule {
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return .{
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.next_result_id = 1, // 0 is an invalid SPIR-V result ID.
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.types_globals_constants = std.ArrayList(u32).init(allocator),
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.fn_decls = std.ArrayList(u32).init(allocator),
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};
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}
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pub fn deinit(self: *SPIRVModule) void {
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self.types_globals_constants.deinit();
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self.fn_decls.deinit();
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}
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pub fn allocResultId(self: *SPIRVModule) u32 {
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defer self.next_result_id += 1;
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return self.next_result_id;
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}
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pub fn resultIdBound(self: *SPIRVModule) u32 {
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return self.next_result_id;
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}
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};
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/// This structure is used to compile a declaration, and contains all relevant meta-information to deal with that.
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pub const DeclGen = struct {
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module: *Module,
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spv: *SPIRVModule,
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args: std.ArrayList(u32),
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next_arg_index: u32,
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types: TypeMap,
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values: ValueMap,
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decl: *Decl,
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error_msg: ?*Module.ErrorMsg,
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const Error = error{
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AnalysisFail,
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OutOfMemory
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};
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/// This structure is used to return information about a type typically used for arithmetic operations.
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/// These types may either be integers, floats, or a vector of these. Most scalar operations also work on vectors,
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/// so we can easily represent those as arithmetic types.
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/// If the type is a scalar, 'inner type' refers to the scalar type. Otherwise, if its a vector, it refers
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/// to the vector's element type.
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const ArithmeticTypeInfo = struct {
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/// A classification of the inner type.
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const Class = enum {
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/// A boolean.
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bool,
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/// A regular, **native**, integer.
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/// This is only returned when the backend supports this int as a native type (when
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/// the relevant capability is enabled).
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integer,
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/// A regular float. These are all required to be natively supported. Floating points for
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/// which the relevant capability is not enabled are not emulated.
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float,
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/// An integer of a 'strange' size (which' bit size is not the same as its backing type. **Note**: this
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/// may **also** include power-of-2 integers for which the relevant capability is not enabled), but still
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/// within the limits of the largest natively supported integer type.
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strange_integer,
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/// An integer with more bits than the largest natively supported integer type.
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composite_integer,
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};
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/// The number of bits in the inner type.
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/// Note: this is the actual number of bits of the type, not the size of the backing integer.
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bits: u16,
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/// Whether the type is a vector.
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is_vector: bool,
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/// Whether the inner type is signed. Only relevant for integers.
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signedness: std.builtin.Signedness,
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/// A classification of the inner type. These scenarios
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/// will all have to be handled slightly different.
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class: Class,
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};
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fn fail(self: *DeclGen, src: LazySrcLoc, comptime format: []const u8, args: anytype) Error {
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@setCold(true);
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const src_loc = src.toSrcLocWithDecl(self.decl);
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self.error_msg = try Module.ErrorMsg.create(self.module.gpa, src_loc, format, args);
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return error.AnalysisFail;
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}
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fn resolve(self: *DeclGen, inst: *Inst) !u32 {
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if (inst.value()) |val| {
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return self.genConstant(inst.ty, val);
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}
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return self.values.get(inst).?; // Instruction does not dominate all uses!
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}
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/// SPIR-V requires enabling specific integer sizes through capabilities, and so if they are not enabled, we need
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/// to emulate them in other instructions/types. This function returns, given an integer bit width (signed or unsigned, sign
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/// included), the width of the underlying type which represents it, given the enabled features for the current target.
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/// If the result is `null`, the largest type the target platform supports natively is not able to perform computations using
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/// that size. In this case, multiple elements of the largest type should be used.
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/// The backing type will be chosen as the smallest supported integer larger or equal to it in number of bits.
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/// The result is valid to be used with OpTypeInt.
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/// TODO: The extension SPV_INTEL_arbitrary_precision_integers allows any integer size (at least up to 32 bits).
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/// TODO: This probably needs an ABI-version as well (especially in combination with SPV_INTEL_arbitrary_precision_integers).
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/// TODO: Should the result of this function be cached?
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fn backingIntBits(self: *DeclGen, bits: u16) ?u16 {
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const target = self.module.getTarget();
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// TODO: Figure out what to do with u0/i0.
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std.debug.assert(bits != 0);
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// 8, 16 and 64-bit integers require the Int8, Int16 and Inr64 capabilities respectively.
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// 32-bit integers are always supported (see spec, 2.16.1, Data rules).
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const ints = [_]struct{ bits: u16, feature: ?Target.spirv.Feature } {
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.{ .bits = 8, .feature = .Int8 },
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.{ .bits = 16, .feature = .Int16 },
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.{ .bits = 32, .feature = null },
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.{ .bits = 64, .feature = .Int64 },
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};
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for (ints) |int| {
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const has_feature = if (int.feature) |feature|
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Target.spirv.featureSetHas(target.cpu.features, feature)
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else
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true;
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if (bits <= int.bits and has_feature) {
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return int.bits;
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}
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}
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return null;
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}
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/// Return the amount of bits in the largest supported integer type. This is either 32 (always supported), or 64 (if
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/// the Int64 capability is enabled).
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/// Note: The extension SPV_INTEL_arbitrary_precision_integers allows any integer size (at least up to 32 bits).
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/// In theory that could also be used, but since the spec says that it only guarantees support up to 32-bit ints there
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/// is no way of knowing whether those are actually supported.
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/// TODO: Maybe this should be cached?
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fn largestSupportedIntBits(self: *DeclGen) u16 {
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const target = self.module.getTarget();
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return if (Target.spirv.featureSetHas(target.cpu.features, .Int64))
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64
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else
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32;
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}
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/// Checks whether the type is "composite int", an integer consisting of multiple native integers. These are represented by
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/// arrays of largestSupportedIntBits().
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/// Asserts `ty` is an integer.
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fn isCompositeInt(self: *DeclGen, ty: Type) bool {
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return self.backingIntBits(ty) == null;
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}
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fn arithmeticTypeInfo(self: *DeclGen, ty: Type) !ArithmeticTypeInfo {
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const target = self.module.getTarget();
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return switch (ty.zigTypeTag()) {
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.Bool => ArithmeticTypeInfo{
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.bits = 1, // Doesn't matter for this class.
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.is_vector = false,
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.signedness = .unsigned, // Technically, but doesn't matter for this class.
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.class = .bool,
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},
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.Float => ArithmeticTypeInfo{
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.bits = ty.floatBits(target),
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.is_vector = false,
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.signedness = .signed, // Technically, but doesn't matter for this class.
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.class = .float,
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},
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.Int => blk: {
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const int_info = ty.intInfo(target);
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// TODO: Maybe it's useful to also return this value.
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const maybe_backing_bits = self.backingIntBits(int_info.bits);
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break :blk ArithmeticTypeInfo{
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.bits = int_info.bits,
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.is_vector = false,
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.signedness = int_info.signedness,
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.class = if (maybe_backing_bits) |backing_bits|
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if (backing_bits == int_info.bits)
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ArithmeticTypeInfo.Class.integer
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else
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ArithmeticTypeInfo.Class.strange_integer
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else
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.composite_integer
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};
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},
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// As of yet, there is no vector support in the self-hosted compiler.
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.Vector => self.fail(.{.node_offset = 0}, "TODO: SPIR-V backend: implement arithmeticTypeInfo for Vector", .{}),
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// TODO: For which types is this the case?
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else => self.fail(.{.node_offset = 0}, "TODO: SPIR-V backend: implement arithmeticTypeInfo for {}", .{ty}),
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};
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}
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/// Generate a constant representing `val`.
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/// TODO: Deduplication?
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fn genConstant(self: *DeclGen, ty: Type, val: Value) Error!u32 {
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const code = &self.spv.types_globals_constants;
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const result_id = self.spv.allocResultId();
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const result_type_id = try self.getOrGenType(ty);
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if (val.isUndef()) {
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try writeInstruction(code, .OpUndef, &[_]u32{ result_type_id, result_id });
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return result_id;
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}
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switch (ty.zigTypeTag()) {
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.Bool => {
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const opcode: Opcode = if (val.toBool()) .OpConstantTrue else .OpConstantFalse;
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try writeInstruction(code, opcode, &[_]u32{ result_type_id, result_id });
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},
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.Float => {
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// At this point we are guaranteed that the target floating point type is supported, otherwise the function
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// would have exited at getOrGenType(ty).
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// f16 and f32 require one word of storage. f64 requires 2, low-order first.
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switch (val.tag()) {
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.float_16 => try writeInstruction(code, .OpConstant, &[_]u32{
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result_type_id,
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result_id,
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@bitCast(u16, val.castTag(.float_16).?.data)
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}),
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.float_32 => try writeInstruction(code, .OpConstant, &[_]u32{
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result_type_id,
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result_id,
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@bitCast(u32, val.castTag(.float_32).?.data)
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}),
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.float_64 => {
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const float_bits = @bitCast(u64, val.castTag(.float_64).?.data);
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try writeInstruction(code, .OpConstant, &[_]u32{
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result_type_id,
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result_id,
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@truncate(u32, float_bits),
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@truncate(u32, float_bits >> 32),
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});
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},
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.float_128 => unreachable, // Filtered out in the call to getOrGenType.
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// TODO: What tags do we need to handle here anyway?
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else => return self.fail(.{.node_offset = 0}, "TODO: SPIR-V backend: float constant generation of value {s}\n", .{ val.tag() }),
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}
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},
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else => return self.fail(.{.node_offset = 0}, "TODO: SPIR-V backend: constant generation of type {s}\n", .{ ty.zigTypeTag() }),
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}
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return result_id;
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}
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fn getOrGenType(self: *DeclGen, ty: Type) Error!u32 {
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// We can't use getOrPut here so we can recursively generate types.
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if (self.types.get(ty)) |already_generated| {
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return already_generated;
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}
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const target = self.module.getTarget();
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const code = &self.spv.types_globals_constants;
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const result_id = self.spv.allocResultId();
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switch (ty.zigTypeTag()) {
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.Void => try writeInstruction(code, .OpTypeVoid, &[_]u32{ result_id }),
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.Bool => try writeInstruction(code, .OpTypeBool, &[_]u32{ result_id }),
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.Int => {
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const int_info = ty.intInfo(target);
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const backing_bits = self.backingIntBits(int_info.bits) orelse {
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// Integers too big for any native type are represented as "composite integers": An array of largestSupportedIntBits.
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return self.fail(.{.node_offset = 0}, "TODO: SPIR-V backend: implement composite ints {}", .{ ty });
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};
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// TODO: If backing_bits != int_info.bits, a duplicate type might be generated here.
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try writeInstruction(code, .OpTypeInt, &[_]u32{
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result_id,
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backing_bits,
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switch (int_info.signedness) {
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.unsigned => 0,
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.signed => 1,
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},
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});
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},
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.Float => {
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// We can (and want) not really emulate floating points with other floating point types like with the integer types,
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// so if the float is not supported, just return an error.
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const bits = ty.floatBits(target);
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const supported = switch (bits) {
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16 => Target.spirv.featureSetHas(target.cpu.features, .Float16),
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// 32-bit floats are always supported (see spec, 2.16.1, Data rules).
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32 => true,
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64 => Target.spirv.featureSetHas(target.cpu.features, .Float64),
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else => false,
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};
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if (!supported) {
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return self.fail(.{.node_offset = 0}, "Floating point width of {} bits is not supported for the current SPIR-V feature set", .{ bits });
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}
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try writeInstruction(code, .OpTypeFloat, &[_]u32{ result_id, bits });
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},
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.Fn => {
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// We only support zig-calling-convention functions, no varargs.
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if (ty.fnCallingConvention() != .Unspecified)
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return self.fail(.{.node_offset = 0}, "Unsupported calling convention for SPIR-V", .{});
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if (ty.fnIsVarArgs())
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return self.fail(.{.node_offset = 0}, "VarArgs unsupported for SPIR-V", .{});
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// In order to avoid a temporary here, first generate all the required types and then simply look them up
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// when generating the function type.
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const params = ty.fnParamLen();
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var i: usize = 0;
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while (i < params) : (i += 1) {
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_ = try self.getOrGenType(ty.fnParamType(i));
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}
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const return_type_id = try self.getOrGenType(ty.fnReturnType());
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// result id + result type id + parameter type ids.
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try writeOpcode(code, .OpTypeFunction, 2 + @intCast(u32, ty.fnParamLen()) );
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try code.appendSlice(&.{ result_id, return_type_id });
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i = 0;
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while (i < params) : (i += 1) {
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const param_type_id = self.types.get(ty.fnParamType(i)).?;
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try code.append(param_type_id);
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}
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},
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.Vector => {
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// Although not 100% the same, Zig vectors map quite neatly to SPIR-V vectors (including many integer and float operations
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// which work on them), so simply use those.
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// Note: SPIR-V vectors only support bools, ints and floats, so pointer vectors need to be supported another way.
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// "composite integers" (larger than the largest supported native type) can probably be represented by an array of vectors.
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// TODO: The SPIR-V spec mentions that vector sizes may be quite restricted! look into which we can use, and whether OpTypeVector
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// is adequate at all for this.
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// TODO: Vectors are not yet supported by the self-hosted compiler itself it seems.
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return self.fail(.{.node_offset = 0}, "TODO: SPIR-V backend: implement type Vector", .{});
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},
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.Null,
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.Undefined,
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.EnumLiteral,
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.ComptimeFloat,
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.ComptimeInt,
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.Type,
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=> unreachable, // Must be const or comptime.
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.BoundFn => unreachable, // this type will be deleted from the language.
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else => |tag| return self.fail(.{.node_offset = 0}, "TODO: SPIR-V backend: implement type {}s", .{ tag }),
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}
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try self.types.putNoClobber(ty, result_id);
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return result_id;
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|
}
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pub fn gen(self: *DeclGen) !void {
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const result_id = self.decl.fn_link.spirv.id;
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const tv = self.decl.typed_value.most_recent.typed_value;
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if (tv.val.castTag(.function)) |func_payload| {
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std.debug.assert(tv.ty.zigTypeTag() == .Fn);
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const prototype_id = try self.getOrGenType(tv.ty);
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try writeInstruction(&self.spv.fn_decls, .OpFunction, &[_]u32{
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self.types.get(tv.ty.fnReturnType()).?, // This type should be generated along with the prototype.
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result_id,
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@bitCast(u32, spec.FunctionControl{}), // TODO: We can set inline here if the type requires it.
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prototype_id,
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|
});
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|
|
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const params = tv.ty.fnParamLen();
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var i: usize = 0;
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|
|
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try self.args.ensureCapacity(params);
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while (i < params) : (i += 1) {
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const param_type_id = self.types.get(tv.ty.fnParamType(i)).?;
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const arg_result_id = self.spv.allocResultId();
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try writeInstruction(&self.spv.fn_decls, .OpFunctionParameter, &[_]u32{ param_type_id, arg_result_id });
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self.args.appendAssumeCapacity(arg_result_id);
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|
}
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|
|
|
// TODO: This could probably be done in a better way...
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const root_block_id = self.spv.allocResultId();
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_ = try writeInstruction(&self.spv.fn_decls, .OpLabel, &[_]u32{root_block_id});
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try self.genBody(func_payload.data.body);
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|
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try writeInstruction(&self.spv.fn_decls, .OpFunctionEnd, &[_]u32{});
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} else {
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return self.fail(.{.node_offset = 0}, "TODO: SPIR-V backend: generate decl type {}", .{ tv.ty.zigTypeTag() });
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|
}
|
|
}
|
|
|
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fn genBody(self: *DeclGen, body: ir.Body) !void {
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for (body.instructions) |inst| {
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const maybe_result_id = try self.genInst(inst);
|
|
if (maybe_result_id) |result_id|
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try self.values.putNoClobber(inst, result_id);
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}
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|
}
|
|
|
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fn genInst(self: *DeclGen, inst: *Inst) !?u32 {
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return switch (inst.tag) {
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|
.add, .addwrap => try self.genBinOp(inst.castTag(.add).?),
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|
.sub, .subwrap => try self.genBinOp(inst.castTag(.sub).?),
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|
.mul, .mulwrap => try self.genBinOp(inst.castTag(.mul).?),
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|
.div => try self.genBinOp(inst.castTag(.div).?),
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|
.bit_and => try self.genBinOp(inst.castTag(.bit_and).?),
|
|
.bit_or => try self.genBinOp(inst.castTag(.bit_or).?),
|
|
.xor => try self.genBinOp(inst.castTag(.xor).?),
|
|
.cmp_eq => try self.genBinOp(inst.castTag(.cmp_eq).?),
|
|
.cmp_neq => try self.genBinOp(inst.castTag(.cmp_neq).?),
|
|
.cmp_gt => try self.genBinOp(inst.castTag(.cmp_gt).?),
|
|
.cmp_gte => try self.genBinOp(inst.castTag(.cmp_gte).?),
|
|
.cmp_lt => try self.genBinOp(inst.castTag(.cmp_lt).?),
|
|
.cmp_lte => try self.genBinOp(inst.castTag(.cmp_lte).?),
|
|
.bool_and => try self.genBinOp(inst.castTag(.bool_and).?),
|
|
.bool_or => try self.genBinOp(inst.castTag(.bool_or).?),
|
|
.not => try self.genUnOp(inst.castTag(.not).?),
|
|
.arg => self.genArg(),
|
|
// TODO: Breakpoints won't be supported in SPIR-V, but the compiler seems to insert them
|
|
// throughout the IR.
|
|
.breakpoint => null,
|
|
.dbg_stmt => null,
|
|
.ret => self.genRet(inst.castTag(.ret).?),
|
|
.retvoid => self.genRetVoid(),
|
|
.unreach => self.genUnreach(),
|
|
else => self.fail(.{.node_offset = 0}, "TODO: SPIR-V backend: implement inst {}", .{inst.tag}),
|
|
};
|
|
}
|
|
|
|
fn genBinOp(self: *DeclGen, inst: *Inst.BinOp) !u32 {
|
|
// TODO: Will lhs and rhs have the same type?
|
|
const lhs_id = try self.resolve(inst.lhs);
|
|
const rhs_id = try self.resolve(inst.rhs);
|
|
|
|
const result_id = self.spv.allocResultId();
|
|
const result_type_id = try self.getOrGenType(inst.base.ty);
|
|
|
|
// TODO: Is the result the same as the argument types?
|
|
// This is supposed to be the case for SPIR-V.
|
|
std.debug.assert(inst.rhs.ty.eql(inst.lhs.ty));
|
|
std.debug.assert(inst.base.ty.tag() == .bool or inst.base.ty.eql(inst.lhs.ty));
|
|
|
|
// Binary operations are generally applicable to both scalar and vector operations in SPIR-V, but int and float
|
|
// versions of operations require different opcodes.
|
|
// For operations which produce bools, the information of inst.base.ty is not useful, so just pick either operand
|
|
// instead.
|
|
const info = try self.arithmeticTypeInfo(inst.lhs.ty);
|
|
|
|
if (info.class == .composite_integer)
|
|
return self.fail(.{.node_offset = 0}, "TODO: SPIR-V backend: binary operations for composite integers", .{});
|
|
|
|
const is_bool = info.class == .bool;
|
|
const is_float = info.class == .float;
|
|
const is_signed = info.signedness == .signed;
|
|
// **Note**: All these operations must be valid for vectors of floats, integers and bools as well!
|
|
// For floating points, we generally want ordered operations (which return false if either operand is nan).
|
|
const opcode = switch (inst.base.tag) {
|
|
// The regular integer operations are all defined for wrapping. Since theyre only relevant for integers,
|
|
// we can just switch on both cases here.
|
|
.add, .addwrap => if (is_float) Opcode.OpFAdd else Opcode.OpIAdd,
|
|
.sub, .subwrap => if (is_float) Opcode.OpFSub else Opcode.OpISub,
|
|
.mul, .mulwrap => if (is_float) Opcode.OpFMul else Opcode.OpIMul,
|
|
// TODO: Trap if divisor is 0?
|
|
// TODO: Figure out of OpSDiv for unsigned/OpUDiv for signed does anything useful.
|
|
// => Those are probably for divTrunc and divFloor, though the compiler does not yet generate those.
|
|
// => TODO: Figure out how those work on the SPIR-V side.
|
|
// => TODO: Test these.
|
|
.div => if (is_float) Opcode.OpFDiv else if (is_signed) Opcode.OpSDiv else Opcode.OpUDiv,
|
|
// Only integer versions for these.
|
|
.bit_and => Opcode.OpBitwiseAnd,
|
|
.bit_or => Opcode.OpBitwiseOr,
|
|
.xor => Opcode.OpBitwiseXor,
|
|
// Int/bool/float -> bool operations.
|
|
.cmp_eq => if (is_float) Opcode.OpFOrdEqual else if (is_bool) Opcode.OpLogicalEqual else Opcode.OpIEqual,
|
|
.cmp_neq => if (is_float) Opcode.OpFOrdNotEqual else if (is_bool) Opcode.OpLogicalNotEqual else Opcode.OpINotEqual,
|
|
// Int/float -> bool operations.
|
|
// TODO: Verify that these OpFOrd type operations produce the right value.
|
|
// TODO: Is there a more fundamental difference between OpU and OpS operations here than just the type?
|
|
.cmp_gt => if (is_float) Opcode.OpFOrdGreaterThan else if (is_signed) Opcode.OpSGreaterThan else Opcode.OpUGreaterThan,
|
|
.cmp_gte => if (is_float) Opcode.OpFOrdGreaterThanEqual else if (is_signed) Opcode.OpSGreaterThanEqual else Opcode.OpUGreaterThanEqual,
|
|
.cmp_lt => if (is_float) Opcode.OpFOrdLessThan else if (is_signed) Opcode.OpSLessThan else Opcode.OpULessThan,
|
|
.cmp_lte => if (is_float) Opcode.OpFOrdLessThanEqual else if (is_signed) Opcode.OpSLessThanEqual else Opcode.OpULessThanEqual,
|
|
// Bool -> bool operations.
|
|
.bool_and => Opcode.OpLogicalAnd,
|
|
.bool_or => Opcode.OpLogicalOr,
|
|
else => unreachable,
|
|
};
|
|
|
|
try writeInstruction(&self.spv.fn_decls, opcode, &[_]u32{ result_type_id, result_id, lhs_id, rhs_id });
|
|
|
|
// TODO: Trap on overflow? Probably going to be annoying.
|
|
// TODO: Look into SPV_KHR_no_integer_wrap_decoration which provides NoSignedWrap/NoUnsignedWrap.
|
|
|
|
if (info.class != .strange_integer)
|
|
return result_id;
|
|
|
|
return self.fail(.{.node_offset = 0}, "TODO: SPIR-V backend: strange integer operation mask", .{});
|
|
}
|
|
|
|
fn genUnOp(self: *DeclGen, inst: *Inst.UnOp) !u32 {
|
|
const operand_id = try self.resolve(inst.operand);
|
|
|
|
const result_id = self.spv.allocResultId();
|
|
const result_type_id = try self.getOrGenType(inst.base.ty);
|
|
|
|
const info = try self.arithmeticTypeInfo(inst.operand.ty);
|
|
|
|
const opcode = switch (inst.base.tag) {
|
|
// Bool -> bool
|
|
.not => Opcode.OpLogicalNot,
|
|
else => unreachable,
|
|
};
|
|
|
|
try writeInstruction(&self.spv.fn_decls, opcode, &[_]u32{ result_type_id, result_id, operand_id });
|
|
|
|
return result_id;
|
|
}
|
|
|
|
fn genArg(self: *DeclGen) u32 {
|
|
defer self.next_arg_index += 1;
|
|
return self.args.items[self.next_arg_index];
|
|
}
|
|
|
|
fn genRet(self: *DeclGen, inst: *Inst.UnOp) !?u32 {
|
|
const operand_id = try self.resolve(inst.operand);
|
|
// TODO: This instruction needs to be the last in a block. Is that guaranteed?
|
|
try writeInstruction(&self.spv.fn_decls, .OpReturnValue, &[_]u32{ operand_id });
|
|
return null;
|
|
}
|
|
|
|
fn genRetVoid(self: *DeclGen) !?u32 {
|
|
// TODO: This instruction needs to be the last in a block. Is that guaranteed?
|
|
try writeInstruction(&self.spv.fn_decls, .OpReturn, &[_]u32{});
|
|
return null;
|
|
}
|
|
|
|
fn genUnreach(self: *DeclGen) !?u32 {
|
|
// TODO: This instruction needs to be the last in a block. Is that guaranteed?
|
|
try writeInstruction(&self.spv.fn_decls, .OpUnreachable, &[_]u32{});
|
|
return null;
|
|
}
|
|
};
|