5b813f1a2a
Prior to this change we would assume the ABI for Apple targets to be GNU which could result in subtle errors in LLVM emitting calls to non-existent system libc provided functions such as `_sincosf` which is a GNU extension and as such is not provided by macOS for example. This would result in linker errors where the linker would not be able to find the said symbol in `libSystem.tbd`. With this change, we now correctly identify macOS (and other Apple platforms) as having ABI `unknown` which translates to unspecified in LLVM under-the-hood: ``` // main.ll target triple = "aarch64-unknown-macos-unknown" ``` Note however that we never suffix the target OS with target version such as `macos11` or `macos12` which means we fail to instruct LLVM of potential optimisations provided by the OS such as the availability of function `___sincosf_stret`. I suggest we investigate that in a follow-up commit.
1232 lines
40 KiB
C
Vendored
1232 lines
40 KiB
C
Vendored
/*
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* Copyright (c) 2004-2006 Apple Computer, Inc. All rights reserved.
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*
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* @APPLE_OSREFERENCE_LICENSE_HEADER_START@
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*
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* This file contains Original Code and/or Modifications of Original Code
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* as defined in and that are subject to the Apple Public Source License
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* Version 2.0 (the 'License'). You may not use this file except in
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* compliance with the License. The rights granted to you under the License
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* may not be used to create, or enable the creation or redistribution of,
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* unlawful or unlicensed copies of an Apple operating system, or to
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* circumvent, violate, or enable the circumvention or violation of, any
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* terms of an Apple operating system software license agreement.
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*
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* Please obtain a copy of the License at
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* http://www.opensource.apple.com/apsl/ and read it before using this file.
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*
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* The Original Code and all software distributed under the License are
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* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
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* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
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* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
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* Please see the License for the specific language governing rights and
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* limitations under the License.
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*
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* @APPLE_OSREFERENCE_LICENSE_HEADER_END@
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*/
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/*
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* @OSF_COPYRIGHT@
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*/
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#ifndef _MACH_I386__STRUCTS_H_
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#define _MACH_I386__STRUCTS_H_
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#include <sys/cdefs.h> /* __DARWIN_UNIX03 */
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#include <machine/types.h> /* __uint8_t */
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/*
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* i386 is the structure that is exported to user threads for
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* use in status/mutate calls. This structure should never change.
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*
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*/
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#if __DARWIN_UNIX03
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#define _STRUCT_X86_THREAD_STATE32 struct __darwin_i386_thread_state
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_STRUCT_X86_THREAD_STATE32
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{
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unsigned int __eax;
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unsigned int __ebx;
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unsigned int __ecx;
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unsigned int __edx;
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unsigned int __edi;
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unsigned int __esi;
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unsigned int __ebp;
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unsigned int __esp;
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unsigned int __ss;
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unsigned int __eflags;
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unsigned int __eip;
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unsigned int __cs;
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unsigned int __ds;
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unsigned int __es;
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unsigned int __fs;
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unsigned int __gs;
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};
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#else /* !__DARWIN_UNIX03 */
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#define _STRUCT_X86_THREAD_STATE32 struct i386_thread_state
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_STRUCT_X86_THREAD_STATE32
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{
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unsigned int eax;
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unsigned int ebx;
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unsigned int ecx;
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unsigned int edx;
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unsigned int edi;
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unsigned int esi;
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unsigned int ebp;
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unsigned int esp;
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unsigned int ss;
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unsigned int eflags;
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unsigned int eip;
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unsigned int cs;
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unsigned int ds;
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unsigned int es;
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unsigned int fs;
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unsigned int gs;
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};
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#endif /* !__DARWIN_UNIX03 */
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/* This structure should be double-word aligned for performance */
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#if __DARWIN_UNIX03
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#define _STRUCT_FP_CONTROL struct __darwin_fp_control
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_STRUCT_FP_CONTROL
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{
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unsigned short __invalid :1,
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__denorm :1,
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__zdiv :1,
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__ovrfl :1,
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__undfl :1,
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__precis :1,
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:2,
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__pc :2,
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#if !defined(_POSIX_C_SOURCE) || defined(_DARWIN_C_SOURCE)
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#define FP_PREC_24B 0
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#define FP_PREC_53B 2
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#define FP_PREC_64B 3
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#endif /* !_POSIX_C_SOURCE || _DARWIN_C_SOURCE */
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__rc :2,
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#if !defined(_POSIX_C_SOURCE) || defined(_DARWIN_C_SOURCE)
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#define FP_RND_NEAR 0
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#define FP_RND_DOWN 1
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#define FP_RND_UP 2
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#define FP_CHOP 3
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#endif /* !_POSIX_C_SOURCE || _DARWIN_C_SOURCE */
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/*inf*/ :1,
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:3;
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};
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typedef _STRUCT_FP_CONTROL __darwin_fp_control_t;
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#else /* !__DARWIN_UNIX03 */
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#define _STRUCT_FP_CONTROL struct fp_control
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_STRUCT_FP_CONTROL
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{
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unsigned short invalid :1,
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denorm :1,
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zdiv :1,
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ovrfl :1,
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undfl :1,
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precis :1,
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:2,
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pc :2,
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#define FP_PREC_24B 0
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#define FP_PREC_53B 2
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#define FP_PREC_64B 3
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rc :2,
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#define FP_RND_NEAR 0
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#define FP_RND_DOWN 1
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#define FP_RND_UP 2
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#define FP_CHOP 3
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/*inf*/ :1,
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:3;
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};
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typedef _STRUCT_FP_CONTROL fp_control_t;
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#endif /* !__DARWIN_UNIX03 */
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/*
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* Status word.
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*/
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#if __DARWIN_UNIX03
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#define _STRUCT_FP_STATUS struct __darwin_fp_status
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_STRUCT_FP_STATUS
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{
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unsigned short __invalid :1,
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__denorm :1,
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__zdiv :1,
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__ovrfl :1,
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__undfl :1,
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__precis :1,
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__stkflt :1,
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__errsumm :1,
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__c0 :1,
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__c1 :1,
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__c2 :1,
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__tos :3,
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__c3 :1,
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__busy :1;
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};
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typedef _STRUCT_FP_STATUS __darwin_fp_status_t;
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#else /* !__DARWIN_UNIX03 */
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#define _STRUCT_FP_STATUS struct fp_status
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_STRUCT_FP_STATUS
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{
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unsigned short invalid :1,
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denorm :1,
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zdiv :1,
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ovrfl :1,
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undfl :1,
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precis :1,
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stkflt :1,
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errsumm :1,
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c0 :1,
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c1 :1,
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c2 :1,
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tos :3,
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c3 :1,
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busy :1;
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};
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typedef _STRUCT_FP_STATUS fp_status_t;
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#endif /* !__DARWIN_UNIX03 */
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/* defn of 80bit x87 FPU or MMX register */
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#if __DARWIN_UNIX03
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#define _STRUCT_MMST_REG struct __darwin_mmst_reg
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_STRUCT_MMST_REG
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{
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char __mmst_reg[10];
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char __mmst_rsrv[6];
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};
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#else /* !__DARWIN_UNIX03 */
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#define _STRUCT_MMST_REG struct mmst_reg
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_STRUCT_MMST_REG
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{
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char mmst_reg[10];
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char mmst_rsrv[6];
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};
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#endif /* !__DARWIN_UNIX03 */
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/* defn of 128 bit XMM regs */
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#if __DARWIN_UNIX03
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#define _STRUCT_XMM_REG struct __darwin_xmm_reg
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_STRUCT_XMM_REG
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{
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char __xmm_reg[16];
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};
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#else /* !__DARWIN_UNIX03 */
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#define _STRUCT_XMM_REG struct xmm_reg
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_STRUCT_XMM_REG
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{
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char xmm_reg[16];
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};
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#endif /* !__DARWIN_UNIX03 */
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/* defn of 256 bit YMM regs */
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#if __DARWIN_UNIX03
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#define _STRUCT_YMM_REG struct __darwin_ymm_reg
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_STRUCT_YMM_REG
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{
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char __ymm_reg[32];
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};
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#else /* !__DARWIN_UNIX03 */
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#define _STRUCT_YMM_REG struct ymm_reg
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_STRUCT_YMM_REG
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{
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char ymm_reg[32];
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};
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#endif /* !__DARWIN_UNIX03 */
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/* defn of 512 bit ZMM regs */
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#if __DARWIN_UNIX03
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#define _STRUCT_ZMM_REG struct __darwin_zmm_reg
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_STRUCT_ZMM_REG
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{
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char __zmm_reg[64];
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};
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#else /* !__DARWIN_UNIX03 */
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#define _STRUCT_ZMM_REG struct zmm_reg
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_STRUCT_ZMM_REG
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{
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char zmm_reg[64];
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};
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#endif /* !__DARWIN_UNIX03 */
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#if __DARWIN_UNIX03
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#define _STRUCT_OPMASK_REG struct __darwin_opmask_reg
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_STRUCT_OPMASK_REG
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{
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char __opmask_reg[8];
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};
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#else /* !__DARWIN_UNIX03 */
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#define _STRUCT_OPMASK_REG struct opmask_reg
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_STRUCT_OPMASK_REG
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{
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char opmask_reg[8];
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};
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#endif /* !__DARWIN_UNIX03 */
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/*
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* Floating point state.
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*/
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#if !defined(_POSIX_C_SOURCE) || defined(_DARWIN_C_SOURCE)
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#define FP_STATE_BYTES 512 /* number of chars worth of data from fpu_fcw */
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#endif /* !_POSIX_C_SOURCE || _DARWIN_C_SOURCE */
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#if __DARWIN_UNIX03
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#define _STRUCT_X86_FLOAT_STATE32 struct __darwin_i386_float_state
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_STRUCT_X86_FLOAT_STATE32
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{
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int __fpu_reserved[2];
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_STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
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_STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
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__uint8_t __fpu_ftw; /* x87 FPU tag word */
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__uint8_t __fpu_rsrv1; /* reserved */
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__uint16_t __fpu_fop; /* x87 FPU Opcode */
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__uint32_t __fpu_ip; /* x87 FPU Instruction Pointer offset */
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__uint16_t __fpu_cs; /* x87 FPU Instruction Pointer Selector */
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__uint16_t __fpu_rsrv2; /* reserved */
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__uint32_t __fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
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__uint16_t __fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
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__uint16_t __fpu_rsrv3; /* reserved */
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__uint32_t __fpu_mxcsr; /* MXCSR Register state */
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__uint32_t __fpu_mxcsrmask; /* MXCSR mask */
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_STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
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_STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
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_STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
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_STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
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_STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
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_STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
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_STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
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_STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
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_STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
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_STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
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_STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
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_STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
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_STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
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_STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
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_STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
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_STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
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char __fpu_rsrv4[14*16]; /* reserved */
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int __fpu_reserved1;
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};
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#define _STRUCT_X86_AVX_STATE32 struct __darwin_i386_avx_state
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_STRUCT_X86_AVX_STATE32
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{
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int __fpu_reserved[2];
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_STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
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_STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
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__uint8_t __fpu_ftw; /* x87 FPU tag word */
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__uint8_t __fpu_rsrv1; /* reserved */
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__uint16_t __fpu_fop; /* x87 FPU Opcode */
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__uint32_t __fpu_ip; /* x87 FPU Instruction Pointer offset */
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__uint16_t __fpu_cs; /* x87 FPU Instruction Pointer Selector */
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__uint16_t __fpu_rsrv2; /* reserved */
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__uint32_t __fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
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__uint16_t __fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
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__uint16_t __fpu_rsrv3; /* reserved */
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__uint32_t __fpu_mxcsr; /* MXCSR Register state */
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__uint32_t __fpu_mxcsrmask; /* MXCSR mask */
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_STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
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_STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
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_STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
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_STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
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_STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
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_STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
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_STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
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_STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
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_STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
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_STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
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_STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
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_STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
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_STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
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_STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
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_STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
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_STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
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char __fpu_rsrv4[14*16]; /* reserved */
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int __fpu_reserved1;
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char __avx_reserved1[64];
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_STRUCT_XMM_REG __fpu_ymmh0; /* YMMH 0 */
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_STRUCT_XMM_REG __fpu_ymmh1; /* YMMH 1 */
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_STRUCT_XMM_REG __fpu_ymmh2; /* YMMH 2 */
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_STRUCT_XMM_REG __fpu_ymmh3; /* YMMH 3 */
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_STRUCT_XMM_REG __fpu_ymmh4; /* YMMH 4 */
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_STRUCT_XMM_REG __fpu_ymmh5; /* YMMH 5 */
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_STRUCT_XMM_REG __fpu_ymmh6; /* YMMH 6 */
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_STRUCT_XMM_REG __fpu_ymmh7; /* YMMH 7 */
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};
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#define _STRUCT_X86_AVX512_STATE32 struct __darwin_i386_avx512_state
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_STRUCT_X86_AVX512_STATE32
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{
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int __fpu_reserved[2];
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_STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
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_STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
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__uint8_t __fpu_ftw; /* x87 FPU tag word */
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__uint8_t __fpu_rsrv1; /* reserved */
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__uint16_t __fpu_fop; /* x87 FPU Opcode */
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__uint32_t __fpu_ip; /* x87 FPU Instruction Pointer offset */
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__uint16_t __fpu_cs; /* x87 FPU Instruction Pointer Selector */
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__uint16_t __fpu_rsrv2; /* reserved */
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__uint32_t __fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
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__uint16_t __fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
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__uint16_t __fpu_rsrv3; /* reserved */
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__uint32_t __fpu_mxcsr; /* MXCSR Register state */
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__uint32_t __fpu_mxcsrmask; /* MXCSR mask */
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_STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
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_STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
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_STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
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_STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
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_STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
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_STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
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_STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
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_STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
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_STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
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_STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
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_STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
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_STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
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_STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
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_STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
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_STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
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_STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
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char __fpu_rsrv4[14*16]; /* reserved */
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int __fpu_reserved1;
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char __avx_reserved1[64];
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_STRUCT_XMM_REG __fpu_ymmh0; /* YMMH 0 */
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_STRUCT_XMM_REG __fpu_ymmh1; /* YMMH 1 */
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_STRUCT_XMM_REG __fpu_ymmh2; /* YMMH 2 */
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_STRUCT_XMM_REG __fpu_ymmh3; /* YMMH 3 */
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_STRUCT_XMM_REG __fpu_ymmh4; /* YMMH 4 */
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_STRUCT_XMM_REG __fpu_ymmh5; /* YMMH 5 */
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_STRUCT_XMM_REG __fpu_ymmh6; /* YMMH 6 */
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_STRUCT_XMM_REG __fpu_ymmh7; /* YMMH 7 */
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_STRUCT_OPMASK_REG __fpu_k0; /* K0 */
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_STRUCT_OPMASK_REG __fpu_k1; /* K1 */
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_STRUCT_OPMASK_REG __fpu_k2; /* K2 */
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_STRUCT_OPMASK_REG __fpu_k3; /* K3 */
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_STRUCT_OPMASK_REG __fpu_k4; /* K4 */
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_STRUCT_OPMASK_REG __fpu_k5; /* K5 */
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_STRUCT_OPMASK_REG __fpu_k6; /* K6 */
|
|
_STRUCT_OPMASK_REG __fpu_k7; /* K7 */
|
|
_STRUCT_YMM_REG __fpu_zmmh0; /* ZMMH 0 */
|
|
_STRUCT_YMM_REG __fpu_zmmh1; /* ZMMH 1 */
|
|
_STRUCT_YMM_REG __fpu_zmmh2; /* ZMMH 2 */
|
|
_STRUCT_YMM_REG __fpu_zmmh3; /* ZMMH 3 */
|
|
_STRUCT_YMM_REG __fpu_zmmh4; /* ZMMH 4 */
|
|
_STRUCT_YMM_REG __fpu_zmmh5; /* ZMMH 5 */
|
|
_STRUCT_YMM_REG __fpu_zmmh6; /* ZMMH 6 */
|
|
_STRUCT_YMM_REG __fpu_zmmh7; /* ZMMH 7 */
|
|
};
|
|
|
|
#else /* !__DARWIN_UNIX03 */
|
|
#define _STRUCT_X86_FLOAT_STATE32 struct i386_float_state
|
|
_STRUCT_X86_FLOAT_STATE32
|
|
{
|
|
int fpu_reserved[2];
|
|
_STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
|
|
_STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
|
|
__uint8_t fpu_ftw; /* x87 FPU tag word */
|
|
__uint8_t fpu_rsrv1; /* reserved */
|
|
__uint16_t fpu_fop; /* x87 FPU Opcode */
|
|
__uint32_t fpu_ip; /* x87 FPU Instruction Pointer offset */
|
|
__uint16_t fpu_cs; /* x87 FPU Instruction Pointer Selector */
|
|
__uint16_t fpu_rsrv2; /* reserved */
|
|
__uint32_t fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
|
|
__uint16_t fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
|
|
__uint16_t fpu_rsrv3; /* reserved */
|
|
__uint32_t fpu_mxcsr; /* MXCSR Register state */
|
|
__uint32_t fpu_mxcsrmask; /* MXCSR mask */
|
|
_STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
|
|
_STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
|
|
_STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
|
|
_STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
|
|
_STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
|
|
_STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
|
|
_STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
|
|
_STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
|
|
_STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
|
|
_STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
|
|
_STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
|
|
_STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
|
|
_STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
|
|
_STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
|
|
_STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
|
|
_STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
|
|
char fpu_rsrv4[14*16]; /* reserved */
|
|
int fpu_reserved1;
|
|
};
|
|
|
|
#define _STRUCT_X86_AVX_STATE32 struct i386_avx_state
|
|
_STRUCT_X86_AVX_STATE32
|
|
{
|
|
int fpu_reserved[2];
|
|
_STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
|
|
_STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
|
|
__uint8_t fpu_ftw; /* x87 FPU tag word */
|
|
__uint8_t fpu_rsrv1; /* reserved */
|
|
__uint16_t fpu_fop; /* x87 FPU Opcode */
|
|
__uint32_t fpu_ip; /* x87 FPU Instruction Pointer offset */
|
|
__uint16_t fpu_cs; /* x87 FPU Instruction Pointer Selector */
|
|
__uint16_t fpu_rsrv2; /* reserved */
|
|
__uint32_t fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
|
|
__uint16_t fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
|
|
__uint16_t fpu_rsrv3; /* reserved */
|
|
__uint32_t fpu_mxcsr; /* MXCSR Register state */
|
|
__uint32_t fpu_mxcsrmask; /* MXCSR mask */
|
|
_STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
|
|
_STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
|
|
_STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
|
|
_STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
|
|
_STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
|
|
_STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
|
|
_STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
|
|
_STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
|
|
_STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
|
|
_STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
|
|
_STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
|
|
_STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
|
|
_STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
|
|
_STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
|
|
_STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
|
|
_STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
|
|
char fpu_rsrv4[14*16]; /* reserved */
|
|
int fpu_reserved1;
|
|
char avx_reserved1[64];
|
|
_STRUCT_XMM_REG fpu_ymmh0; /* YMMH 0 */
|
|
_STRUCT_XMM_REG fpu_ymmh1; /* YMMH 1 */
|
|
_STRUCT_XMM_REG fpu_ymmh2; /* YMMH 2 */
|
|
_STRUCT_XMM_REG fpu_ymmh3; /* YMMH 3 */
|
|
_STRUCT_XMM_REG fpu_ymmh4; /* YMMH 4 */
|
|
_STRUCT_XMM_REG fpu_ymmh5; /* YMMH 5 */
|
|
_STRUCT_XMM_REG fpu_ymmh6; /* YMMH 6 */
|
|
_STRUCT_XMM_REG fpu_ymmh7; /* YMMH 7 */
|
|
};
|
|
|
|
#define _STRUCT_X86_AVX512_STATE32 struct i386_avx512_state
|
|
_STRUCT_X86_AVX512_STATE32
|
|
{
|
|
int fpu_reserved[2];
|
|
_STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
|
|
_STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
|
|
__uint8_t fpu_ftw; /* x87 FPU tag word */
|
|
__uint8_t fpu_rsrv1; /* reserved */
|
|
__uint16_t fpu_fop; /* x87 FPU Opcode */
|
|
__uint32_t fpu_ip; /* x87 FPU Instruction Pointer offset */
|
|
__uint16_t fpu_cs; /* x87 FPU Instruction Pointer Selector */
|
|
__uint16_t fpu_rsrv2; /* reserved */
|
|
__uint32_t fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
|
|
__uint16_t fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
|
|
__uint16_t fpu_rsrv3; /* reserved */
|
|
__uint32_t fpu_mxcsr; /* MXCSR Register state */
|
|
__uint32_t fpu_mxcsrmask; /* MXCSR mask */
|
|
_STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
|
|
_STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
|
|
_STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
|
|
_STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
|
|
_STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
|
|
_STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
|
|
_STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
|
|
_STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
|
|
_STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
|
|
_STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
|
|
_STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
|
|
_STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
|
|
_STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
|
|
_STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
|
|
_STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
|
|
_STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
|
|
char fpu_rsrv4[14*16]; /* reserved */
|
|
int fpu_reserved1;
|
|
char avx_reserved1[64];
|
|
_STRUCT_XMM_REG fpu_ymmh0; /* YMMH 0 */
|
|
_STRUCT_XMM_REG fpu_ymmh1; /* YMMH 1 */
|
|
_STRUCT_XMM_REG fpu_ymmh2; /* YMMH 2 */
|
|
_STRUCT_XMM_REG fpu_ymmh3; /* YMMH 3 */
|
|
_STRUCT_XMM_REG fpu_ymmh4; /* YMMH 4 */
|
|
_STRUCT_XMM_REG fpu_ymmh5; /* YMMH 5 */
|
|
_STRUCT_XMM_REG fpu_ymmh6; /* YMMH 6 */
|
|
_STRUCT_XMM_REG fpu_ymmh7; /* YMMH 7 */
|
|
_STRUCT_OPMASK_REG fpu_k0; /* K0 */
|
|
_STRUCT_OPMASK_REG fpu_k1; /* K1 */
|
|
_STRUCT_OPMASK_REG fpu_k2; /* K2 */
|
|
_STRUCT_OPMASK_REG fpu_k3; /* K3 */
|
|
_STRUCT_OPMASK_REG fpu_k4; /* K4 */
|
|
_STRUCT_OPMASK_REG fpu_k5; /* K5 */
|
|
_STRUCT_OPMASK_REG fpu_k6; /* K6 */
|
|
_STRUCT_OPMASK_REG fpu_k7; /* K7 */
|
|
_STRUCT_YMM_REG fpu_zmmh0; /* ZMMH 0 */
|
|
_STRUCT_YMM_REG fpu_zmmh1; /* ZMMH 1 */
|
|
_STRUCT_YMM_REG fpu_zmmh2; /* ZMMH 2 */
|
|
_STRUCT_YMM_REG fpu_zmmh3; /* ZMMH 3 */
|
|
_STRUCT_YMM_REG fpu_zmmh4; /* ZMMH 4 */
|
|
_STRUCT_YMM_REG fpu_zmmh5; /* ZMMH 5 */
|
|
_STRUCT_YMM_REG fpu_zmmh6; /* ZMMH 6 */
|
|
_STRUCT_YMM_REG fpu_zmmh7; /* ZMMH 7 */
|
|
};
|
|
|
|
#endif /* !__DARWIN_UNIX03 */
|
|
|
|
#if __DARWIN_UNIX03
|
|
#define _STRUCT_X86_EXCEPTION_STATE32 struct __darwin_i386_exception_state
|
|
_STRUCT_X86_EXCEPTION_STATE32
|
|
{
|
|
__uint16_t __trapno;
|
|
__uint16_t __cpu;
|
|
__uint32_t __err;
|
|
__uint32_t __faultvaddr;
|
|
};
|
|
#else /* !__DARWIN_UNIX03 */
|
|
#define _STRUCT_X86_EXCEPTION_STATE32 struct i386_exception_state
|
|
_STRUCT_X86_EXCEPTION_STATE32
|
|
{
|
|
__uint16_t trapno;
|
|
__uint16_t cpu;
|
|
__uint32_t err;
|
|
__uint32_t faultvaddr;
|
|
};
|
|
#endif /* !__DARWIN_UNIX03 */
|
|
|
|
#if __DARWIN_UNIX03
|
|
#define _STRUCT_X86_DEBUG_STATE32 struct __darwin_x86_debug_state32
|
|
_STRUCT_X86_DEBUG_STATE32
|
|
{
|
|
unsigned int __dr0;
|
|
unsigned int __dr1;
|
|
unsigned int __dr2;
|
|
unsigned int __dr3;
|
|
unsigned int __dr4;
|
|
unsigned int __dr5;
|
|
unsigned int __dr6;
|
|
unsigned int __dr7;
|
|
};
|
|
#else /* !__DARWIN_UNIX03 */
|
|
#define _STRUCT_X86_DEBUG_STATE32 struct x86_debug_state32
|
|
_STRUCT_X86_DEBUG_STATE32
|
|
{
|
|
unsigned int dr0;
|
|
unsigned int dr1;
|
|
unsigned int dr2;
|
|
unsigned int dr3;
|
|
unsigned int dr4;
|
|
unsigned int dr5;
|
|
unsigned int dr6;
|
|
unsigned int dr7;
|
|
};
|
|
#endif /* !__DARWIN_UNIX03 */
|
|
|
|
#define _STRUCT_X86_PAGEIN_STATE struct __x86_pagein_state
|
|
_STRUCT_X86_PAGEIN_STATE
|
|
{
|
|
int __pagein_error;
|
|
};
|
|
|
|
/*
|
|
* 64 bit versions of the above
|
|
*/
|
|
|
|
#if __DARWIN_UNIX03
|
|
#define _STRUCT_X86_THREAD_STATE64 struct __darwin_x86_thread_state64
|
|
_STRUCT_X86_THREAD_STATE64
|
|
{
|
|
__uint64_t __rax;
|
|
__uint64_t __rbx;
|
|
__uint64_t __rcx;
|
|
__uint64_t __rdx;
|
|
__uint64_t __rdi;
|
|
__uint64_t __rsi;
|
|
__uint64_t __rbp;
|
|
__uint64_t __rsp;
|
|
__uint64_t __r8;
|
|
__uint64_t __r9;
|
|
__uint64_t __r10;
|
|
__uint64_t __r11;
|
|
__uint64_t __r12;
|
|
__uint64_t __r13;
|
|
__uint64_t __r14;
|
|
__uint64_t __r15;
|
|
__uint64_t __rip;
|
|
__uint64_t __rflags;
|
|
__uint64_t __cs;
|
|
__uint64_t __fs;
|
|
__uint64_t __gs;
|
|
};
|
|
#else /* !__DARWIN_UNIX03 */
|
|
#define _STRUCT_X86_THREAD_STATE64 struct x86_thread_state64
|
|
_STRUCT_X86_THREAD_STATE64
|
|
{
|
|
__uint64_t rax;
|
|
__uint64_t rbx;
|
|
__uint64_t rcx;
|
|
__uint64_t rdx;
|
|
__uint64_t rdi;
|
|
__uint64_t rsi;
|
|
__uint64_t rbp;
|
|
__uint64_t rsp;
|
|
__uint64_t r8;
|
|
__uint64_t r9;
|
|
__uint64_t r10;
|
|
__uint64_t r11;
|
|
__uint64_t r12;
|
|
__uint64_t r13;
|
|
__uint64_t r14;
|
|
__uint64_t r15;
|
|
__uint64_t rip;
|
|
__uint64_t rflags;
|
|
__uint64_t cs;
|
|
__uint64_t fs;
|
|
__uint64_t gs;
|
|
};
|
|
#endif /* !__DARWIN_UNIX03 */
|
|
|
|
/*
|
|
* 64 bit versions of the above (complete)
|
|
*/
|
|
|
|
#if __DARWIN_UNIX03
|
|
#define _STRUCT_X86_THREAD_FULL_STATE64 struct __darwin_x86_thread_full_state64
|
|
_STRUCT_X86_THREAD_FULL_STATE64
|
|
{
|
|
_STRUCT_X86_THREAD_STATE64 __ss64;
|
|
__uint64_t __ds;
|
|
__uint64_t __es;
|
|
__uint64_t __ss;
|
|
__uint64_t __gsbase;
|
|
};
|
|
#else /* !__DARWIN_UNIX03 */
|
|
#define _STRUCT_X86_THREAD_FULL_STATE64 struct x86_thread_full_state64
|
|
_STRUCT_X86_THREAD_FULL_STATE64
|
|
{
|
|
_STRUCT_X86_THREAD_STATE64 ss64;
|
|
__uint64_t ds;
|
|
__uint64_t es;
|
|
__uint64_t ss;
|
|
__uint64_t gsbase;
|
|
};
|
|
#endif /* !__DARWIN_UNIX03 */
|
|
|
|
|
|
#if __DARWIN_UNIX03
|
|
#define _STRUCT_X86_FLOAT_STATE64 struct __darwin_x86_float_state64
|
|
_STRUCT_X86_FLOAT_STATE64
|
|
{
|
|
int __fpu_reserved[2];
|
|
_STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
|
|
_STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
|
|
__uint8_t __fpu_ftw; /* x87 FPU tag word */
|
|
__uint8_t __fpu_rsrv1; /* reserved */
|
|
__uint16_t __fpu_fop; /* x87 FPU Opcode */
|
|
|
|
/* x87 FPU Instruction Pointer */
|
|
__uint32_t __fpu_ip; /* offset */
|
|
__uint16_t __fpu_cs; /* Selector */
|
|
|
|
__uint16_t __fpu_rsrv2; /* reserved */
|
|
|
|
/* x87 FPU Instruction Operand(Data) Pointer */
|
|
__uint32_t __fpu_dp; /* offset */
|
|
__uint16_t __fpu_ds; /* Selector */
|
|
|
|
__uint16_t __fpu_rsrv3; /* reserved */
|
|
__uint32_t __fpu_mxcsr; /* MXCSR Register state */
|
|
__uint32_t __fpu_mxcsrmask; /* MXCSR mask */
|
|
_STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
|
|
_STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
|
|
_STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
|
|
_STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
|
|
_STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
|
|
_STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
|
|
_STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
|
|
_STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
|
|
_STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
|
|
_STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
|
|
_STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
|
|
_STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
|
|
_STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
|
|
_STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
|
|
_STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
|
|
_STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
|
|
_STRUCT_XMM_REG __fpu_xmm8; /* XMM 8 */
|
|
_STRUCT_XMM_REG __fpu_xmm9; /* XMM 9 */
|
|
_STRUCT_XMM_REG __fpu_xmm10; /* XMM 10 */
|
|
_STRUCT_XMM_REG __fpu_xmm11; /* XMM 11 */
|
|
_STRUCT_XMM_REG __fpu_xmm12; /* XMM 12 */
|
|
_STRUCT_XMM_REG __fpu_xmm13; /* XMM 13 */
|
|
_STRUCT_XMM_REG __fpu_xmm14; /* XMM 14 */
|
|
_STRUCT_XMM_REG __fpu_xmm15; /* XMM 15 */
|
|
char __fpu_rsrv4[6*16]; /* reserved */
|
|
int __fpu_reserved1;
|
|
};
|
|
|
|
#define _STRUCT_X86_AVX_STATE64 struct __darwin_x86_avx_state64
|
|
_STRUCT_X86_AVX_STATE64
|
|
{
|
|
int __fpu_reserved[2];
|
|
_STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
|
|
_STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
|
|
__uint8_t __fpu_ftw; /* x87 FPU tag word */
|
|
__uint8_t __fpu_rsrv1; /* reserved */
|
|
__uint16_t __fpu_fop; /* x87 FPU Opcode */
|
|
|
|
/* x87 FPU Instruction Pointer */
|
|
__uint32_t __fpu_ip; /* offset */
|
|
__uint16_t __fpu_cs; /* Selector */
|
|
|
|
__uint16_t __fpu_rsrv2; /* reserved */
|
|
|
|
/* x87 FPU Instruction Operand(Data) Pointer */
|
|
__uint32_t __fpu_dp; /* offset */
|
|
__uint16_t __fpu_ds; /* Selector */
|
|
|
|
__uint16_t __fpu_rsrv3; /* reserved */
|
|
__uint32_t __fpu_mxcsr; /* MXCSR Register state */
|
|
__uint32_t __fpu_mxcsrmask; /* MXCSR mask */
|
|
_STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
|
|
_STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
|
|
_STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
|
|
_STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
|
|
_STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
|
|
_STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
|
|
_STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
|
|
_STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
|
|
_STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
|
|
_STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
|
|
_STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
|
|
_STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
|
|
_STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
|
|
_STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
|
|
_STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
|
|
_STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
|
|
_STRUCT_XMM_REG __fpu_xmm8; /* XMM 8 */
|
|
_STRUCT_XMM_REG __fpu_xmm9; /* XMM 9 */
|
|
_STRUCT_XMM_REG __fpu_xmm10; /* XMM 10 */
|
|
_STRUCT_XMM_REG __fpu_xmm11; /* XMM 11 */
|
|
_STRUCT_XMM_REG __fpu_xmm12; /* XMM 12 */
|
|
_STRUCT_XMM_REG __fpu_xmm13; /* XMM 13 */
|
|
_STRUCT_XMM_REG __fpu_xmm14; /* XMM 14 */
|
|
_STRUCT_XMM_REG __fpu_xmm15; /* XMM 15 */
|
|
char __fpu_rsrv4[6*16]; /* reserved */
|
|
int __fpu_reserved1;
|
|
char __avx_reserved1[64];
|
|
_STRUCT_XMM_REG __fpu_ymmh0; /* YMMH 0 */
|
|
_STRUCT_XMM_REG __fpu_ymmh1; /* YMMH 1 */
|
|
_STRUCT_XMM_REG __fpu_ymmh2; /* YMMH 2 */
|
|
_STRUCT_XMM_REG __fpu_ymmh3; /* YMMH 3 */
|
|
_STRUCT_XMM_REG __fpu_ymmh4; /* YMMH 4 */
|
|
_STRUCT_XMM_REG __fpu_ymmh5; /* YMMH 5 */
|
|
_STRUCT_XMM_REG __fpu_ymmh6; /* YMMH 6 */
|
|
_STRUCT_XMM_REG __fpu_ymmh7; /* YMMH 7 */
|
|
_STRUCT_XMM_REG __fpu_ymmh8; /* YMMH 8 */
|
|
_STRUCT_XMM_REG __fpu_ymmh9; /* YMMH 9 */
|
|
_STRUCT_XMM_REG __fpu_ymmh10; /* YMMH 10 */
|
|
_STRUCT_XMM_REG __fpu_ymmh11; /* YMMH 11 */
|
|
_STRUCT_XMM_REG __fpu_ymmh12; /* YMMH 12 */
|
|
_STRUCT_XMM_REG __fpu_ymmh13; /* YMMH 13 */
|
|
_STRUCT_XMM_REG __fpu_ymmh14; /* YMMH 14 */
|
|
_STRUCT_XMM_REG __fpu_ymmh15; /* YMMH 15 */
|
|
};
|
|
|
|
#define _STRUCT_X86_AVX512_STATE64 struct __darwin_x86_avx512_state64
|
|
_STRUCT_X86_AVX512_STATE64
|
|
{
|
|
int __fpu_reserved[2];
|
|
_STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
|
|
_STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
|
|
__uint8_t __fpu_ftw; /* x87 FPU tag word */
|
|
__uint8_t __fpu_rsrv1; /* reserved */
|
|
__uint16_t __fpu_fop; /* x87 FPU Opcode */
|
|
|
|
/* x87 FPU Instruction Pointer */
|
|
__uint32_t __fpu_ip; /* offset */
|
|
__uint16_t __fpu_cs; /* Selector */
|
|
|
|
__uint16_t __fpu_rsrv2; /* reserved */
|
|
|
|
/* x87 FPU Instruction Operand(Data) Pointer */
|
|
__uint32_t __fpu_dp; /* offset */
|
|
__uint16_t __fpu_ds; /* Selector */
|
|
|
|
__uint16_t __fpu_rsrv3; /* reserved */
|
|
__uint32_t __fpu_mxcsr; /* MXCSR Register state */
|
|
__uint32_t __fpu_mxcsrmask; /* MXCSR mask */
|
|
_STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
|
|
_STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
|
|
_STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
|
|
_STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
|
|
_STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
|
|
_STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
|
|
_STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
|
|
_STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
|
|
_STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
|
|
_STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
|
|
_STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
|
|
_STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
|
|
_STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
|
|
_STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
|
|
_STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
|
|
_STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
|
|
_STRUCT_XMM_REG __fpu_xmm8; /* XMM 8 */
|
|
_STRUCT_XMM_REG __fpu_xmm9; /* XMM 9 */
|
|
_STRUCT_XMM_REG __fpu_xmm10; /* XMM 10 */
|
|
_STRUCT_XMM_REG __fpu_xmm11; /* XMM 11 */
|
|
_STRUCT_XMM_REG __fpu_xmm12; /* XMM 12 */
|
|
_STRUCT_XMM_REG __fpu_xmm13; /* XMM 13 */
|
|
_STRUCT_XMM_REG __fpu_xmm14; /* XMM 14 */
|
|
_STRUCT_XMM_REG __fpu_xmm15; /* XMM 15 */
|
|
char __fpu_rsrv4[6*16]; /* reserved */
|
|
int __fpu_reserved1;
|
|
char __avx_reserved1[64];
|
|
_STRUCT_XMM_REG __fpu_ymmh0; /* YMMH 0 */
|
|
_STRUCT_XMM_REG __fpu_ymmh1; /* YMMH 1 */
|
|
_STRUCT_XMM_REG __fpu_ymmh2; /* YMMH 2 */
|
|
_STRUCT_XMM_REG __fpu_ymmh3; /* YMMH 3 */
|
|
_STRUCT_XMM_REG __fpu_ymmh4; /* YMMH 4 */
|
|
_STRUCT_XMM_REG __fpu_ymmh5; /* YMMH 5 */
|
|
_STRUCT_XMM_REG __fpu_ymmh6; /* YMMH 6 */
|
|
_STRUCT_XMM_REG __fpu_ymmh7; /* YMMH 7 */
|
|
_STRUCT_XMM_REG __fpu_ymmh8; /* YMMH 8 */
|
|
_STRUCT_XMM_REG __fpu_ymmh9; /* YMMH 9 */
|
|
_STRUCT_XMM_REG __fpu_ymmh10; /* YMMH 10 */
|
|
_STRUCT_XMM_REG __fpu_ymmh11; /* YMMH 11 */
|
|
_STRUCT_XMM_REG __fpu_ymmh12; /* YMMH 12 */
|
|
_STRUCT_XMM_REG __fpu_ymmh13; /* YMMH 13 */
|
|
_STRUCT_XMM_REG __fpu_ymmh14; /* YMMH 14 */
|
|
_STRUCT_XMM_REG __fpu_ymmh15; /* YMMH 15 */
|
|
_STRUCT_OPMASK_REG __fpu_k0; /* K0 */
|
|
_STRUCT_OPMASK_REG __fpu_k1; /* K1 */
|
|
_STRUCT_OPMASK_REG __fpu_k2; /* K2 */
|
|
_STRUCT_OPMASK_REG __fpu_k3; /* K3 */
|
|
_STRUCT_OPMASK_REG __fpu_k4; /* K4 */
|
|
_STRUCT_OPMASK_REG __fpu_k5; /* K5 */
|
|
_STRUCT_OPMASK_REG __fpu_k6; /* K6 */
|
|
_STRUCT_OPMASK_REG __fpu_k7; /* K7 */
|
|
_STRUCT_YMM_REG __fpu_zmmh0; /* ZMMH 0 */
|
|
_STRUCT_YMM_REG __fpu_zmmh1; /* ZMMH 1 */
|
|
_STRUCT_YMM_REG __fpu_zmmh2; /* ZMMH 2 */
|
|
_STRUCT_YMM_REG __fpu_zmmh3; /* ZMMH 3 */
|
|
_STRUCT_YMM_REG __fpu_zmmh4; /* ZMMH 4 */
|
|
_STRUCT_YMM_REG __fpu_zmmh5; /* ZMMH 5 */
|
|
_STRUCT_YMM_REG __fpu_zmmh6; /* ZMMH 6 */
|
|
_STRUCT_YMM_REG __fpu_zmmh7; /* ZMMH 7 */
|
|
_STRUCT_YMM_REG __fpu_zmmh8; /* ZMMH 8 */
|
|
_STRUCT_YMM_REG __fpu_zmmh9; /* ZMMH 9 */
|
|
_STRUCT_YMM_REG __fpu_zmmh10; /* ZMMH 10 */
|
|
_STRUCT_YMM_REG __fpu_zmmh11; /* ZMMH 11 */
|
|
_STRUCT_YMM_REG __fpu_zmmh12; /* ZMMH 12 */
|
|
_STRUCT_YMM_REG __fpu_zmmh13; /* ZMMH 13 */
|
|
_STRUCT_YMM_REG __fpu_zmmh14; /* ZMMH 14 */
|
|
_STRUCT_YMM_REG __fpu_zmmh15; /* ZMMH 15 */
|
|
_STRUCT_ZMM_REG __fpu_zmm16; /* ZMM 16 */
|
|
_STRUCT_ZMM_REG __fpu_zmm17; /* ZMM 17 */
|
|
_STRUCT_ZMM_REG __fpu_zmm18; /* ZMM 18 */
|
|
_STRUCT_ZMM_REG __fpu_zmm19; /* ZMM 19 */
|
|
_STRUCT_ZMM_REG __fpu_zmm20; /* ZMM 20 */
|
|
_STRUCT_ZMM_REG __fpu_zmm21; /* ZMM 21 */
|
|
_STRUCT_ZMM_REG __fpu_zmm22; /* ZMM 22 */
|
|
_STRUCT_ZMM_REG __fpu_zmm23; /* ZMM 23 */
|
|
_STRUCT_ZMM_REG __fpu_zmm24; /* ZMM 24 */
|
|
_STRUCT_ZMM_REG __fpu_zmm25; /* ZMM 25 */
|
|
_STRUCT_ZMM_REG __fpu_zmm26; /* ZMM 26 */
|
|
_STRUCT_ZMM_REG __fpu_zmm27; /* ZMM 27 */
|
|
_STRUCT_ZMM_REG __fpu_zmm28; /* ZMM 28 */
|
|
_STRUCT_ZMM_REG __fpu_zmm29; /* ZMM 29 */
|
|
_STRUCT_ZMM_REG __fpu_zmm30; /* ZMM 30 */
|
|
_STRUCT_ZMM_REG __fpu_zmm31; /* ZMM 31 */
|
|
};
|
|
|
|
#else /* !__DARWIN_UNIX03 */
|
|
#define _STRUCT_X86_FLOAT_STATE64 struct x86_float_state64
|
|
_STRUCT_X86_FLOAT_STATE64
|
|
{
|
|
int fpu_reserved[2];
|
|
_STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
|
|
_STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
|
|
__uint8_t fpu_ftw; /* x87 FPU tag word */
|
|
__uint8_t fpu_rsrv1; /* reserved */
|
|
__uint16_t fpu_fop; /* x87 FPU Opcode */
|
|
|
|
/* x87 FPU Instruction Pointer */
|
|
__uint32_t fpu_ip; /* offset */
|
|
__uint16_t fpu_cs; /* Selector */
|
|
|
|
__uint16_t fpu_rsrv2; /* reserved */
|
|
|
|
/* x87 FPU Instruction Operand(Data) Pointer */
|
|
__uint32_t fpu_dp; /* offset */
|
|
__uint16_t fpu_ds; /* Selector */
|
|
|
|
__uint16_t fpu_rsrv3; /* reserved */
|
|
__uint32_t fpu_mxcsr; /* MXCSR Register state */
|
|
__uint32_t fpu_mxcsrmask; /* MXCSR mask */
|
|
_STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
|
|
_STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
|
|
_STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
|
|
_STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
|
|
_STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
|
|
_STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
|
|
_STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
|
|
_STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
|
|
_STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
|
|
_STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
|
|
_STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
|
|
_STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
|
|
_STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
|
|
_STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
|
|
_STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
|
|
_STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
|
|
_STRUCT_XMM_REG fpu_xmm8; /* XMM 8 */
|
|
_STRUCT_XMM_REG fpu_xmm9; /* XMM 9 */
|
|
_STRUCT_XMM_REG fpu_xmm10; /* XMM 10 */
|
|
_STRUCT_XMM_REG fpu_xmm11; /* XMM 11 */
|
|
_STRUCT_XMM_REG fpu_xmm12; /* XMM 12 */
|
|
_STRUCT_XMM_REG fpu_xmm13; /* XMM 13 */
|
|
_STRUCT_XMM_REG fpu_xmm14; /* XMM 14 */
|
|
_STRUCT_XMM_REG fpu_xmm15; /* XMM 15 */
|
|
char fpu_rsrv4[6*16]; /* reserved */
|
|
int fpu_reserved1;
|
|
};
|
|
|
|
#define _STRUCT_X86_AVX_STATE64 struct x86_avx_state64
|
|
_STRUCT_X86_AVX_STATE64
|
|
{
|
|
int fpu_reserved[2];
|
|
_STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
|
|
_STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
|
|
__uint8_t fpu_ftw; /* x87 FPU tag word */
|
|
__uint8_t fpu_rsrv1; /* reserved */
|
|
__uint16_t fpu_fop; /* x87 FPU Opcode */
|
|
|
|
/* x87 FPU Instruction Pointer */
|
|
__uint32_t fpu_ip; /* offset */
|
|
__uint16_t fpu_cs; /* Selector */
|
|
|
|
__uint16_t fpu_rsrv2; /* reserved */
|
|
|
|
/* x87 FPU Instruction Operand(Data) Pointer */
|
|
__uint32_t fpu_dp; /* offset */
|
|
__uint16_t fpu_ds; /* Selector */
|
|
|
|
__uint16_t fpu_rsrv3; /* reserved */
|
|
__uint32_t fpu_mxcsr; /* MXCSR Register state */
|
|
__uint32_t fpu_mxcsrmask; /* MXCSR mask */
|
|
_STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
|
|
_STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
|
|
_STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
|
|
_STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
|
|
_STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
|
|
_STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
|
|
_STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
|
|
_STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
|
|
_STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
|
|
_STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
|
|
_STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
|
|
_STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
|
|
_STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
|
|
_STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
|
|
_STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
|
|
_STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
|
|
_STRUCT_XMM_REG fpu_xmm8; /* XMM 8 */
|
|
_STRUCT_XMM_REG fpu_xmm9; /* XMM 9 */
|
|
_STRUCT_XMM_REG fpu_xmm10; /* XMM 10 */
|
|
_STRUCT_XMM_REG fpu_xmm11; /* XMM 11 */
|
|
_STRUCT_XMM_REG fpu_xmm12; /* XMM 12 */
|
|
_STRUCT_XMM_REG fpu_xmm13; /* XMM 13 */
|
|
_STRUCT_XMM_REG fpu_xmm14; /* XMM 14 */
|
|
_STRUCT_XMM_REG fpu_xmm15; /* XMM 15 */
|
|
char fpu_rsrv4[6*16]; /* reserved */
|
|
int fpu_reserved1;
|
|
char avx_reserved1[64];
|
|
_STRUCT_XMM_REG fpu_ymmh0; /* YMMH 0 */
|
|
_STRUCT_XMM_REG fpu_ymmh1; /* YMMH 1 */
|
|
_STRUCT_XMM_REG fpu_ymmh2; /* YMMH 2 */
|
|
_STRUCT_XMM_REG fpu_ymmh3; /* YMMH 3 */
|
|
_STRUCT_XMM_REG fpu_ymmh4; /* YMMH 4 */
|
|
_STRUCT_XMM_REG fpu_ymmh5; /* YMMH 5 */
|
|
_STRUCT_XMM_REG fpu_ymmh6; /* YMMH 6 */
|
|
_STRUCT_XMM_REG fpu_ymmh7; /* YMMH 7 */
|
|
_STRUCT_XMM_REG fpu_ymmh8; /* YMMH 8 */
|
|
_STRUCT_XMM_REG fpu_ymmh9; /* YMMH 9 */
|
|
_STRUCT_XMM_REG fpu_ymmh10; /* YMMH 10 */
|
|
_STRUCT_XMM_REG fpu_ymmh11; /* YMMH 11 */
|
|
_STRUCT_XMM_REG fpu_ymmh12; /* YMMH 12 */
|
|
_STRUCT_XMM_REG fpu_ymmh13; /* YMMH 13 */
|
|
_STRUCT_XMM_REG fpu_ymmh14; /* YMMH 14 */
|
|
_STRUCT_XMM_REG fpu_ymmh15; /* YMMH 15 */
|
|
};
|
|
|
|
#define _STRUCT_X86_AVX512_STATE64 struct x86_avx512_state64
|
|
_STRUCT_X86_AVX512_STATE64
|
|
{
|
|
int fpu_reserved[2];
|
|
_STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
|
|
_STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
|
|
__uint8_t fpu_ftw; /* x87 FPU tag word */
|
|
__uint8_t fpu_rsrv1; /* reserved */
|
|
__uint16_t fpu_fop; /* x87 FPU Opcode */
|
|
|
|
/* x87 FPU Instruction Pointer */
|
|
__uint32_t fpu_ip; /* offset */
|
|
__uint16_t fpu_cs; /* Selector */
|
|
|
|
__uint16_t fpu_rsrv2; /* reserved */
|
|
|
|
/* x87 FPU Instruction Operand(Data) Pointer */
|
|
__uint32_t fpu_dp; /* offset */
|
|
__uint16_t fpu_ds; /* Selector */
|
|
|
|
__uint16_t fpu_rsrv3; /* reserved */
|
|
__uint32_t fpu_mxcsr; /* MXCSR Register state */
|
|
__uint32_t fpu_mxcsrmask; /* MXCSR mask */
|
|
_STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
|
|
_STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
|
|
_STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
|
|
_STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
|
|
_STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
|
|
_STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
|
|
_STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
|
|
_STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
|
|
_STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
|
|
_STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
|
|
_STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
|
|
_STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
|
|
_STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
|
|
_STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
|
|
_STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
|
|
_STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
|
|
_STRUCT_XMM_REG fpu_xmm8; /* XMM 8 */
|
|
_STRUCT_XMM_REG fpu_xmm9; /* XMM 9 */
|
|
_STRUCT_XMM_REG fpu_xmm10; /* XMM 10 */
|
|
_STRUCT_XMM_REG fpu_xmm11; /* XMM 11 */
|
|
_STRUCT_XMM_REG fpu_xmm12; /* XMM 12 */
|
|
_STRUCT_XMM_REG fpu_xmm13; /* XMM 13 */
|
|
_STRUCT_XMM_REG fpu_xmm14; /* XMM 14 */
|
|
_STRUCT_XMM_REG fpu_xmm15; /* XMM 15 */
|
|
char fpu_rsrv4[6*16]; /* reserved */
|
|
int fpu_reserved1;
|
|
char avx_reserved1[64];
|
|
_STRUCT_XMM_REG fpu_ymmh0; /* YMMH 0 */
|
|
_STRUCT_XMM_REG fpu_ymmh1; /* YMMH 1 */
|
|
_STRUCT_XMM_REG fpu_ymmh2; /* YMMH 2 */
|
|
_STRUCT_XMM_REG fpu_ymmh3; /* YMMH 3 */
|
|
_STRUCT_XMM_REG fpu_ymmh4; /* YMMH 4 */
|
|
_STRUCT_XMM_REG fpu_ymmh5; /* YMMH 5 */
|
|
_STRUCT_XMM_REG fpu_ymmh6; /* YMMH 6 */
|
|
_STRUCT_XMM_REG fpu_ymmh7; /* YMMH 7 */
|
|
_STRUCT_XMM_REG fpu_ymmh8; /* YMMH 8 */
|
|
_STRUCT_XMM_REG fpu_ymmh9; /* YMMH 9 */
|
|
_STRUCT_XMM_REG fpu_ymmh10; /* YMMH 10 */
|
|
_STRUCT_XMM_REG fpu_ymmh11; /* YMMH 11 */
|
|
_STRUCT_XMM_REG fpu_ymmh12; /* YMMH 12 */
|
|
_STRUCT_XMM_REG fpu_ymmh13; /* YMMH 13 */
|
|
_STRUCT_XMM_REG fpu_ymmh14; /* YMMH 14 */
|
|
_STRUCT_XMM_REG fpu_ymmh15; /* YMMH 15 */
|
|
_STRUCT_OPMASK_REG fpu_k0; /* K0 */
|
|
_STRUCT_OPMASK_REG fpu_k1; /* K1 */
|
|
_STRUCT_OPMASK_REG fpu_k2; /* K2 */
|
|
_STRUCT_OPMASK_REG fpu_k3; /* K3 */
|
|
_STRUCT_OPMASK_REG fpu_k4; /* K4 */
|
|
_STRUCT_OPMASK_REG fpu_k5; /* K5 */
|
|
_STRUCT_OPMASK_REG fpu_k6; /* K6 */
|
|
_STRUCT_OPMASK_REG fpu_k7; /* K7 */
|
|
_STRUCT_YMM_REG fpu_zmmh0; /* ZMMH 0 */
|
|
_STRUCT_YMM_REG fpu_zmmh1; /* ZMMH 1 */
|
|
_STRUCT_YMM_REG fpu_zmmh2; /* ZMMH 2 */
|
|
_STRUCT_YMM_REG fpu_zmmh3; /* ZMMH 3 */
|
|
_STRUCT_YMM_REG fpu_zmmh4; /* ZMMH 4 */
|
|
_STRUCT_YMM_REG fpu_zmmh5; /* ZMMH 5 */
|
|
_STRUCT_YMM_REG fpu_zmmh6; /* ZMMH 6 */
|
|
_STRUCT_YMM_REG fpu_zmmh7; /* ZMMH 7 */
|
|
_STRUCT_YMM_REG fpu_zmmh8; /* ZMMH 8 */
|
|
_STRUCT_YMM_REG fpu_zmmh9; /* ZMMH 9 */
|
|
_STRUCT_YMM_REG fpu_zmmh10; /* ZMMH 10 */
|
|
_STRUCT_YMM_REG fpu_zmmh11; /* ZMMH 11 */
|
|
_STRUCT_YMM_REG fpu_zmmh12; /* ZMMH 12 */
|
|
_STRUCT_YMM_REG fpu_zmmh13; /* ZMMH 13 */
|
|
_STRUCT_YMM_REG fpu_zmmh14; /* ZMMH 14 */
|
|
_STRUCT_YMM_REG fpu_zmmh15; /* ZMMH 15 */
|
|
_STRUCT_ZMM_REG fpu_zmm16; /* ZMM 16 */
|
|
_STRUCT_ZMM_REG fpu_zmm17; /* ZMM 17 */
|
|
_STRUCT_ZMM_REG fpu_zmm18; /* ZMM 18 */
|
|
_STRUCT_ZMM_REG fpu_zmm19; /* ZMM 19 */
|
|
_STRUCT_ZMM_REG fpu_zmm20; /* ZMM 20 */
|
|
_STRUCT_ZMM_REG fpu_zmm21; /* ZMM 21 */
|
|
_STRUCT_ZMM_REG fpu_zmm22; /* ZMM 22 */
|
|
_STRUCT_ZMM_REG fpu_zmm23; /* ZMM 23 */
|
|
_STRUCT_ZMM_REG fpu_zmm24; /* ZMM 24 */
|
|
_STRUCT_ZMM_REG fpu_zmm25; /* ZMM 25 */
|
|
_STRUCT_ZMM_REG fpu_zmm26; /* ZMM 26 */
|
|
_STRUCT_ZMM_REG fpu_zmm27; /* ZMM 27 */
|
|
_STRUCT_ZMM_REG fpu_zmm28; /* ZMM 28 */
|
|
_STRUCT_ZMM_REG fpu_zmm29; /* ZMM 29 */
|
|
_STRUCT_ZMM_REG fpu_zmm30; /* ZMM 30 */
|
|
_STRUCT_ZMM_REG fpu_zmm31; /* ZMM 31 */
|
|
};
|
|
|
|
#endif /* !__DARWIN_UNIX03 */
|
|
|
|
#if __DARWIN_UNIX03
|
|
#define _STRUCT_X86_EXCEPTION_STATE64 struct __darwin_x86_exception_state64
|
|
_STRUCT_X86_EXCEPTION_STATE64
|
|
{
|
|
__uint16_t __trapno;
|
|
__uint16_t __cpu;
|
|
__uint32_t __err;
|
|
__uint64_t __faultvaddr;
|
|
};
|
|
#else /* !__DARWIN_UNIX03 */
|
|
#define _STRUCT_X86_EXCEPTION_STATE64 struct x86_exception_state64
|
|
_STRUCT_X86_EXCEPTION_STATE64
|
|
{
|
|
__uint16_t trapno;
|
|
__uint16_t cpu;
|
|
__uint32_t err;
|
|
__uint64_t faultvaddr;
|
|
};
|
|
#endif /* !__DARWIN_UNIX03 */
|
|
|
|
#if __DARWIN_UNIX03
|
|
#define _STRUCT_X86_DEBUG_STATE64 struct __darwin_x86_debug_state64
|
|
_STRUCT_X86_DEBUG_STATE64
|
|
{
|
|
__uint64_t __dr0;
|
|
__uint64_t __dr1;
|
|
__uint64_t __dr2;
|
|
__uint64_t __dr3;
|
|
__uint64_t __dr4;
|
|
__uint64_t __dr5;
|
|
__uint64_t __dr6;
|
|
__uint64_t __dr7;
|
|
};
|
|
#else /* !__DARWIN_UNIX03 */
|
|
#define _STRUCT_X86_DEBUG_STATE64 struct x86_debug_state64
|
|
_STRUCT_X86_DEBUG_STATE64
|
|
{
|
|
__uint64_t dr0;
|
|
__uint64_t dr1;
|
|
__uint64_t dr2;
|
|
__uint64_t dr3;
|
|
__uint64_t dr4;
|
|
__uint64_t dr5;
|
|
__uint64_t dr6;
|
|
__uint64_t dr7;
|
|
};
|
|
#endif /* !__DARWIN_UNIX03 */
|
|
|
|
#if __DARWIN_UNIX03
|
|
#define _STRUCT_X86_CPMU_STATE64 struct __darwin_x86_cpmu_state64
|
|
_STRUCT_X86_CPMU_STATE64
|
|
{
|
|
__uint64_t __ctrs[16];
|
|
};
|
|
#else /* __DARWIN_UNIX03 */
|
|
#define _STRUCT_X86_CPMU_STATE64 struct x86_cpmu_state64
|
|
_STRUCT_X86_CPMU_STATE64
|
|
{
|
|
__uint64_t ctrs[16];
|
|
};
|
|
#endif /* !__DARWIN_UNIX03 */
|
|
|
|
#endif /* _MACH_I386__STRUCTS_H_ */ |