208 lines
8.1 KiB
Zig
208 lines
8.1 KiB
Zig
//! This file contains the functionality for emitting RISC-V MIR as machine code
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bin_file: *link.File,
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lower: Lower,
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debug_output: DebugInfoOutput,
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code: *std.ArrayList(u8),
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prev_di_line: u32,
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prev_di_column: u32,
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/// Relative to the beginning of `code`.
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prev_di_pc: usize,
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code_offset_mapping: std.AutoHashMapUnmanaged(Mir.Inst.Index, usize) = .{},
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relocs: std.ArrayListUnmanaged(Reloc) = .{},
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pub const Error = Lower.Error || error{
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EmitFail,
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};
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pub fn emitMir(emit: *Emit) Error!void {
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log.debug("mir instruction len: {}", .{emit.lower.mir.instructions.len});
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for (0..emit.lower.mir.instructions.len) |mir_i| {
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const mir_index: Mir.Inst.Index = @intCast(mir_i);
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try emit.code_offset_mapping.putNoClobber(
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emit.lower.allocator,
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mir_index,
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@intCast(emit.code.items.len),
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);
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const lowered = try emit.lower.lowerMir(mir_index, .{ .allow_frame_locs = true });
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var lowered_relocs = lowered.relocs;
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for (lowered.insts, 0..) |lowered_inst, lowered_index| {
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const start_offset: u32 = @intCast(emit.code.items.len);
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try lowered_inst.encode(emit.code.writer());
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while (lowered_relocs.len > 0 and
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lowered_relocs[0].lowered_inst_index == lowered_index) : ({
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lowered_relocs = lowered_relocs[1..];
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}) switch (lowered_relocs[0].target) {
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.inst => |target| try emit.relocs.append(emit.lower.allocator, .{
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.source = start_offset,
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.target = target,
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.offset = 0,
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.fmt = std.meta.activeTag(lowered_inst),
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}),
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.load_symbol_reloc => |symbol| {
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const is_obj_or_static_lib = switch (emit.lower.output_mode) {
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.Exe => false,
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.Obj => true,
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.Lib => emit.lower.link_mode == .static,
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};
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const elf_file = emit.bin_file.cast(link.File.Elf).?;
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const atom_ptr = elf_file.symbol(symbol.atom_index).atom(elf_file).?;
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const sym_index = elf_file.zigObjectPtr().?.symbol(symbol.sym_index);
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const sym = elf_file.symbol(sym_index);
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var hi_r_type: u32 = @intFromEnum(std.elf.R_RISCV.HI20);
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var lo_r_type: u32 = @intFromEnum(std.elf.R_RISCV.LO12_I);
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if (sym.flags.needs_zig_got and !is_obj_or_static_lib) {
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_ = try sym.getOrCreateZigGotEntry(sym_index, elf_file);
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hi_r_type = Elf.R_ZIG_GOT_HI20;
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lo_r_type = Elf.R_ZIG_GOT_LO12;
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}
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try atom_ptr.addReloc(elf_file, .{
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.r_offset = start_offset,
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.r_info = (@as(u64, @intCast(symbol.sym_index)) << 32) | hi_r_type,
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.r_addend = 0,
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});
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try atom_ptr.addReloc(elf_file, .{
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.r_offset = start_offset + 4,
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.r_info = (@as(u64, @intCast(symbol.sym_index)) << 32) | lo_r_type,
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.r_addend = 0,
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});
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},
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.call_extern_fn_reloc => |symbol| {
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const elf_file = emit.bin_file.cast(link.File.Elf).?;
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const atom_ptr = elf_file.symbol(symbol.atom_index).atom(elf_file).?;
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const r_type: u32 = @intFromEnum(std.elf.R_RISCV.CALL_PLT);
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try atom_ptr.addReloc(elf_file, .{
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.r_offset = start_offset,
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.r_info = (@as(u64, @intCast(symbol.sym_index)) << 32) | r_type,
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.r_addend = 0,
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});
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},
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};
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}
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std.debug.assert(lowered_relocs.len == 0);
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if (lowered.insts.len == 0) {
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const mir_inst = emit.lower.mir.instructions.get(mir_index);
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switch (mir_inst.tag) {
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else => unreachable,
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.pseudo_dbg_prologue_end => {
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switch (emit.debug_output) {
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.dwarf => |dw| {
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try dw.setPrologueEnd();
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log.debug("mirDbgPrologueEnd (line={d}, col={d})", .{
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emit.prev_di_line, emit.prev_di_column,
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});
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try emit.dbgAdvancePCAndLine(emit.prev_di_line, emit.prev_di_column);
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},
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.plan9 => {},
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.none => {},
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}
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},
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.pseudo_dbg_line_column => try emit.dbgAdvancePCAndLine(
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mir_inst.data.pseudo_dbg_line_column.line,
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mir_inst.data.pseudo_dbg_line_column.column,
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),
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.pseudo_dbg_epilogue_begin => {
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switch (emit.debug_output) {
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.dwarf => |dw| {
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try dw.setEpilogueBegin();
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log.debug("mirDbgEpilogueBegin (line={d}, col={d})", .{
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emit.prev_di_line, emit.prev_di_column,
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});
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try emit.dbgAdvancePCAndLine(emit.prev_di_line, emit.prev_di_column);
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},
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.plan9 => {},
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.none => {},
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}
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},
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.pseudo_dead => {},
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}
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}
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}
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try emit.fixupRelocs();
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}
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pub fn deinit(emit: *Emit) void {
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emit.relocs.deinit(emit.lower.allocator);
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emit.code_offset_mapping.deinit(emit.lower.allocator);
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emit.* = undefined;
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}
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const Reloc = struct {
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/// Offset of the instruction.
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source: usize,
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/// Target of the relocation.
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target: Mir.Inst.Index,
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/// Offset of the relocation within the instruction.
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offset: u32,
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/// Format of the instruction, used to determine how to modify it.
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fmt: encoding.Lir.Format,
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};
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fn fixupRelocs(emit: *Emit) Error!void {
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for (emit.relocs.items) |reloc| {
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log.debug("target inst: {}", .{emit.lower.mir.instructions.get(reloc.target)});
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const target = emit.code_offset_mapping.get(reloc.target) orelse
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return emit.fail("relocation target not found!", .{});
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const disp = @as(i32, @intCast(target)) - @as(i32, @intCast(reloc.source));
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const code: *[4]u8 = emit.code.items[reloc.source + reloc.offset ..][0..4];
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switch (reloc.fmt) {
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.J => riscv_util.writeInstJ(code, @bitCast(disp)),
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.B => riscv_util.writeInstB(code, @bitCast(disp)),
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else => return emit.fail("tried to reloc format type {s}", .{@tagName(reloc.fmt)}),
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}
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}
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}
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fn dbgAdvancePCAndLine(emit: *Emit, line: u32, column: u32) Error!void {
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const delta_line = @as(i33, line) - @as(i33, emit.prev_di_line);
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const delta_pc: usize = emit.code.items.len - emit.prev_di_pc;
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log.debug(" (advance pc={d} and line={d})", .{ delta_pc, delta_line });
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switch (emit.debug_output) {
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.dwarf => |dw| {
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if (column != emit.prev_di_column) try dw.setColumn(column);
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if (delta_line == 0) return; // TODO: fix these edge cases.
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try dw.advancePCAndLine(delta_line, delta_pc);
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emit.prev_di_line = line;
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emit.prev_di_column = column;
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emit.prev_di_pc = emit.code.items.len;
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},
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.plan9 => {},
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.none => {},
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}
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}
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fn fail(emit: *Emit, comptime format: []const u8, args: anytype) Error {
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return switch (emit.lower.fail(format, args)) {
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error.LowerFail => error.EmitFail,
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else => |e| e,
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};
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}
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const link = @import("../../link.zig");
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const log = std.log.scoped(.emit);
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const mem = std.mem;
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const std = @import("std");
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const DebugInfoOutput = @import("../../codegen.zig").DebugInfoOutput;
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const Emit = @This();
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const Lower = @import("Lower.zig");
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const Mir = @import("Mir.zig");
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const riscv_util = @import("../../link/riscv.zig");
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const Elf = @import("../../link/Elf.zig");
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const encoding = @import("encoding.zig");
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