1053 lines
34 KiB
Zig
1053 lines
34 KiB
Zig
const Encoding = @This();
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const std = @import("std");
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const assert = std.debug.assert;
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const math = std.math;
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const bits = @import("bits.zig");
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const encoder = @import("encoder.zig");
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const Instruction = encoder.Instruction;
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const Operand = Instruction.Operand;
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const Prefix = Instruction.Prefix;
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const Register = bits.Register;
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const Rex = encoder.Rex;
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const LegacyPrefixes = encoder.LegacyPrefixes;
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mnemonic: Mnemonic,
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data: Data,
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const Data = struct {
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op_en: OpEn,
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ops: [4]Op,
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opc_len: u3,
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opc: [7]u8,
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modrm_ext: u3,
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mode: Mode,
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feature: Feature,
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};
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pub fn findByMnemonic(
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prefix: Instruction.Prefix,
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mnemonic: Mnemonic,
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ops: []const Instruction.Operand,
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target: *const std.Target,
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) !?Encoding {
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var input_ops: [4]Op = @splat(.none);
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for (input_ops[0..ops.len], ops) |*input_op, op| input_op.* = Op.fromOperand(op, target);
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const rex_required = for (ops) |op| switch (op) {
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.reg => |r| switch (r) {
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.spl, .bpl, .sil, .dil => break true,
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else => {},
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},
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else => {},
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} else false;
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const rex_invalid = for (ops) |op| switch (op) {
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.reg => |r| switch (r) {
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.ah, .bh, .ch, .dh => break true,
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else => {},
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},
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else => {},
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} else false;
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const rex_extended = for (ops) |op| {
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if (op.isBaseExtended() or op.isIndexExtended()) break true;
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} else false;
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if ((rex_required or rex_extended) and rex_invalid) return error.CannotEncode;
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var shortest_enc: ?Encoding = null;
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var shortest_len: ?usize = null;
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next: for (mnemonic_to_encodings_map[@intFromEnum(mnemonic)]) |data| {
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if (!switch (data.feature) {
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.none => true,
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.@"32bit" => switch (target.cpu.arch) {
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else => unreachable,
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.x86 => true,
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.x86_64 => false,
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},
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.@"64bit" => switch (target.cpu.arch) {
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else => unreachable,
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.x86 => false,
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.x86_64 => true,
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},
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inline .@"invpcid 32bit", .@"rdpid 32bit" => |tag| switch (target.cpu.arch) {
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else => unreachable,
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.x86 => std.Target.x86.featureSetHas(
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target.cpu.features,
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@field(std.Target.x86.Feature, @tagName(tag)[0 .. @tagName(tag).len - " 32bit".len]),
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),
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.x86_64 => false,
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},
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inline .@"invpcid 64bit", .@"rdpid 64bit", .@"prefetchi 64bit" => |tag| switch (target.cpu.arch) {
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else => unreachable,
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.x86 => false,
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.x86_64 => std.Target.x86.featureSetHas(
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target.cpu.features,
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@field(std.Target.x86.Feature, @tagName(tag)[0 .. @tagName(tag).len - " 64bit".len]),
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),
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},
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.prefetch => std.Target.x86.featureSetHasAny(target.cpu.features, .{ .sse, .prfchw, .prefetchi, .prefetchwt1 }),
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inline else => |tag| has_features: {
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comptime var feature_it = std.mem.splitScalar(u8, @tagName(tag), ' ');
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comptime var features: []const std.Target.x86.Feature = &.{};
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inline while (comptime feature_it.next()) |feature| features = features ++ .{@field(std.Target.x86.Feature, feature)};
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break :has_features std.Target.x86.featureSetHasAll(target.cpu.features, features[0..].*);
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},
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}) continue;
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switch (data.mode) {
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.none, .short => if (rex_required) continue,
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.rex, .rex_short => if (!rex_required) continue,
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else => {},
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}
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for (input_ops, data.ops) |input_op, data_op| if (!input_op.isSubset(data_op)) continue :next;
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const enc: Encoding = .{ .mnemonic = mnemonic, .data = data };
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if (shortest_enc) |previous_shortest_enc| {
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const len = estimateInstructionLength(prefix, enc, ops);
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const previous_shortest_len = shortest_len orelse
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estimateInstructionLength(prefix, previous_shortest_enc, ops);
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if (len < previous_shortest_len) {
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shortest_enc = enc;
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shortest_len = len;
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} else shortest_len = previous_shortest_len;
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} else shortest_enc = enc;
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}
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return shortest_enc;
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}
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/// Returns first matching encoding by opcode.
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pub fn findByOpcode(opc: []const u8, prefixes: struct {
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legacy: LegacyPrefixes,
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rex: Rex,
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}, modrm_ext: ?u3) ?Encoding {
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for (mnemonic_to_encodings_map, 0..) |encs, mnemonic_int| for (encs) |data| {
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const enc = Encoding{ .mnemonic = @as(Mnemonic, @enumFromInt(mnemonic_int)), .data = data };
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if (modrm_ext) |ext| if (ext != data.modrm_ext) continue;
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if (!std.mem.eql(u8, opc, enc.opcode())) continue;
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if (prefixes.rex.w) {
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if (!data.mode.isLong()) continue;
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} else if (prefixes.rex.present and !prefixes.rex.isSet()) {
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if (!data.mode.isRex()) continue;
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} else if (prefixes.legacy.prefix_66) {
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if (!data.mode.isShort()) continue;
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} else {
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if (data.mode.isShort()) continue;
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}
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return enc;
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};
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return null;
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}
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pub fn opcode(encoding: *const Encoding) []const u8 {
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return encoding.data.opc[0..encoding.data.opc_len];
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}
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pub fn mandatoryPrefix(encoding: *const Encoding) ?u8 {
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const prefix = encoding.data.opc[0];
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return switch (prefix) {
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0x66, 0xf2, 0xf3 => prefix,
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else => null,
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};
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}
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pub fn modRmExt(encoding: Encoding) u3 {
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return switch (encoding.data.op_en) {
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.ia, .m, .mi, .m1, .mc, .vm, .vmi => encoding.data.modrm_ext,
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else => unreachable,
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};
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}
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pub fn format(
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encoding: Encoding,
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comptime fmt: []const u8,
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options: std.fmt.FormatOptions,
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writer: anytype,
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) !void {
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_ = options;
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_ = fmt;
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var opc = encoding.opcode();
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if (encoding.data.mode.isVex()) {
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try writer.writeAll("VEX.");
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try writer.writeAll(switch (encoding.data.mode) {
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.vex_128_w0, .vex_128_w1, .vex_128_wig => "128",
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.vex_256_w0, .vex_256_w1, .vex_256_wig => "256",
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.vex_lig_w0, .vex_lig_w1, .vex_lig_wig => "LIG",
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.vex_lz_w0, .vex_lz_w1, .vex_lz_wig => "LZ",
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else => unreachable,
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});
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switch (opc[0]) {
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else => {},
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0x66, 0xf3, 0xf2 => {
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try writer.print(".{X:0>2}", .{opc[0]});
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opc = opc[1..];
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},
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}
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try writer.print(".{}", .{std.fmt.fmtSliceHexUpper(opc[0 .. opc.len - 1])});
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opc = opc[opc.len - 1 ..];
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try writer.writeAll(".W");
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try writer.writeAll(switch (encoding.data.mode) {
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.vex_128_w0, .vex_256_w0, .vex_lig_w0, .vex_lz_w0 => "0",
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.vex_128_w1, .vex_256_w1, .vex_lig_w1, .vex_lz_w1 => "1",
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.vex_128_wig, .vex_256_wig, .vex_lig_wig, .vex_lz_wig => "IG",
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else => unreachable,
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});
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try writer.writeByte(' ');
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} else if (encoding.data.mode.isLong()) try writer.writeAll("REX.W + ");
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for (opc) |byte| try writer.print("{x:0>2} ", .{byte});
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switch (encoding.data.op_en) {
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.z, .fd, .td, .i, .zi, .ii, .d => {},
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.o, .zo, .oz, .oi => {
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const op = switch (encoding.data.op_en) {
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.o, .oz, .oi => encoding.data.ops[0],
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.zo => encoding.data.ops[1],
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else => unreachable,
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};
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const tag = switch (op) {
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.r8 => "rb",
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.r16 => "rw",
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.r32 => "rd",
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.r64 => "rd",
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else => unreachable,
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};
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try writer.print("+{s} ", .{tag});
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},
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.ia, .m, .mi, .m1, .mc, .vm, .vmi => try writer.print("/{d} ", .{encoding.modRmExt()}),
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.mr, .rm, .rmi, .mri, .mrc, .rm0, .rvm, .rvmr, .rvmi, .mvr, .rmv => try writer.writeAll("/r "),
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}
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switch (encoding.data.op_en) {
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.i, .d, .zi, .ii, .ia, .oi, .mi, .rmi, .mri, .vmi, .rvmi => for (0..2) |i| {
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const op = switch (i) {
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0 => switch (encoding.data.op_en) {
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.i, .ii, .ia, .d => encoding.data.ops[0],
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.zi, .oi, .mi => encoding.data.ops[1],
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.rmi, .mri, .vmi => encoding.data.ops[2],
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.rvmi => encoding.data.ops[3],
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else => unreachable,
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},
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1 => switch (encoding.data.op_en) {
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.ii => encoding.data.ops[1],
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else => break,
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},
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else => unreachable,
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};
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const tag = switch (op) {
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.imm8, .imm8s => "ib",
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.imm16, .imm16s => "iw",
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.imm32, .imm32s => "id",
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.imm64 => "io",
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.rel8 => "cb",
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.rel16 => "cw",
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.rel32 => "cd",
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else => unreachable,
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};
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try writer.print("{s} ", .{tag});
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},
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.rvmr => try writer.writeAll("/is4 "),
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.z, .fd, .td, .o, .zo, .oz, .m, .m1, .mc, .mr, .rm, .mrc, .rm0, .vm, .rvm, .mvr, .rmv => {},
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}
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try writer.print("{s} ", .{@tagName(encoding.mnemonic)});
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for (encoding.data.ops) |op| switch (op) {
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.none => break,
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else => try writer.print("{s} ", .{@tagName(op)}),
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};
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const op_en = switch (encoding.data.op_en) {
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.zi => .i,
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else => |op_en| op_en,
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};
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try writer.print("{s}", .{@tagName(op_en)});
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}
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pub const Mnemonic = enum {
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// Directives
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@".cfi_def_cfa",
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@".cfi_def_cfa_register",
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@".cfi_def_cfa_offset",
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@".cfi_adjust_cfa_offset",
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@".cfi_offset",
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@".cfi_val_offset",
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@".cfi_rel_offset",
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@".cfi_register",
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@".cfi_restore",
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@".cfi_undefined",
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@".cfi_same_value",
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@".cfi_remember_state",
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@".cfi_restore_state",
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@".cfi_escape",
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// zig fmt: off
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// General-purpose
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aaa, aad, aam, aas, adc, add, @"and", arpl,
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bound, bsf, bsr, bswap, bt, btc, btr, bts,
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call, cbw, cdq, cdqe,
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clac, clc, cld, cldemote, clflush, clflushopt, cli, clts, clui, clrssbsy, clwb, cmc,
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cmova, cmovae, cmovb, cmovbe, cmovc, cmove, cmovg, cmovge, cmovl, cmovle, cmovna,
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cmovnae, cmovnb, cmovnbe, cmovnc, cmovne, cmovng, cmovnge, cmovnl, cmovnle, cmovno,
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cmovnp, cmovns, cmovnz, cmovo, cmovp, cmovpe, cmovpo, cmovs, cmovz,
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cmp, cmps, cmpsb, cmpsd, cmpsq, cmpsw, cmpxchg, cmpxchg8b, cmpxchg16b,
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cpuid, cqo, cwd, cwde,
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daa, das, dec, div,
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endbr32, endbr64, enqcmd, enqcmds, enter,
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hlt, hreset,
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idiv, imul, in, inc, incsspd, incsspq, ins, insb, insd, insw,
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int, int1, int3, into, invd, invlpg, invpcid, iret, iretd, iretq, iretw,
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ja, jae, jb, jbe, jc, jcxz, je, jecxz, jg, jge, jl, jle, jmp, jna, jnae, jnb, jnbe,
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jnc, jne, jng, jnge, jnl, jnle, jno, jnp, jns, jnz, jo, jp, jpe, jpo, jrcxz, js, jz,
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lahf, lar, lea, leave, lfence, lgdt, lidt, lldt, lmsw, loop, loope, loopne,
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lods, lodsb, lodsd, lodsq, lodsw,
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lsl, ltr,
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mfence, mov, movbe,
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movs, movsb, movsd, movsq, movsw,
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movsx, movsxd, movzx, mul,
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neg, nop, not,
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@"or", out, outs, outsb, outsd, outsw,
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pause, pop, popf, popfd, popfq, push, pushfq,
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rcl, rcr,
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rdfsbase, rdgsbase, rdmsr, rdpid, rdpkru, rdpmc, rdrand, rdseed, rdssd, rdssq, rdtsc, rdtscp,
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ret, rol, ror, rsm,
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sahf, sal, sar, sbb,
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scas, scasb, scasd, scasq, scasw,
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senduipi, serialize,
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shl, shld, shr, shrd,
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stac, stc, std, sti, str, stui,
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sub, swapgs, syscall, sysenter, sysexit, sysret,
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seta, setae, setb, setbe, setc, sete, setg, setge, setl, setle, setna, setnae,
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setnb, setnbe, setnc, setne, setng, setnge, setnl, setnle, setno, setnp, setns,
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setnz, seto, setp, setpe, setpo, sets, setz,
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sfence, sidt, sldt, smsw,
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stos, stosb, stosd, stosq, stosw,
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@"test", testui, tpause,
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ud0, ud1, ud2, uiret, umonitor, umwait,
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verr, verw, wrfsbase, wrgsbase, wrmsr, wrpkru, wrssd, wrssq, wrussd, wrussq,
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xadd, xchg, xgetbv, xlat, xlatb, xor,
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// X87
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f2xm1, fabs, fadd, faddp, fbld, fbstp, fchs, fclex,
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fcmovb, fcmovbe, fcmove, fcmovnb, fcmovnbe, fcmovne, fcmovnu, fcmovu,
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fcom, fcomi, fcomip, fcomp, fcompp, fcos,
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fdecstp, fdiv, fdivp, fdivr, fdivrp, ffree,
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fiadd, ficom, ficomp, fidiv, fidivr, fild, fimul, fincstp, finit,
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fist, fistp, fisttp, fisub, fisubr,
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fld, fld1, fldcw, fldenv, fldl2e, fldl2t, fldlg2, fldln2, fldpi, fldz,
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fmul, fmulp,
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fnclex, fninit, fnop, fnsave, fnstcw, fnstenv, fnstsw,
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fpatan, fprem, fprem1, fptan, frndint, frstor,
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fsave, fscale, fsin, fsincos, fsqrt,
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fst, fstcw, fstenv, fstp, fstsw,
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fsub, fsubp, fsubr, fsubrp,
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ftst, fucom, fucomi, fucomip, fucomp, fucompp,
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fwait, fxam, fxch, fxtract, fyl2x, fyl2xp1, wait,
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// MMX
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emms, movd, movq,
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packssdw, packsswb, packuswb,
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paddb, paddd, paddq, paddsb, paddsw, paddusb, paddusw, paddw,
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pand, pandn, por, pxor,
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pcmpeqb, pcmpeqd, pcmpeqw,
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pcmpgtb, pcmpgtd, pcmpgtw,
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pmulhw, pmullw,
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pslld, psllq, psllw,
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psrad, psraw,
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psrld, psrlq, psrlw,
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psubb, psubd, psubq, psubsb, psubsw, psubusb, psubusw, psubw,
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// SSE
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addps, addss,
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andps,
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andnps,
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cmpps, cmpss, comiss,
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cvtpi2ps, cvtps2pi, cvtsi2ss, cvtss2si, cvttps2pi, cvttss2si,
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divps, divss,
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fxrstor, fxrstor64, fxsave, fxsave64,
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ldmxcsr,
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maxps, maxss,
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minps, minss,
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movaps, movhlps, movhps, movlhps, movlps,
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movmskps,
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movss, movups,
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mulps, mulss,
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orps,
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pextrw, pinsrw,
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pmaxsw, pmaxub, pminsw, pminub, pmovmskb,
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prefetchit0, prefetchit1, prefetchnta, prefetcht0, prefetcht1, prefetcht2, prefetchw, prefetchwt1,
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shufps,
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sqrtps, sqrtss,
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stmxcsr,
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subps, subss,
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ucomiss, unpckhps, unpcklps,
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xorps,
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// SSE2
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addpd, addsd,
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andpd,
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andnpd,
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cmppd, //cmpsd,
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comisd,
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cvtdq2pd, cvtdq2ps, cvtpd2dq, cvtpd2pi, cvtpd2ps, cvtpi2pd,
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cvtps2dq, cvtps2pd, cvtsd2si, cvtsd2ss, cvtsi2sd, cvtss2sd,
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cvttpd2dq, cvttpd2pi, cvttps2dq, cvttsd2si,
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divpd, divsd,
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gf2p8affineinvqb, gf2p8affineqb, gf2p8mulb,
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maxpd, maxsd,
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minpd, minsd,
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movapd,
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movdqa, movdqu,
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movhpd, movlpd,
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movmskpd,
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//movsd,
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movupd,
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mulpd, mulsd,
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orpd,
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pshufd, pshufhw, pshuflw,
|
|
pslldq, psrldq,
|
|
punpckhbw, punpckhdq, punpckhqdq, punpckhwd,
|
|
punpcklbw, punpckldq, punpcklqdq, punpcklwd,
|
|
shufpd,
|
|
sqrtpd, sqrtsd,
|
|
subpd, subsd,
|
|
ucomisd, unpckhpd, unpcklpd,
|
|
xorpd,
|
|
// SSE3
|
|
addsubpd, addsubps, haddpd, haddps, lddqu, movddup, movshdup, movsldup,
|
|
// SSSE3
|
|
pabsb, pabsd, pabsw, palignr, pshufb,
|
|
// SSE4.1
|
|
blendpd, blendps, blendvpd, blendvps,
|
|
dppd, dpps,
|
|
extractps,
|
|
insertps,
|
|
packusdw,
|
|
pblendvb, pblendw,
|
|
pcmpeqq,
|
|
pextrb, pextrd, pextrq,
|
|
pinsrb, pinsrd, pinsrq,
|
|
pmaxsb, pmaxsd, pmaxud, pmaxuw, pminsb, pminsd, pminud, pminuw,
|
|
pmovsxbd, pmovsxbq, pmovsxbw, pmovsxdq, pmovsxwd, pmovsxwq,
|
|
pmovzxbd, pmovzxbq, pmovzxbw, pmovzxdq, pmovzxwd, pmovzxwq,
|
|
pmulld,
|
|
ptest,
|
|
roundpd, roundps, roundsd, roundss,
|
|
// SSE4.2
|
|
crc32, pcmpgtq,
|
|
// ABM
|
|
lzcnt, popcnt,
|
|
// PCLMUL
|
|
pclmulqdq,
|
|
// AES
|
|
aesdec, aesdeclast, aesenc, aesenclast, aesimc, aeskeygenassist,
|
|
// SHA
|
|
sha1rnds4, sha1nexte, sha1msg1, sha1msg2, sha256msg1, sha256msg2, sha256rnds2,
|
|
// AVX
|
|
vaddpd, vaddps, vaddsd, vaddss, vaddsubpd, vaddsubps,
|
|
vaesdec, vaesdeclast, vaesenc, vaesenclast, vaesimc, vaeskeygenassist,
|
|
vandnpd, vandnps, vandpd, vandps,
|
|
vblendpd, vblendps, vblendvpd, vblendvps,
|
|
vbroadcastf128, vbroadcastsd, vbroadcastss,
|
|
vcmppd, vcmpps, vcmpsd, vcmpss, vcomisd, vcomiss,
|
|
vcvtdq2pd, vcvtdq2ps, vcvtpd2dq, vcvtpd2ps,
|
|
vcvtps2dq, vcvtps2pd, vcvtsd2si, vcvtsd2ss,
|
|
vcvtsi2sd, vcvtsi2ss, vcvtss2sd, vcvtss2si,
|
|
vcvttpd2dq, vcvttps2dq, vcvttsd2si, vcvttss2si,
|
|
vdivpd, vdivps, vdivsd, vdivss,
|
|
vdppd, vdpps,
|
|
vextractf128, vextractps,
|
|
vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb,
|
|
vhaddpd, vhaddps,
|
|
vinsertf128, vinsertps,
|
|
vlddqu, vldmxcsr,
|
|
vmaskmovpd, vmaskmovps,
|
|
vmaxpd, vmaxps, vmaxsd, vmaxss,
|
|
vminpd, vminps, vminsd, vminss,
|
|
vmovapd, vmovaps,
|
|
vmovd,
|
|
vmovddup,
|
|
vmovdqa, vmovdqu,
|
|
vmovhlps, vmovhpd, vmovhps, vmovlhps, vmovlpd, vmovlps,
|
|
vmovmskpd, vmovmskps,
|
|
vmovq,
|
|
vmovsd,
|
|
vmovshdup, vmovsldup,
|
|
vmovss,
|
|
vmovupd, vmovups,
|
|
vmulpd, vmulps, vmulsd, vmulss,
|
|
vorpd, vorps,
|
|
vpabsb, vpabsd, vpabsw,
|
|
vpackssdw, vpacksswb, vpackusdw, vpackuswb,
|
|
vpaddb, vpaddd, vpaddq, vpaddsb, vpaddsw, vpaddusb, vpaddusw, vpaddw,
|
|
vpalignr, vpand, vpandn,
|
|
vpblendvb, vpblendw, vpclmulqdq,
|
|
vpcmpeqb, vpcmpeqd, vpcmpeqq, vpcmpeqw,
|
|
vpcmpgtb, vpcmpgtd, vpcmpgtq, vpcmpgtw,
|
|
vperm2f128, vpermilpd, vpermilps,
|
|
vpextrb, vpextrd, vpextrq, vpextrw,
|
|
vpinsrb, vpinsrd, vpinsrq, vpinsrw,
|
|
vpmaxsb, vpmaxsd, vpmaxsw, vpmaxub, vpmaxud, vpmaxuw,
|
|
vpminsb, vpminsd, vpminsw, vpminub, vpminud, vpminuw,
|
|
vpmovmskb,
|
|
vpmovsxbd, vpmovsxbq, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovsxwq,
|
|
vpmovzxbd, vpmovzxbq, vpmovzxbw, vpmovzxdq, vpmovzxwd, vpmovzxwq,
|
|
vpmulhw, vpmulld, vpmullw,
|
|
vpor,
|
|
vpshufb, vpshufd, vpshufhw, vpshuflw,
|
|
vpslld, vpslldq, vpsllq, vpsllw,
|
|
vpsrad, vpsraq, vpsraw,
|
|
vpsrld, vpsrldq, vpsrlq, vpsrlw,
|
|
vpsubb, vpsubd, vpsubq, vpsubsb, vpsubsw, vpsubusb, vpsubusw, vpsubw,
|
|
vptest,
|
|
vpunpckhbw, vpunpckhdq, vpunpckhqdq, vpunpckhwd,
|
|
vpunpcklbw, vpunpckldq, vpunpcklqdq, vpunpcklwd,
|
|
vpxor,
|
|
vroundpd, vroundps, vroundsd, vroundss,
|
|
vshufpd, vshufps,
|
|
vsqrtpd, vsqrtps, vsqrtsd, vsqrtss,
|
|
vstmxcsr,
|
|
vsubpd, vsubps, vsubsd, vsubss,
|
|
vtestpd, vtestps,
|
|
vucomisd, vucomiss, vunpckhpd, vunpckhps, vunpcklpd, vunpcklps,
|
|
vxorpd, vxorps,
|
|
// BMI
|
|
andn, bextr, blsi, blsmsk, blsr, tzcnt,
|
|
// BMI2
|
|
bzhi, mulx, pdep, pext, rorx, sarx, shlx, shrx,
|
|
// F16C
|
|
vcvtph2ps, vcvtps2ph,
|
|
// FMA
|
|
vfmadd132pd, vfmadd213pd, vfmadd231pd,
|
|
vfmadd132ps, vfmadd213ps, vfmadd231ps,
|
|
vfmadd132sd, vfmadd213sd, vfmadd231sd,
|
|
vfmadd132ss, vfmadd213ss, vfmadd231ss,
|
|
// AVX2
|
|
vbroadcasti128, vpbroadcastb, vpbroadcastd, vpbroadcastq, vpbroadcastw,
|
|
vextracti128, vinserti128, vpblendd,
|
|
vperm2i128, vpermd, vpermpd, vpermps, vpermq,
|
|
vpmaskmovd, vpmaskmovq,
|
|
vpsllvd, vpsllvq, vpsravd, vpsrlvd, vpsrlvq,
|
|
// ADX
|
|
adcx, adox,
|
|
// AESKLE
|
|
aesdec128kl, aesdec256kl, aesenc128kl, aesenc256kl, encodekey128, encodekey256, loadiwkey,
|
|
// AESKLEWIDE_KL
|
|
aesdecwide128kl, aesdecwide256kl, aesencwide128kl, aesencwide256kl,
|
|
// zig fmt: on
|
|
};
|
|
|
|
pub const OpEn = enum {
|
|
// zig fmt: off
|
|
z,
|
|
o, zo, oz, oi,
|
|
i, zi, ii, ia,
|
|
d, m,
|
|
fd, td,
|
|
m1, mc, mi, mr, rm,
|
|
rmi, mri, mrc,
|
|
rm0, vm, vmi, rvm, rvmr, rvmi, mvr, rmv,
|
|
// zig fmt: on
|
|
};
|
|
|
|
pub const Op = enum {
|
|
// zig fmt: off
|
|
none,
|
|
unity,
|
|
imm8, imm16, imm32, imm64,
|
|
imm8s, imm16s, imm32s,
|
|
al, ax, eax, rax,
|
|
cl, dx,
|
|
rip, eip, ip,
|
|
r8, r16, r32, r64,
|
|
rm8, rm16, rm32, rm64,
|
|
r32_m8, r32_m16, r64_m16,
|
|
m8, m16, m32, m64, m80, m128, m256,
|
|
rel8, rel16, rel32,
|
|
m, moffs, mrip8,
|
|
sreg,
|
|
st0, st, mm, mm_m64,
|
|
xmm0, xmm, xmm_m8, xmm_m16, xmm_m32, xmm_m64, xmm_m128,
|
|
ymm, ymm_m256,
|
|
cr, dr,
|
|
// zig fmt: on
|
|
|
|
pub fn fromOperand(operand: Instruction.Operand, target: *const std.Target) Op {
|
|
return switch (operand) {
|
|
.none => .none,
|
|
|
|
.reg => |reg| switch (reg.class()) {
|
|
.general_purpose => switch (reg) {
|
|
.al => .al,
|
|
.ax => .ax,
|
|
.eax => .eax,
|
|
.rax => .rax,
|
|
.cl => .cl,
|
|
.dx => .dx,
|
|
else => switch (reg.bitSize()) {
|
|
8 => .r8,
|
|
16 => .r16,
|
|
32 => .r32,
|
|
64 => .r64,
|
|
else => unreachable,
|
|
},
|
|
},
|
|
.segment => .sreg,
|
|
.x87 => switch (reg) {
|
|
.st0 => .st0,
|
|
else => .st,
|
|
},
|
|
.mmx => .mm,
|
|
.sse => switch (reg) {
|
|
.xmm0 => .xmm0,
|
|
else => switch (reg.bitSize()) {
|
|
128 => .xmm,
|
|
256 => .ymm,
|
|
else => unreachable,
|
|
},
|
|
},
|
|
.ip => switch (reg) {
|
|
.rip => .rip,
|
|
.eip => .eip,
|
|
.ip => .ip,
|
|
else => unreachable,
|
|
},
|
|
.cr => .cr,
|
|
.dr => .dr,
|
|
},
|
|
|
|
.mem => |mem| switch (mem) {
|
|
.moffs => .moffs,
|
|
.sib => switch (mem.bitSize(target)) {
|
|
0 => .m,
|
|
8 => .m8,
|
|
16 => .m16,
|
|
32 => .m32,
|
|
64 => .m64,
|
|
80 => .m80,
|
|
128 => .m128,
|
|
256 => .m256,
|
|
else => unreachable,
|
|
},
|
|
.rip => switch (mem.bitSize(target)) {
|
|
0, 8 => .mrip8,
|
|
16 => .m16,
|
|
32 => .m32,
|
|
64 => .m64,
|
|
80 => .m80,
|
|
128 => .m128,
|
|
256 => .m256,
|
|
else => unreachable,
|
|
},
|
|
},
|
|
|
|
.imm => |imm| switch (imm) {
|
|
.signed => |x| if (x == 1)
|
|
.unity
|
|
else if (math.cast(i8, x)) |_|
|
|
.imm8s
|
|
else if (math.cast(i16, x)) |_|
|
|
.imm16s
|
|
else
|
|
.imm32s,
|
|
.unsigned => |x| if (x == 1)
|
|
.unity
|
|
else if (math.cast(i8, x)) |_|
|
|
.imm8s
|
|
else if (math.cast(u8, x)) |_|
|
|
.imm8
|
|
else if (math.cast(i16, x)) |_|
|
|
.imm16s
|
|
else if (math.cast(u16, x)) |_|
|
|
.imm16
|
|
else if (math.cast(i32, x)) |_|
|
|
.imm32s
|
|
else if (math.cast(u32, x)) |_|
|
|
.imm32
|
|
else
|
|
.imm64,
|
|
},
|
|
|
|
.bytes => unreachable,
|
|
};
|
|
}
|
|
|
|
pub fn toReg(op: Op) Register {
|
|
return switch (op) {
|
|
else => .none,
|
|
.al => .al,
|
|
.ax => .ax,
|
|
.eax => .eax,
|
|
.rax => .rax,
|
|
.cl => .cl,
|
|
.dx => .dx,
|
|
.rip => .rip,
|
|
.eip => .eip,
|
|
.ip => .ip,
|
|
.st0 => .st0,
|
|
.xmm0 => .xmm0,
|
|
};
|
|
}
|
|
|
|
pub fn immBitSize(op: Op) u64 {
|
|
return switch (op) {
|
|
.none, .m, .moffs, .mrip8, .sreg => unreachable,
|
|
.al, .cl, .dx, .rip, .eip, .ip, .r8, .rm8, .r32_m8 => unreachable,
|
|
.ax, .r16, .rm16 => unreachable,
|
|
.eax, .r32, .rm32, .r32_m16 => unreachable,
|
|
.rax, .r64, .rm64, .r64_m16 => unreachable,
|
|
.st0, .st, .mm, .mm_m64 => unreachable,
|
|
.xmm0, .xmm, .xmm_m8, .xmm_m16, .xmm_m32, .xmm_m64, .xmm_m128 => unreachable,
|
|
.ymm, .ymm_m256 => unreachable,
|
|
.m8, .m16, .m32, .m64, .m80, .m128, .m256 => unreachable,
|
|
.cr, .dr => unreachable,
|
|
.unity => 1,
|
|
.imm8, .imm8s, .rel8 => 8,
|
|
.imm16, .imm16s, .rel16 => 16,
|
|
.imm32, .imm32s, .rel32 => 32,
|
|
.imm64 => 64,
|
|
};
|
|
}
|
|
|
|
pub fn regBitSize(op: Op) u64 {
|
|
return switch (op) {
|
|
.none, .m, .moffs, .mrip8, .sreg => unreachable,
|
|
.unity, .imm8, .imm8s, .imm16, .imm16s, .imm32, .imm32s, .imm64 => unreachable,
|
|
.rel8, .rel16, .rel32 => unreachable,
|
|
.m8, .m16, .m32, .m64, .m80, .m128, .m256 => unreachable,
|
|
.al, .cl, .r8, .rm8 => 8,
|
|
.ax, .dx, .ip, .r16, .rm16 => 16,
|
|
.eax, .eip, .r32, .rm32, .r32_m8, .r32_m16 => 32,
|
|
.rax, .rip, .r64, .rm64, .r64_m16, .mm, .mm_m64, .cr, .dr => 64,
|
|
.st0, .st => 80,
|
|
.xmm0, .xmm, .xmm_m8, .xmm_m16, .xmm_m32, .xmm_m64, .xmm_m128 => 128,
|
|
.ymm, .ymm_m256 => 256,
|
|
};
|
|
}
|
|
|
|
pub fn memBitSize(op: Op) u64 {
|
|
return switch (op) {
|
|
.none, .m, .moffs, .sreg => unreachable,
|
|
.unity, .imm8, .imm8s, .imm16, .imm16s, .imm32, .imm32s, .imm64 => unreachable,
|
|
.rel8, .rel16, .rel32 => unreachable,
|
|
.al, .cl, .r8, .ax, .dx, .ip, .r16, .eax, .eip, .r32, .rax, .rip, .r64 => unreachable,
|
|
.st0, .st, .mm, .xmm0, .xmm, .ymm => unreachable,
|
|
.cr, .dr => unreachable,
|
|
.mrip8, .m8, .rm8, .r32_m8, .xmm_m8 => 8,
|
|
.m16, .rm16, .r32_m16, .r64_m16, .xmm_m16 => 16,
|
|
.m32, .rm32, .xmm_m32 => 32,
|
|
.m64, .rm64, .mm_m64, .xmm_m64 => 64,
|
|
.m80 => 80,
|
|
.m128, .xmm_m128 => 128,
|
|
.m256, .ymm_m256 => 256,
|
|
};
|
|
}
|
|
|
|
pub fn isSigned(op: Op) bool {
|
|
return switch (op) {
|
|
.unity, .imm8, .imm16, .imm32, .imm64 => false,
|
|
.imm8s, .imm16s, .imm32s => true,
|
|
.rel8, .rel16, .rel32 => true,
|
|
else => unreachable,
|
|
};
|
|
}
|
|
|
|
pub fn isUnsigned(op: Op) bool {
|
|
return !op.isSigned();
|
|
}
|
|
|
|
pub fn isRegister(op: Op) bool {
|
|
// zig fmt: off
|
|
return switch (op) {
|
|
.al, .ax, .eax, .rax,
|
|
.cl, .dx,
|
|
.ip, .eip, .rip,
|
|
.r8, .r16, .r32, .r64,
|
|
.rm8, .rm16, .rm32, .rm64,
|
|
.r32_m8, .r32_m16, .r64_m16,
|
|
.st0, .st, .mm, .mm_m64,
|
|
.xmm0, .xmm, .xmm_m8, .xmm_m16, .xmm_m32, .xmm_m64, .xmm_m128,
|
|
.ymm, .ymm_m256,
|
|
.cr, .dr,
|
|
=> true,
|
|
else => false,
|
|
};
|
|
// zig fmt: on
|
|
}
|
|
|
|
pub fn isImmediate(op: Op) bool {
|
|
// zig fmt: off
|
|
return switch (op) {
|
|
.imm8, .imm16, .imm32, .imm64,
|
|
.imm8s, .imm16s, .imm32s,
|
|
.rel8, .rel16, .rel32,
|
|
.unity,
|
|
=> true,
|
|
else => false,
|
|
};
|
|
// zig fmt: on
|
|
}
|
|
|
|
pub fn isMemory(op: Op) bool {
|
|
// zig fmt: off
|
|
return switch (op) {
|
|
.rm8, .rm16, .rm32, .rm64,
|
|
.r32_m8, .r32_m16, .r64_m16,
|
|
.m8, .m16, .m32, .m64, .m80, .m128, .m256,
|
|
.m, .moffs, .mrip8,
|
|
.mm_m64,
|
|
.xmm_m8, .xmm_m16, .xmm_m32, .xmm_m64, .xmm_m128,
|
|
.ymm_m256,
|
|
=> true,
|
|
else => false,
|
|
};
|
|
// zig fmt: on
|
|
}
|
|
|
|
pub fn isSegmentRegister(op: Op) bool {
|
|
return switch (op) {
|
|
.moffs, .sreg => true,
|
|
else => false,
|
|
};
|
|
}
|
|
|
|
pub fn class(op: Op) bits.Register.Class {
|
|
return switch (op) {
|
|
else => unreachable,
|
|
.al, .ax, .eax, .rax, .cl, .dx => .general_purpose,
|
|
.r8, .r16, .r32, .r64 => .general_purpose,
|
|
.rm8, .rm16, .rm32, .rm64 => .general_purpose,
|
|
.r32_m8, .r32_m16, .r64_m16 => .general_purpose,
|
|
.sreg => .segment,
|
|
.st0, .st => .x87,
|
|
.mm, .mm_m64 => .mmx,
|
|
.xmm0, .xmm, .xmm_m8, .xmm_m16, .xmm_m32, .xmm_m64, .xmm_m128 => .sse,
|
|
.ymm, .ymm_m256 => .sse,
|
|
.rip, .eip, .ip => .ip,
|
|
.cr => .cr,
|
|
.dr => .dr,
|
|
};
|
|
}
|
|
|
|
/// Given an operand `op` checks if `target` is a subset for the purposes of the encoding.
|
|
pub fn isSubset(op: Op, target: Op) bool {
|
|
switch (op) {
|
|
.none, .m, .moffs, .sreg => return op == target,
|
|
else => {
|
|
if (op.isRegister() and target.isRegister()) {
|
|
return switch (target.toReg()) {
|
|
.none => op.class() == target.class() and op.regBitSize() == target.regBitSize(),
|
|
else => op == target,
|
|
};
|
|
}
|
|
if (op.isMemory() and target.isMemory()) {
|
|
switch (target) {
|
|
.m => return true,
|
|
.moffs, .mrip8 => return op == target,
|
|
else => return op.memBitSize() == target.memBitSize(),
|
|
}
|
|
}
|
|
if (op.isImmediate() and target.isImmediate()) {
|
|
switch (target) {
|
|
.imm64 => if (op.immBitSize() <= 64) return true,
|
|
.imm32s, .rel32 => if (op.immBitSize() < 32 or (op.immBitSize() == 32 and op.isSigned()))
|
|
return true,
|
|
.imm32 => if (op.immBitSize() <= 32) return true,
|
|
.imm16s, .rel16 => if (op.immBitSize() < 16 or (op.immBitSize() == 16 and op.isSigned()))
|
|
return true,
|
|
.imm16 => if (op.immBitSize() <= 16) return true,
|
|
.imm8s, .rel8 => if (op.immBitSize() < 8 or (op.immBitSize() == 8 and op.isSigned()))
|
|
return true,
|
|
.imm8 => if (op.immBitSize() <= 8) return true,
|
|
else => {},
|
|
}
|
|
return op == target;
|
|
}
|
|
return false;
|
|
},
|
|
}
|
|
}
|
|
};
|
|
|
|
pub const Mode = enum {
|
|
// zig fmt: off
|
|
none,
|
|
short, long,
|
|
rex, rex_short,
|
|
wait,
|
|
vex_128_w0, vex_128_w1, vex_128_wig,
|
|
vex_256_w0, vex_256_w1, vex_256_wig,
|
|
vex_lig_w0, vex_lig_w1, vex_lig_wig,
|
|
vex_lz_w0, vex_lz_w1, vex_lz_wig,
|
|
// zig fmt: on
|
|
|
|
pub fn isShort(mode: Mode) bool {
|
|
return switch (mode) {
|
|
.short, .rex_short => true,
|
|
else => false,
|
|
};
|
|
}
|
|
|
|
pub fn isLong(mode: Mode) bool {
|
|
return switch (mode) {
|
|
.long,
|
|
.vex_128_w1,
|
|
.vex_256_w1,
|
|
.vex_lig_w1,
|
|
.vex_lz_w1,
|
|
=> true,
|
|
else => false,
|
|
};
|
|
}
|
|
|
|
pub fn isRex(mode: Mode) bool {
|
|
return switch (mode) {
|
|
else => false,
|
|
.rex, .rex_short => true,
|
|
};
|
|
}
|
|
|
|
pub fn isVex(mode: Mode) bool {
|
|
return switch (mode) {
|
|
// zig fmt: off
|
|
else => false,
|
|
.vex_128_w0, .vex_128_w1, .vex_128_wig,
|
|
.vex_256_w0, .vex_256_w1, .vex_256_wig,
|
|
.vex_lig_w0, .vex_lig_w1, .vex_lig_wig,
|
|
.vex_lz_w0, .vex_lz_w1, .vex_lz_wig,
|
|
=> true,
|
|
// zig fmt: on
|
|
};
|
|
}
|
|
|
|
pub fn isVecLong(mode: Mode) bool {
|
|
return switch (mode) {
|
|
// zig fmt: off
|
|
else => unreachable,
|
|
.vex_128_w0, .vex_128_w1, .vex_128_wig,
|
|
.vex_lig_w0, .vex_lig_w1, .vex_lig_wig,
|
|
.vex_lz_w0, .vex_lz_w1, .vex_lz_wig,
|
|
=> false,
|
|
.vex_256_w0, .vex_256_w1, .vex_256_wig,
|
|
=> true,
|
|
// zig fmt: on
|
|
};
|
|
}
|
|
};
|
|
|
|
pub const Feature = enum {
|
|
none,
|
|
@"32bit",
|
|
@"64bit",
|
|
adx,
|
|
aes,
|
|
@"aes avx",
|
|
avx,
|
|
avx2,
|
|
bmi,
|
|
bmi2,
|
|
cldemote,
|
|
clflushopt,
|
|
clwb,
|
|
cmov,
|
|
@"cmov x87",
|
|
crc32,
|
|
enqcmd,
|
|
f16c,
|
|
fma,
|
|
fsgsbase,
|
|
fxsr,
|
|
gfni,
|
|
@"gfni avx",
|
|
hreset,
|
|
@"invpcid 32bit",
|
|
@"invpcid 64bit",
|
|
kl,
|
|
lzcnt,
|
|
mmx,
|
|
movbe,
|
|
pclmul,
|
|
@"pclmul avx",
|
|
pku,
|
|
popcnt,
|
|
prefetch,
|
|
@"prefetchi 64bit",
|
|
prefetchwt1,
|
|
prfchw,
|
|
rdrnd,
|
|
rdseed,
|
|
@"rdpid 32bit",
|
|
@"rdpid 64bit",
|
|
sahf,
|
|
serialize,
|
|
shstk,
|
|
smap,
|
|
sse,
|
|
sse2,
|
|
sse3,
|
|
sse4_1,
|
|
sse4_2,
|
|
ssse3,
|
|
sha,
|
|
uintr,
|
|
vaes,
|
|
vpclmulqdq,
|
|
waitpkg,
|
|
widekl,
|
|
x87,
|
|
};
|
|
|
|
fn estimateInstructionLength(prefix: Prefix, encoding: Encoding, ops: []const Operand) usize {
|
|
var inst = Instruction{
|
|
.prefix = prefix,
|
|
.encoding = encoding,
|
|
.ops = @splat(.none),
|
|
};
|
|
@memcpy(inst.ops[0..ops.len], ops);
|
|
|
|
var cwriter = std.io.countingWriter(std.io.null_writer);
|
|
inst.encode(cwriter.writer(), .{
|
|
.allow_frame_locs = true,
|
|
.allow_symbols = true,
|
|
}) catch unreachable; // Not allowed to fail here unless OOM.
|
|
return @as(usize, @intCast(cwriter.bytes_written));
|
|
}
|
|
|
|
const mnemonic_to_encodings_map = init: {
|
|
@setEvalBranchQuota(5_800);
|
|
const mnemonic_count = @typeInfo(Mnemonic).@"enum".fields.len;
|
|
var mnemonic_map: [mnemonic_count][]Data = @splat(&.{});
|
|
const encodings = @import("encodings.zig");
|
|
for (encodings.table) |entry| mnemonic_map[@intFromEnum(entry[0])].len += 1;
|
|
var data_storage: [encodings.table.len]Data = undefined;
|
|
var storage_i: usize = 0;
|
|
for (&mnemonic_map) |*value| {
|
|
value.ptr = data_storage[storage_i..].ptr;
|
|
storage_i += value.len;
|
|
}
|
|
var mnemonic_i: [mnemonic_count]usize = @splat(0);
|
|
const ops_len = @typeInfo(std.meta.FieldType(Data, .ops)).array.len;
|
|
const opc_len = @typeInfo(std.meta.FieldType(Data, .opc)).array.len;
|
|
for (encodings.table) |entry| {
|
|
const i = &mnemonic_i[@intFromEnum(entry[0])];
|
|
mnemonic_map[@intFromEnum(entry[0])][i.*] = .{
|
|
.op_en = entry[1],
|
|
.ops = (entry[2] ++ .{.none} ** (ops_len - entry[2].len)).*,
|
|
.opc_len = entry[3].len,
|
|
.opc = (entry[3] ++ .{undefined} ** (opc_len - entry[3].len)).*,
|
|
.modrm_ext = entry[4],
|
|
.mode = entry[5],
|
|
.feature = entry[6],
|
|
};
|
|
i.* += 1;
|
|
}
|
|
const final_storage = data_storage;
|
|
var final_map: [mnemonic_count][]const Data = @splat(&.{});
|
|
storage_i = 0;
|
|
for (&final_map, mnemonic_map) |*final_value, value| {
|
|
final_value.* = final_storage[storage_i..][0..value.len];
|
|
storage_i += value.len;
|
|
}
|
|
break :init final_map;
|
|
};
|