8f1408578c
Rather than directly pasting the output from the target-details-generator tool, we have to look at the diff line by line and decide how to incorporate the changes. The baseline abstraction is something that Zig provides. The changes to x86 appear to be incorrect. After LLVM commit 3ad09fd03c51823aeb0bcbd7898aada33e9228d6 the CPU features are stored in a different data layout in their tables, and so we need to update the target details extraction tool to match.
1109 lines
30 KiB
Zig
1109 lines
30 KiB
Zig
// SPDX-License-Identifier: MIT
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// Copyright (c) 2015-2020 Zig Contributors
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// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
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// The MIT license requires this copyright notice to be included in all copies
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// and substantial portions of the software.
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const std = @import("../std.zig");
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const CpuFeature = std.Target.Cpu.Feature;
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const CpuModel = std.Target.Cpu.Model;
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pub const Feature = enum {
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@"64bit",
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@"64bitregs",
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allow_unaligned_fp_access,
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altivec,
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booke,
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bpermd,
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cmpb,
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crbits,
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crypto,
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direct_move,
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e500,
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extdiv,
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fcpsgn,
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float128,
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fpcvt,
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fprnd,
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fpu,
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fre,
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fres,
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frsqrte,
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frsqrtes,
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fsqrt,
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fuse_addi_load,
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fuse_addis_load,
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fuse_store,
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fusion,
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hard_float,
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htm,
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icbt,
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invariant_function_descriptors,
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isa_v30_instructions,
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isa_v31_instructions,
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isel,
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ldbrx,
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lfiwax,
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longcall,
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mfocrf,
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mma,
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msync,
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paired_vector_memops,
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partword_atomics,
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pcrelative_memops,
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popcntd,
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power10_vector,
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power8_altivec,
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power8_vector,
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power9_altivec,
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power9_vector,
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ppc_postra_sched,
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ppc_prera_sched,
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ppc4xx,
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ppc6xx,
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predictable_select_expensive,
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prefix_instrs,
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qpx,
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recipprec,
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secure_plt,
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slow_popcntd,
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spe,
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stfiwx,
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two_const_nr,
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vectors_use_two_units,
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vsx,
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};
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pub usingnamespace CpuFeature.feature_set_fns(Feature);
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pub const all_features = blk: {
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const len = @typeInfo(Feature).Enum.fields.len;
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std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
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var result: [len]CpuFeature = undefined;
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result[@enumToInt(Feature.@"64bit")] = .{
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.llvm_name = "64bit",
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.description = "Enable 64-bit instructions",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.@"64bitregs")] = .{
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.llvm_name = "64bitregs",
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.description = "Enable 64-bit registers usage for ppc32 [beta]",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.allow_unaligned_fp_access)] = .{
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.llvm_name = "allow-unaligned-fp-access",
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.description = "CPU does not trap on unaligned FP access",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.altivec)] = .{
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.llvm_name = "altivec",
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.description = "Enable Altivec instructions",
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.dependencies = featureSet(&[_]Feature{
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.fpu,
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}),
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};
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result[@enumToInt(Feature.booke)] = .{
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.llvm_name = "booke",
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.description = "Enable Book E instructions",
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.dependencies = featureSet(&[_]Feature{
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.icbt,
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}),
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};
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result[@enumToInt(Feature.bpermd)] = .{
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.llvm_name = "bpermd",
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.description = "Enable the bpermd instruction",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.cmpb)] = .{
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.llvm_name = "cmpb",
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.description = "Enable the cmpb instruction",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.crbits)] = .{
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.llvm_name = "crbits",
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.description = "Use condition-register bits individually",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.crypto)] = .{
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.llvm_name = "crypto",
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.description = "Enable POWER8 Crypto instructions",
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.dependencies = featureSet(&[_]Feature{
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.power8_altivec,
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}),
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};
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result[@enumToInt(Feature.direct_move)] = .{
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.llvm_name = "direct-move",
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.description = "Enable Power8 direct move instructions",
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.dependencies = featureSet(&[_]Feature{
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.vsx,
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}),
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};
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result[@enumToInt(Feature.e500)] = .{
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.llvm_name = "e500",
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.description = "Enable E500/E500mc instructions",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.extdiv)] = .{
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.llvm_name = "extdiv",
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.description = "Enable extended divide instructions",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.fcpsgn)] = .{
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.llvm_name = "fcpsgn",
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.description = "Enable the fcpsgn instruction",
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.dependencies = featureSet(&[_]Feature{
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.fpu,
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}),
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};
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result[@enumToInt(Feature.float128)] = .{
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.llvm_name = "float128",
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.description = "Enable the __float128 data type for IEEE-754R Binary128.",
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.dependencies = featureSet(&[_]Feature{
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.vsx,
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}),
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};
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result[@enumToInt(Feature.fpcvt)] = .{
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.llvm_name = "fpcvt",
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.description = "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions",
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.dependencies = featureSet(&[_]Feature{
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.fpu,
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}),
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};
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result[@enumToInt(Feature.fprnd)] = .{
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.llvm_name = "fprnd",
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.description = "Enable the fri[mnpz] instructions",
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.dependencies = featureSet(&[_]Feature{
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.fpu,
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}),
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};
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result[@enumToInt(Feature.fpu)] = .{
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.llvm_name = "fpu",
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.description = "Enable classic FPU instructions",
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.dependencies = featureSet(&[_]Feature{
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.hard_float,
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}),
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};
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result[@enumToInt(Feature.fre)] = .{
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.llvm_name = "fre",
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.description = "Enable the fre instruction",
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.dependencies = featureSet(&[_]Feature{
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.fpu,
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}),
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};
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result[@enumToInt(Feature.fres)] = .{
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.llvm_name = "fres",
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.description = "Enable the fres instruction",
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.dependencies = featureSet(&[_]Feature{
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.fpu,
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}),
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};
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result[@enumToInt(Feature.frsqrte)] = .{
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.llvm_name = "frsqrte",
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.description = "Enable the frsqrte instruction",
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.dependencies = featureSet(&[_]Feature{
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.fpu,
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}),
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};
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result[@enumToInt(Feature.frsqrtes)] = .{
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.llvm_name = "frsqrtes",
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.description = "Enable the frsqrtes instruction",
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.dependencies = featureSet(&[_]Feature{
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.fpu,
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}),
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};
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result[@enumToInt(Feature.fsqrt)] = .{
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.llvm_name = "fsqrt",
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.description = "Enable the fsqrt instruction",
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.dependencies = featureSet(&[_]Feature{
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.fpu,
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}),
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};
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result[@enumToInt(Feature.fuse_addi_load)] = .{
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.llvm_name = "fuse-addi-load",
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.description = "Power8 Addi-Load fusion",
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.dependencies = featureSet(&[_]Feature{
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.fusion,
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}),
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};
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result[@enumToInt(Feature.fuse_addis_load)] = .{
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.llvm_name = "fuse-addis-load",
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.description = "Power8 Addis-Load fusion",
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.dependencies = featureSet(&[_]Feature{
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.fusion,
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}),
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};
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result[@enumToInt(Feature.fuse_store)] = .{
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.llvm_name = "fuse-store",
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.description = "Target supports store clustering",
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.dependencies = featureSet(&[_]Feature{
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.fusion,
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}),
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};
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result[@enumToInt(Feature.fusion)] = .{
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.llvm_name = "fusion",
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.description = "Target supports instruction fusion",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.hard_float)] = .{
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.llvm_name = "hard-float",
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.description = "Enable floating-point instructions",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.htm)] = .{
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.llvm_name = "htm",
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.description = "Enable Hardware Transactional Memory instructions",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.icbt)] = .{
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.llvm_name = "icbt",
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.description = "Enable icbt instruction",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.invariant_function_descriptors)] = .{
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.llvm_name = "invariant-function-descriptors",
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.description = "Assume function descriptors are invariant",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.isa_v30_instructions)] = .{
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.llvm_name = "isa-v30-instructions",
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.description = "Enable instructions in ISA 3.0.",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.isa_v31_instructions)] = .{
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.llvm_name = "isa-v31-instructions",
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.description = "Enable instructions in ISA 3.1.",
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.dependencies = featureSet(&[_]Feature{
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.isa_v30_instructions,
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}),
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};
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result[@enumToInt(Feature.isel)] = .{
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.llvm_name = "isel",
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.description = "Enable the isel instruction",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.ldbrx)] = .{
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.llvm_name = "ldbrx",
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.description = "Enable the ldbrx instruction",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.lfiwax)] = .{
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.llvm_name = "lfiwax",
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.description = "Enable the lfiwax instruction",
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.dependencies = featureSet(&[_]Feature{
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.fpu,
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}),
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};
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result[@enumToInt(Feature.longcall)] = .{
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.llvm_name = "longcall",
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.description = "Always use indirect calls",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.mfocrf)] = .{
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.llvm_name = "mfocrf",
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.description = "Enable the MFOCRF instruction",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.mma)] = .{
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.llvm_name = "mma",
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.description = "Enable MMA instructions",
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.dependencies = featureSet(&[_]Feature{
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.paired_vector_memops,
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.power8_vector,
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.power9_altivec,
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}),
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};
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result[@enumToInt(Feature.msync)] = .{
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.llvm_name = "msync",
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.description = "Has only the msync instruction instead of sync",
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.dependencies = featureSet(&[_]Feature{
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.booke,
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}),
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};
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result[@enumToInt(Feature.paired_vector_memops)] = .{
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.llvm_name = "paired-vector-memops",
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.description = "32Byte load and store instructions",
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.dependencies = featureSet(&[_]Feature{
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.isa_v30_instructions,
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}),
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};
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result[@enumToInt(Feature.partword_atomics)] = .{
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.llvm_name = "partword-atomics",
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.description = "Enable l[bh]arx and st[bh]cx.",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.pcrelative_memops)] = .{
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.llvm_name = "pcrelative-memops",
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.description = "Enable PC relative Memory Ops",
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.dependencies = featureSet(&[_]Feature{
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.isa_v30_instructions,
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.prefix_instrs,
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}),
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};
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result[@enumToInt(Feature.popcntd)] = .{
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.llvm_name = "popcntd",
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.description = "Enable the popcnt[dw] instructions",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.power10_vector)] = .{
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.llvm_name = "power10-vector",
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.description = "Enable POWER10 vector instructions",
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.dependencies = featureSet(&[_]Feature{
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.isa_v31_instructions,
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.power9_vector,
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}),
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};
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result[@enumToInt(Feature.power8_altivec)] = .{
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.llvm_name = "power8-altivec",
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.description = "Enable POWER8 Altivec instructions",
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.dependencies = featureSet(&[_]Feature{
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.altivec,
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}),
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};
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result[@enumToInt(Feature.power8_vector)] = .{
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.llvm_name = "power8-vector",
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.description = "Enable POWER8 vector instructions",
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.dependencies = featureSet(&[_]Feature{
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.power8_altivec,
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.vsx,
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}),
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};
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result[@enumToInt(Feature.power9_altivec)] = .{
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.llvm_name = "power9-altivec",
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.description = "Enable POWER9 Altivec instructions",
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.dependencies = featureSet(&[_]Feature{
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.isa_v30_instructions,
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.power8_altivec,
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}),
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};
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result[@enumToInt(Feature.power9_vector)] = .{
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.llvm_name = "power9-vector",
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.description = "Enable POWER9 vector instructions",
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.dependencies = featureSet(&[_]Feature{
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.isa_v30_instructions,
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.power8_vector,
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.power9_altivec,
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}),
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};
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result[@enumToInt(Feature.ppc_postra_sched)] = .{
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.llvm_name = "ppc-postra-sched",
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.description = "Use PowerPC post-RA scheduling strategy",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.ppc_prera_sched)] = .{
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.llvm_name = "ppc-prera-sched",
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.description = "Use PowerPC pre-RA scheduling strategy",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.ppc4xx)] = .{
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.llvm_name = "ppc4xx",
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.description = "Enable PPC 4xx instructions",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.ppc6xx)] = .{
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.llvm_name = "ppc6xx",
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.description = "Enable PPC 6xx instructions",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.predictable_select_expensive)] = .{
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.llvm_name = "predictable-select-expensive",
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.description = "Prefer likely predicted branches over selects",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.prefix_instrs)] = .{
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.llvm_name = "prefix-instrs",
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.description = "Enable prefixed instructions",
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.dependencies = featureSet(&[_]Feature{
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.isa_v30_instructions,
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.power8_vector,
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.power9_altivec,
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}),
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};
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result[@enumToInt(Feature.qpx)] = .{
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.llvm_name = null,
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.description = "Enable QPX instructions",
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.dependencies = featureSet(&[_]Feature{
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.fpu,
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}),
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};
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result[@enumToInt(Feature.recipprec)] = .{
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.llvm_name = "recipprec",
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.description = "Assume higher precision reciprocal estimates",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.secure_plt)] = .{
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.llvm_name = "secure-plt",
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.description = "Enable secure plt mode",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.slow_popcntd)] = .{
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.llvm_name = "slow-popcntd",
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.description = "Has slow popcnt[dw] instructions",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.spe)] = .{
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.llvm_name = "spe",
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.description = "Enable SPE instructions",
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.dependencies = featureSet(&[_]Feature{
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.hard_float,
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}),
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};
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result[@enumToInt(Feature.stfiwx)] = .{
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.llvm_name = "stfiwx",
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.description = "Enable the stfiwx instruction",
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.dependencies = featureSet(&[_]Feature{
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.fpu,
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}),
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};
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result[@enumToInt(Feature.two_const_nr)] = .{
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.llvm_name = "two-const-nr",
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.description = "Requires two constant Newton-Raphson computation",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.vectors_use_two_units)] = .{
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.llvm_name = "vectors-use-two-units",
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.description = "Vectors use two units",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.vsx)] = .{
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.llvm_name = "vsx",
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.description = "Enable VSX instructions",
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.dependencies = featureSet(&[_]Feature{
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.altivec,
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}),
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};
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const ti = @typeInfo(Feature);
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for (result) |*elem, i| {
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elem.index = i;
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elem.name = ti.Enum.fields[i].name;
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}
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break :blk result;
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};
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pub const cpu = struct {
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pub const @"ppc440" = CpuModel{
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.name = "ppc440",
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.llvm_name = "440",
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.features = featureSet(&[_]Feature{
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.booke,
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.fres,
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.frsqrte,
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.icbt,
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.isel,
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.msync,
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}),
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};
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pub const @"ppc450" = CpuModel{
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.name = "ppc450",
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.llvm_name = "450",
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.features = featureSet(&[_]Feature{
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.booke,
|
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.fres,
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.frsqrte,
|
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.icbt,
|
|
.isel,
|
|
.msync,
|
|
}),
|
|
};
|
|
pub const @"ppc601" = CpuModel{
|
|
.name = "ppc601",
|
|
.llvm_name = "601",
|
|
.features = featureSet(&[_]Feature{
|
|
.fpu,
|
|
}),
|
|
};
|
|
pub const @"ppc602" = CpuModel{
|
|
.name = "ppc602",
|
|
.llvm_name = "602",
|
|
.features = featureSet(&[_]Feature{
|
|
.fpu,
|
|
}),
|
|
};
|
|
pub const @"ppc603" = CpuModel{
|
|
.name = "ppc603",
|
|
.llvm_name = "603",
|
|
.features = featureSet(&[_]Feature{
|
|
.fres,
|
|
.frsqrte,
|
|
}),
|
|
};
|
|
pub const @"ppc603e" = CpuModel{
|
|
.name = "ppc603e",
|
|
.llvm_name = "603e",
|
|
.features = featureSet(&[_]Feature{
|
|
.fres,
|
|
.frsqrte,
|
|
}),
|
|
};
|
|
pub const @"ppc603ev" = CpuModel{
|
|
.name = "ppc603ev",
|
|
.llvm_name = "603ev",
|
|
.features = featureSet(&[_]Feature{
|
|
.fres,
|
|
.frsqrte,
|
|
}),
|
|
};
|
|
pub const @"ppc604" = CpuModel{
|
|
.name = "ppc604",
|
|
.llvm_name = "604",
|
|
.features = featureSet(&[_]Feature{
|
|
.fres,
|
|
.frsqrte,
|
|
}),
|
|
};
|
|
pub const @"ppc604e" = CpuModel{
|
|
.name = "ppc604e",
|
|
.llvm_name = "604e",
|
|
.features = featureSet(&[_]Feature{
|
|
.fres,
|
|
.frsqrte,
|
|
}),
|
|
};
|
|
pub const @"ppc620" = CpuModel{
|
|
.name = "ppc620",
|
|
.llvm_name = "620",
|
|
.features = featureSet(&[_]Feature{
|
|
.fres,
|
|
.frsqrte,
|
|
}),
|
|
};
|
|
pub const @"ppc7400" = CpuModel{
|
|
.name = "ppc7400",
|
|
.llvm_name = "7400",
|
|
.features = featureSet(&[_]Feature{
|
|
.altivec,
|
|
.fres,
|
|
.frsqrte,
|
|
}),
|
|
};
|
|
pub const @"ppc7450" = CpuModel{
|
|
.name = "ppc7450",
|
|
.llvm_name = "7450",
|
|
.features = featureSet(&[_]Feature{
|
|
.altivec,
|
|
.fres,
|
|
.frsqrte,
|
|
}),
|
|
};
|
|
pub const @"ppc750" = CpuModel{
|
|
.name = "ppc750",
|
|
.llvm_name = "750",
|
|
.features = featureSet(&[_]Feature{
|
|
.fres,
|
|
.frsqrte,
|
|
}),
|
|
};
|
|
pub const @"ppc970" = CpuModel{
|
|
.name = "ppc970",
|
|
.llvm_name = "970",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.altivec,
|
|
.fres,
|
|
.frsqrte,
|
|
.fsqrt,
|
|
.mfocrf,
|
|
.stfiwx,
|
|
}),
|
|
};
|
|
pub const a2 = CpuModel{
|
|
.name = "a2",
|
|
.llvm_name = "a2",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.booke,
|
|
.cmpb,
|
|
.fcpsgn,
|
|
.fpcvt,
|
|
.fprnd,
|
|
.fre,
|
|
.fres,
|
|
.frsqrte,
|
|
.frsqrtes,
|
|
.fsqrt,
|
|
.icbt,
|
|
.isel,
|
|
.ldbrx,
|
|
.lfiwax,
|
|
.mfocrf,
|
|
.recipprec,
|
|
.slow_popcntd,
|
|
.stfiwx,
|
|
}),
|
|
};
|
|
pub const a2q = CpuModel{
|
|
.name = "a2q",
|
|
.llvm_name = "a2q",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.booke,
|
|
.cmpb,
|
|
.fcpsgn,
|
|
.fpcvt,
|
|
.fprnd,
|
|
.fre,
|
|
.fres,
|
|
.frsqrte,
|
|
.frsqrtes,
|
|
.fsqrt,
|
|
.icbt,
|
|
.isel,
|
|
.ldbrx,
|
|
.lfiwax,
|
|
.mfocrf,
|
|
.qpx,
|
|
.recipprec,
|
|
.slow_popcntd,
|
|
.stfiwx,
|
|
}),
|
|
};
|
|
pub const e500 = CpuModel{
|
|
.name = "e500",
|
|
.llvm_name = "e500",
|
|
.features = featureSet(&[_]Feature{
|
|
.booke,
|
|
.icbt,
|
|
.isel,
|
|
.msync,
|
|
.spe,
|
|
}),
|
|
};
|
|
pub const e500mc = CpuModel{
|
|
.name = "e500mc",
|
|
.llvm_name = "e500mc",
|
|
.features = featureSet(&[_]Feature{
|
|
.booke,
|
|
.icbt,
|
|
.isel,
|
|
.stfiwx,
|
|
}),
|
|
};
|
|
pub const e5500 = CpuModel{
|
|
.name = "e5500",
|
|
.llvm_name = "e5500",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.booke,
|
|
.icbt,
|
|
.isel,
|
|
.mfocrf,
|
|
.stfiwx,
|
|
}),
|
|
};
|
|
pub const future = CpuModel{
|
|
.name = "future",
|
|
.llvm_name = "future",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.allow_unaligned_fp_access,
|
|
.altivec,
|
|
.bpermd,
|
|
.cmpb,
|
|
.crypto,
|
|
.direct_move,
|
|
.extdiv,
|
|
.fcpsgn,
|
|
.fpcvt,
|
|
.fprnd,
|
|
.fre,
|
|
.fres,
|
|
.frsqrte,
|
|
.frsqrtes,
|
|
.fsqrt,
|
|
.fuse_store,
|
|
.htm,
|
|
.icbt,
|
|
.isa_v30_instructions,
|
|
.isa_v31_instructions,
|
|
.isel,
|
|
.ldbrx,
|
|
.lfiwax,
|
|
.mfocrf,
|
|
.mma,
|
|
.paired_vector_memops,
|
|
.partword_atomics,
|
|
.pcrelative_memops,
|
|
.popcntd,
|
|
.power10_vector,
|
|
.power8_altivec,
|
|
.power8_vector,
|
|
.power9_altivec,
|
|
.power9_vector,
|
|
.ppc_postra_sched,
|
|
.ppc_prera_sched,
|
|
.predictable_select_expensive,
|
|
.prefix_instrs,
|
|
.recipprec,
|
|
.stfiwx,
|
|
.two_const_nr,
|
|
.vsx,
|
|
}),
|
|
};
|
|
pub const g3 = CpuModel{
|
|
.name = "g3",
|
|
.llvm_name = "g3",
|
|
.features = featureSet(&[_]Feature{
|
|
.fres,
|
|
.frsqrte,
|
|
}),
|
|
};
|
|
pub const g4 = CpuModel{
|
|
.name = "g4",
|
|
.llvm_name = "g4",
|
|
.features = featureSet(&[_]Feature{
|
|
.altivec,
|
|
.fres,
|
|
.frsqrte,
|
|
}),
|
|
};
|
|
pub const @"g4+" = CpuModel{
|
|
.name = "g4+",
|
|
.llvm_name = "g4+",
|
|
.features = featureSet(&[_]Feature{
|
|
.altivec,
|
|
.fres,
|
|
.frsqrte,
|
|
}),
|
|
};
|
|
pub const g5 = CpuModel{
|
|
.name = "g5",
|
|
.llvm_name = "g5",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.altivec,
|
|
.fres,
|
|
.frsqrte,
|
|
.fsqrt,
|
|
.mfocrf,
|
|
.stfiwx,
|
|
}),
|
|
};
|
|
pub const generic = CpuModel{
|
|
.name = "generic",
|
|
.llvm_name = "generic",
|
|
.features = featureSet(&[_]Feature{
|
|
.hard_float,
|
|
}),
|
|
};
|
|
pub const ppc = CpuModel{
|
|
.name = "ppc",
|
|
.llvm_name = "ppc",
|
|
.features = featureSet(&[_]Feature{
|
|
.hard_float,
|
|
}),
|
|
};
|
|
pub const ppc32 = CpuModel{
|
|
.name = "ppc32",
|
|
.llvm_name = "ppc32",
|
|
.features = featureSet(&[_]Feature{
|
|
.hard_float,
|
|
}),
|
|
};
|
|
pub const ppc64 = CpuModel{
|
|
.name = "ppc64",
|
|
.llvm_name = "ppc64",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.altivec,
|
|
.fres,
|
|
.frsqrte,
|
|
.fsqrt,
|
|
.mfocrf,
|
|
.stfiwx,
|
|
}),
|
|
};
|
|
pub const ppc64le = CpuModel{
|
|
.name = "ppc64le",
|
|
.llvm_name = "ppc64le",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.allow_unaligned_fp_access,
|
|
.altivec,
|
|
.bpermd,
|
|
.cmpb,
|
|
.crypto,
|
|
.direct_move,
|
|
.extdiv,
|
|
.fcpsgn,
|
|
.fpcvt,
|
|
.fprnd,
|
|
.fre,
|
|
.fres,
|
|
.frsqrte,
|
|
.frsqrtes,
|
|
.fsqrt,
|
|
.fuse_addi_load,
|
|
.fuse_addis_load,
|
|
.htm,
|
|
.icbt,
|
|
.isel,
|
|
.ldbrx,
|
|
.lfiwax,
|
|
.mfocrf,
|
|
.partword_atomics,
|
|
.popcntd,
|
|
.power8_altivec,
|
|
.power8_vector,
|
|
.predictable_select_expensive,
|
|
.recipprec,
|
|
.stfiwx,
|
|
.two_const_nr,
|
|
.vsx,
|
|
}),
|
|
};
|
|
pub const pwr10 = CpuModel{
|
|
.name = "pwr10",
|
|
.llvm_name = "pwr10",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.allow_unaligned_fp_access,
|
|
.altivec,
|
|
.bpermd,
|
|
.cmpb,
|
|
.crypto,
|
|
.direct_move,
|
|
.extdiv,
|
|
.fcpsgn,
|
|
.fpcvt,
|
|
.fprnd,
|
|
.fre,
|
|
.fres,
|
|
.frsqrte,
|
|
.frsqrtes,
|
|
.fsqrt,
|
|
.fuse_store,
|
|
.htm,
|
|
.icbt,
|
|
.isa_v30_instructions,
|
|
.isa_v31_instructions,
|
|
.isel,
|
|
.ldbrx,
|
|
.lfiwax,
|
|
.mfocrf,
|
|
.mma,
|
|
.paired_vector_memops,
|
|
.partword_atomics,
|
|
.pcrelative_memops,
|
|
.popcntd,
|
|
.power10_vector,
|
|
.power8_altivec,
|
|
.power8_vector,
|
|
.power9_altivec,
|
|
.power9_vector,
|
|
.ppc_postra_sched,
|
|
.ppc_prera_sched,
|
|
.predictable_select_expensive,
|
|
.prefix_instrs,
|
|
.recipprec,
|
|
.stfiwx,
|
|
.two_const_nr,
|
|
.vsx,
|
|
}),
|
|
};
|
|
pub const pwr3 = CpuModel{
|
|
.name = "pwr3",
|
|
.llvm_name = "pwr3",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.altivec,
|
|
.fres,
|
|
.frsqrte,
|
|
.mfocrf,
|
|
.stfiwx,
|
|
}),
|
|
};
|
|
pub const pwr4 = CpuModel{
|
|
.name = "pwr4",
|
|
.llvm_name = "pwr4",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.altivec,
|
|
.fres,
|
|
.frsqrte,
|
|
.fsqrt,
|
|
.mfocrf,
|
|
.stfiwx,
|
|
}),
|
|
};
|
|
pub const pwr5 = CpuModel{
|
|
.name = "pwr5",
|
|
.llvm_name = "pwr5",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.altivec,
|
|
.fre,
|
|
.fres,
|
|
.frsqrte,
|
|
.frsqrtes,
|
|
.fsqrt,
|
|
.mfocrf,
|
|
.stfiwx,
|
|
}),
|
|
};
|
|
pub const pwr5x = CpuModel{
|
|
.name = "pwr5x",
|
|
.llvm_name = "pwr5x",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.altivec,
|
|
.fprnd,
|
|
.fre,
|
|
.fres,
|
|
.frsqrte,
|
|
.frsqrtes,
|
|
.fsqrt,
|
|
.mfocrf,
|
|
.stfiwx,
|
|
}),
|
|
};
|
|
pub const pwr6 = CpuModel{
|
|
.name = "pwr6",
|
|
.llvm_name = "pwr6",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.altivec,
|
|
.cmpb,
|
|
.fcpsgn,
|
|
.fprnd,
|
|
.fre,
|
|
.fres,
|
|
.frsqrte,
|
|
.frsqrtes,
|
|
.fsqrt,
|
|
.lfiwax,
|
|
.mfocrf,
|
|
.recipprec,
|
|
.stfiwx,
|
|
}),
|
|
};
|
|
pub const pwr6x = CpuModel{
|
|
.name = "pwr6x",
|
|
.llvm_name = "pwr6x",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.altivec,
|
|
.cmpb,
|
|
.fcpsgn,
|
|
.fprnd,
|
|
.fre,
|
|
.fres,
|
|
.frsqrte,
|
|
.frsqrtes,
|
|
.fsqrt,
|
|
.lfiwax,
|
|
.mfocrf,
|
|
.recipprec,
|
|
.stfiwx,
|
|
}),
|
|
};
|
|
pub const pwr7 = CpuModel{
|
|
.name = "pwr7",
|
|
.llvm_name = "pwr7",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.allow_unaligned_fp_access,
|
|
.altivec,
|
|
.bpermd,
|
|
.cmpb,
|
|
.extdiv,
|
|
.fcpsgn,
|
|
.fpcvt,
|
|
.fprnd,
|
|
.fre,
|
|
.fres,
|
|
.frsqrte,
|
|
.frsqrtes,
|
|
.fsqrt,
|
|
.isel,
|
|
.ldbrx,
|
|
.lfiwax,
|
|
.mfocrf,
|
|
.popcntd,
|
|
.recipprec,
|
|
.stfiwx,
|
|
.two_const_nr,
|
|
.vsx,
|
|
}),
|
|
};
|
|
pub const pwr8 = CpuModel{
|
|
.name = "pwr8",
|
|
.llvm_name = "pwr8",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.allow_unaligned_fp_access,
|
|
.altivec,
|
|
.bpermd,
|
|
.cmpb,
|
|
.crypto,
|
|
.direct_move,
|
|
.extdiv,
|
|
.fcpsgn,
|
|
.fpcvt,
|
|
.fprnd,
|
|
.fre,
|
|
.fres,
|
|
.frsqrte,
|
|
.frsqrtes,
|
|
.fsqrt,
|
|
.fuse_addi_load,
|
|
.fuse_addis_load,
|
|
.htm,
|
|
.icbt,
|
|
.isel,
|
|
.ldbrx,
|
|
.lfiwax,
|
|
.mfocrf,
|
|
.partword_atomics,
|
|
.popcntd,
|
|
.power8_altivec,
|
|
.power8_vector,
|
|
.predictable_select_expensive,
|
|
.recipprec,
|
|
.stfiwx,
|
|
.two_const_nr,
|
|
.vsx,
|
|
}),
|
|
};
|
|
pub const pwr9 = CpuModel{
|
|
.name = "pwr9",
|
|
.llvm_name = "pwr9",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.allow_unaligned_fp_access,
|
|
.altivec,
|
|
.bpermd,
|
|
.cmpb,
|
|
.crypto,
|
|
.direct_move,
|
|
.extdiv,
|
|
.fcpsgn,
|
|
.fpcvt,
|
|
.fprnd,
|
|
.fre,
|
|
.fres,
|
|
.frsqrte,
|
|
.frsqrtes,
|
|
.fsqrt,
|
|
.htm,
|
|
.icbt,
|
|
.isa_v30_instructions,
|
|
.isel,
|
|
.ldbrx,
|
|
.lfiwax,
|
|
.mfocrf,
|
|
.partword_atomics,
|
|
.popcntd,
|
|
.power8_altivec,
|
|
.power8_vector,
|
|
.power9_altivec,
|
|
.power9_vector,
|
|
.ppc_postra_sched,
|
|
.ppc_prera_sched,
|
|
.predictable_select_expensive,
|
|
.recipprec,
|
|
.stfiwx,
|
|
.two_const_nr,
|
|
.vectors_use_two_units,
|
|
.vsx,
|
|
}),
|
|
};
|
|
};
|